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1//===-- X86InstrUtils.td - X86 Instruction Utilities --------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides utilities for simplifying the instruction definitions.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Classes for setting the fields of X86Inst15//===----------------------------------------------------------------------===//16 17// Prefix byte classes which are used to indicate to the ad-hoc machine code18// emitter that various prefix bytes are required.19class OpSize16 { OperandSize OpSize = OpSize16; }20class OpSize32 { OperandSize OpSize = OpSize32; }21class AdSize16 { AddressSize AdSize = AdSize16; }22class AdSize32 { AddressSize AdSize = AdSize32; }23class AdSize64 { AddressSize AdSize = AdSize64; }24class REX_W { bit hasREX_W = 1; }25class LOCK { bit hasLockPrefix = 1; }26class REP { bit hasREPPrefix = 1; }27class TB { Map OpMap = TB; }28class T8 { Map OpMap = T8; }29class TA { Map OpMap = TA; }30class T_MAP4 { Map OpMap = T_MAP4; }31class T_MAP5 { Map OpMap = T_MAP5; }32class T_MAP6 { Map OpMap = T_MAP6; }33class T_MAP7 { Map OpMap = T_MAP7; }34class XOP8 { Map OpMap = XOP8; }35class XOP9 { Map OpMap = XOP9; }36class XOPA { Map OpMap = XOPA; }37class ThreeDNow { Map OpMap = ThreeDNow; }38class PS { Prefix OpPrefix = PS; }39class PD { Prefix OpPrefix = PD; }40class XD { Prefix OpPrefix = XD; }41class XS { Prefix OpPrefix = XS; }42class XOP { Encoding OpEnc = EncXOP; }43class VEX { Encoding OpEnc = EncVEX; }44class EVEX { Encoding OpEnc = EncEVEX; }45class WIG { bit IgnoresW = 1; }46class VEX_L { bit hasVEX_L = 1; }47class VEX_LIG { bit ignoresVEX_L = 1; }48class VVVV { bit hasVEX_4V = 1; }49class EVEX_K { bit hasEVEX_K = 1; }50class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }51class EVEX_B { bit hasEVEX_B = 1; }52class EVEX_NF { bit hasEVEX_NF = 1; }53class EVEX_RC { bit hasEVEX_RC = 1; }54class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }55class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }56class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }57class NOTRACK { bit hasNoTrackPrefix = 1; }58class SIMD_EXC { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; }59// Specify AVX512 8-bit compressed displacement encoding based on the vector60// element size in bits (8, 16, 32, 64) and the CDisp8 form.61class EVEX_CD8<int esize, CD8VForm form> {62 int CD8_EltSize = !srl(esize, 3);63 bits<3> CD8_Form = form.Value;64}65class NoCD8 { bits<7> CD8_Scale = 0; }66 67class AVX512BIi8Base : TB, PD {68 Domain ExeDomain = SSEPackedInt;69 ImmType ImmT = Imm8;70}71class AVX512XSIi8Base : TB, XS {72 Domain ExeDomain = SSEPackedInt;73 ImmType ImmT = Imm8;74}75class AVX512XDIi8Base : TB, XD {76 Domain ExeDomain = SSEPackedInt;77 ImmType ImmT = Imm8;78}79class AVX512PSIi8Base : TB {80 Domain ExeDomain = SSEPackedSingle;81 ImmType ImmT = Imm8;82}83class AVX512PDIi8Base : TB, PD {84 Domain ExeDomain = SSEPackedDouble;85 ImmType ImmT = Imm8;86}87class ExplicitREX2Prefix { ExplicitOpPrefix explicitOpPrefix = ExplicitREX2; }88class ExplicitVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitVEX; }89class ExplicitEVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitEVEX; }90class DefEFLAGS { list<Register> Defs = [EFLAGS]; }91class UseEFLAGS { list<Register> Uses = [EFLAGS]; }92class DisassembleOnly {93 // The disassembler should know about this, but not the asmparser.94 bit isCodeGenOnly = 1;95 bit ForceDisassemble = 1;96}97 98defvar unaryop_args = "$src1";99defvar unaryop_ndd_args = "{$src1, $dst|$dst, $src1}";100defvar binop_args = "{$src2, $src1|$src1, $src2}";101defvar binop_ndd_args = "{$src2, $src1, $dst|$dst, $src1, $src2}";102defvar binop_cl_args = "{%cl, $src1|$src1, cl}";103defvar binop_cl_ndd_args = "{%cl, $src1, $dst|$dst, $src1, cl}";104defvar triop_args = "{$src3, $src2, $src1|$src1, $src2, $src3}";105defvar triop_ndd_args = "{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}";106defvar triop_cl_args = "{%cl, $src2, $src1|$src1, $src2, cl}";107defvar triop_cl_ndd_args = "{%cl, $src2, $src1, $dst|$dst, $src1, $src2, cl}";108defvar tie_dst_src1 = "$src1 = $dst";109 110// NDD - Helper for new data destination instructions111class NDD<bit ndd> {112 string Constraints = !if(!eq(ndd, 0), tie_dst_src1, "");113 Encoding OpEnc = !if(!eq(ndd, 0), EncNormal, EncEVEX);114 bit hasEVEX_B = ndd;115 bit hasVEX_4V = ndd;116 Map OpMap = !if(!eq(ndd, 0), OB, T_MAP4);117}118// NF - Helper for NF (no flags update) instructions119class NF: T_MAP4, EVEX, EVEX_NF;120// PL - Helper for promoted legacy instructions121class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;122// ZU - Helper for Zero Upper instructions123class ZU: T_MAP4, EVEX, EVEX_B;124 125//===----------------------------------------------------------------------===//126// X86 Type infomation definitions127//===----------------------------------------------------------------------===//128 129/// X86TypeInfo - This is a bunch of information that describes relevant X86130/// information about value types. For example, it can tell you what the131/// register class and preferred load to use.132class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,133 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,134 Operand immoperand, SDPatternOperator immoperator,135 SDPatternOperator immnosuoperator, Operand imm8operand,136 SDPatternOperator imm8operator, SDPatternOperator imm8nosuoperator,137 bit hasEvenOpcode, bit hasREX_W> {138 /// VT - This is the value type itself.139 ValueType VT = vt;140 141 /// InstrSuffix - This is the suffix used on instructions with this type. For142 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".143 string InstrSuffix = instrsuffix;144 145 /// RegClass - This is the register class associated with this type. For146 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.147 RegisterClass RegClass = regclass;148 149 /// LoadNode - This is the load node associated with this type. For150 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.151 PatFrag LoadNode = loadnode;152 153 /// MemOperand - This is the memory operand associated with this type. For154 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.155 X86MemOperand MemOperand = memoperand;156 157 /// ImmEncoding - This is the encoding of an immediate of this type. For158 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32159 /// since the immediate fields of i64 instructions is a 32-bit sign extended160 /// value.161 ImmType ImmEncoding = immkind;162 163 /// ImmOperand - This is the operand kind of an immediate of this type. For164 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->165 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign166 /// extended value.167 Operand ImmOperand = immoperand;168 169 /// ImmOperator - This is the operator that should be used to match an170 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).171 SDPatternOperator ImmOperator = immoperator;172 173 SDPatternOperator ImmNoSuOperator = immnosuoperator;174 175 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.176 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is177 /// only used for instructions that have a sign-extended imm8 field form.178 Operand Imm8Operand = imm8operand;179 180 /// Imm8Operator - This is the operator that should be used to match an 8-bit181 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).182 SDPatternOperator Imm8Operator = imm8operator;183 184 SDPatternOperator Imm8NoSuOperator = imm8nosuoperator;185 186 /// HasEvenOpcode - This bit is true if the instruction should have an even (as187 /// opposed to odd) opcode. Operations on i8 are even, operations on188 /// other datatypes are usually odd.189 bit HasEvenOpcode = hasEvenOpcode;190 191 /// HasREX_W - This bit is set to true if the instruction should have192 /// the 0x40 REX prefix. This is set for i64 types.193 bit HasREX_W = hasREX_W;194}195 196def Xi8 : X86TypeInfo<i8, "b", GR8, loadi8, i8mem, Imm8, i8imm,197 imm_su, imm, i8imm, null_frag, null_frag,198 1, 0>;199def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, Imm16, i16imm,200 imm_su, imm, i16i8imm, i16immSExt8_su, i16immSExt8,201 0, 0>;202def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm,203 imm_su, imm, i32i8imm, i32immSExt8_su, i32immSExt8,204 0, 0>;205def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, Imm32S, i64i32imm,206 i64immSExt32_su, i64immSExt32, i64i8imm, i64immSExt8_su,207 i64immSExt8, 0, 1>;208 209// Group template arguments that can be derived from the vector type (EltNum x210// EltVT). These are things like the register class for the writemask, etc.211// The idea is to pass one of these as the template argument rather than the212// individual arguments.213// The template is also used for scalar types, in this case numelts is 1.214class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,215 string suffix = ""> {216 RegisterClass RC = rc;217 ValueType EltVT = eltvt;218 int NumElts = numelts;219 220 // Corresponding mask register class.221 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);222 223 // Corresponding mask register pair class.224 RegisterOperand KRPC = !if (!gt(NumElts, 16), ?,225 !cast<RegisterOperand>("VK" # NumElts # "Pair"));226 227 // Corresponding write-mask register class.228 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");229 230 // The mask VT.231 ValueType KVT = !cast<ValueType>("v" # NumElts # "i1");232 233 // Suffix used in the instruction mnemonic.234 string Suffix = suffix;235 236 // VTName is a string name for vector VT. For vector types it will be237 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32238 // It is a little bit complex for scalar types, where NumElts = 1.239 // In this case we build v4f32 or v2f64240 string VTName = "v" # !if (!eq (NumElts, 1),241 !if (!eq (EltVT.Size, 16), 8,242 !if (!eq (EltVT.Size, 32), 4,243 !if (!eq (EltVT.Size, 64), 2, NumElts))), NumElts) # EltVT;244 245 // The vector VT.246 ValueType VT = !cast<ValueType>(VTName);247 248 string EltTypeName = !cast<string>(EltVT);249 // Size of the element type in bits, e.g. 32 for v16i32.250 string EltSizeName = !subst("i", "", !subst("f", "", !subst("b", "", EltTypeName)));251 int EltSize = EltVT.Size;252 253 // "i" for integer types and "f" for floating-point types254 string TypeVariantName = !subst("b", "", !subst(EltSizeName, "", EltTypeName));255 256 // Size of RC in bits, e.g. 512 for VR512.257 int Size = VT.Size;258 259 // The corresponding memory operand, e.g. i512mem for VR512.260 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");261 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(!subst("b", "", EltTypeName) # "mem");262 // FP scalar memory operand for intrinsics - ssmem/sdmem.263 Operand IntScalarMemOp = !if (!eq (EltTypeName, "f16"), !cast<Operand>("shmem"),264 !if (!eq (EltTypeName, "bf16"), !cast<Operand>("shmem"),265 !if (!eq (EltTypeName, "f32"), !cast<Operand>("ssmem"),266 !if (!eq (EltTypeName, "f64"), !cast<Operand>("sdmem"), ?))));267 268 // Load patterns269 PatFrag LdFrag = !cast<PatFrag>("load" # VTName);270 271 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" # VTName);272 273 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # !subst("b", "", EltTypeName));274 PatFrag BroadcastLdFrag = !cast<PatFrag>("X86VBroadcastld" # EltSizeName);275 276 PatFrags ScalarIntMemFrags = !if (!eq (EltTypeName, "f16"), !cast<PatFrags>("sse_load_f16"),277 !if (!eq (EltTypeName, "bf16"), !cast<PatFrags>("sse_load_f16"),278 !if (!eq (EltTypeName, "f32"), !cast<PatFrags>("sse_load_f32"),279 !if (!eq (EltTypeName, "f64"), !cast<PatFrags>("sse_load_f64"), ?))));280 281 // The string to specify embedded broadcast in assembly.282 string BroadcastStr = "{1to" # NumElts # "}";283 284 // 8-bit compressed displacement tuple/subvector format. This is only285 // defined for NumElts <= 8.286 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),287 !cast<CD8VForm>("CD8VT" # NumElts), ?);288 289 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,290 !if (!eq (Size, 256), sub_ymm, ?));291 292 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,293 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,294 !if (!eq (EltTypeName, "f16"), SSEPackedSingle, // FIXME?295 !if (!eq (EltTypeName, "bf16"), SSEPackedSingle, // FIXME?296 SSEPackedInt))));297 298 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X,299 !if (!eq (EltTypeName, "f16"), FR16X,300 !if (!eq (EltTypeName, "bf16"), FR16X,301 FR64X)));302 303 dag ImmAllZerosV = (VT immAllZerosV);304 305 string ZSuffix = !if (!eq (Size, 128), "Z128",306 !if (!eq (Size, 256), "Z256", "Z"));307}308 309def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;310def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;311def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;312def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;313def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">;314def v32bf16_info: X86VectorVTInfo<32, bf16, VR512, "bf16">;315def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;316def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;317 318// "x" in v32i8x_info means RC = VR256X319def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;320def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;321def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;322def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;323def v16f16x_info : X86VectorVTInfo<16, f16, VR256X, "ph">;324def v16bf16x_info: X86VectorVTInfo<16, bf16, VR256X, "bf16">;325def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;326def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;327 328def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;329def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;330def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;331def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;332def v8f16x_info : X86VectorVTInfo<8, f16, VR128X, "ph">;333def v8bf16x_info : X86VectorVTInfo<8, bf16, VR128X, "bf16">;334def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;335def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;336 337// We map scalar types to the smallest (128-bit) vector type338// with the appropriate element type. This allows to use the same masking logic.339def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;340def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;341def f16x_info : X86VectorVTInfo<1, f16, VR128X, "sh">;342def bf16x_info : X86VectorVTInfo<1, bf16, VR128X, "sbf">;343def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;344def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;345 346class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,347 X86VectorVTInfo i128> {348 X86VectorVTInfo info512 = i512;349 X86VectorVTInfo info256 = i256;350 X86VectorVTInfo info128 = i128;351}352 353def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,354 v16i8x_info>;355def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,356 v8i16x_info>;357def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,358 v4i32x_info>;359def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,360 v2i64x_info>;361def avx512vl_f16_info : AVX512VLVectorVTInfo<v32f16_info, v16f16x_info,362 v8f16x_info>;363def avx512vl_bf16_info : AVX512VLVectorVTInfo<v32bf16_info, v16bf16x_info,364 v8bf16x_info>;365def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,366 v4f32x_info>;367def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,368 v2f64x_info>;369 370class X86KVectorVTInfo<RegisterClass _krc, RegisterClass _krcwm,371 ValueType _vt> {372 RegisterClass KRC = _krc;373 RegisterClass KRCWM = _krcwm;374 ValueType KVT = _vt;375}376 377def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>;378def v2i1_info : X86KVectorVTInfo<VK2, VK2WM, v2i1>;379def v4i1_info : X86KVectorVTInfo<VK4, VK4WM, v4i1>;380def v8i1_info : X86KVectorVTInfo<VK8, VK8WM, v8i1>;381def v16i1_info : X86KVectorVTInfo<VK16, VK16WM, v16i1>;382def v32i1_info : X86KVectorVTInfo<VK32, VK32WM, v32i1>;383def v64i1_info : X86KVectorVTInfo<VK64, VK64WM, v64i1>;384 385// Subclasses of X86Inst386class PseudoI<dag oops, dag iops, list<dag> pattern>387 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {388 let Pattern = pattern;389}390 391class I<bits<8> o, Format f, dag outs, dag ins, string asm,392 list<dag> pattern, Domain d = GenericDomain>393 : X86Inst<o, f, NoImm, outs, ins, asm, d> {394 let Pattern = pattern;395}396class Ii8<bits<8> o, Format f, dag outs, dag ins, string asm,397 list<dag> pattern, Domain d = GenericDomain>398 : X86Inst<o, f, Imm8, outs, ins, asm, d> {399 let Pattern = pattern;400}401class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm,402 list<dag> pattern, Domain d = GenericDomain>403 : X86Inst<o, f, Imm8Reg, outs, ins, asm, d> {404 let Pattern = pattern;405}406class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,407 list<dag> pattern>408 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {409 let Pattern = pattern;410}411class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,412 list<dag> pattern>413 : X86Inst<o, f, Imm16, outs, ins, asm> {414 let Pattern = pattern;415}416class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,417 list<dag> pattern>418 : X86Inst<o, f, Imm32, outs, ins, asm> {419 let Pattern = pattern;420}421class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,422 list<dag> pattern>423 : X86Inst<o, f, Imm32S, outs, ins, asm> {424 let Pattern = pattern;425}426 427class Ii64<bits<8> o, Format f, dag outs, dag ins, string asm,428 list<dag> pattern>429 : X86Inst<o, f, Imm64, outs, ins, asm> {430 let Pattern = pattern;431}432 433class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,434 list<dag> pattern>435 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {436 let Pattern = pattern;437}438 439class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,440 list<dag> pattern>441 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {442 let Pattern = pattern;443}444 445// FPStack Instruction Templates:446// FPI - Floating Point Instruction template.447class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>448 : I<o, F, outs, ins, asm, []> {449 let Defs = [FPSW];450 let Predicates = [HasX87];451}452 453// FpI_ - Floating Point Pseudo Instruction template.454class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>455 : PseudoI<outs, ins, pattern> {456 let FPForm = fp;457 let Defs = [FPSW];458 let Predicates = [HasX87];459}460 461// Templates for instructions that use a 16- or 32-bit segmented address as462// their only operand: lcall (FAR CALL) and ljmp (FAR JMP)463//464// Iseg16 - 16-bit segment selector, 16-bit offset465// Iseg32 - 16-bit segment selector, 32-bit offset466 467class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,468 list<dag> pattern>469 : X86Inst<o, f, Imm16, outs, ins, asm> {470 let Pattern = pattern;471}472 473class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,474 list<dag> pattern>475 : X86Inst<o, f, Imm32, outs, ins, asm> {476 let Pattern = pattern;477}478 479// SI - SSE 1 & 2 scalar instructions480class SI<bits<8> o, Format F, dag outs, dag ins, string asm,481 list<dag> pattern, Domain d = GenericDomain>482 : I<o, F, outs, ins, asm, pattern, d> {483 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],484 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],485 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],486 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],487 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],488 [UseSSE1])))));489 490 // AVX instructions have a 'v' prefix in the mnemonic491 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),492 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),493 asm));494}495 496// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512497class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm,498 list<dag> pattern, Domain d = GenericDomain>499 : I<o, F, outs, ins, asm, pattern, d> {500 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],501 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],502 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],503 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],504 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],505 [UseSSE1])))));506 507 // AVX instructions have a 'v' prefix in the mnemonic508 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),509 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),510 asm));511}512// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512513class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,514 list<dag> pattern>515 : Ii8<o, F, outs, ins, asm, pattern> {516 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],517 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],518 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],519 [UseSSE2])));520 521 // AVX instructions have a 'v' prefix in the mnemonic522 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),523 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),524 asm));525}526 527// PI - SSE 1 & 2 packed instructions528class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,529 Domain d>530 : I<o, F, outs, ins, asm, pattern, d> {531 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],532 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],533 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],534 [UseSSE1])));535 536 // AVX instructions have a 'v' prefix in the mnemonic537 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),538 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),539 asm));540}541 542// MMXPI - SSE 1 & 2 packed instructions with MMX operands543class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,544 Domain d>545 : I<o, F, outs, ins, asm, pattern, d> {546 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2],547 [HasMMX, HasSSE1]);548}549 550// PIi8 - SSE 1 & 2 packed instructions with immediate551class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,552 list<dag> pattern, Domain d>553 : Ii8<o, F, outs, ins, asm, pattern, d> {554 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],555 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],556 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],557 [UseSSE1])));558 559 // AVX instructions have a 'v' prefix in the mnemonic560 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),561 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),562 asm));563}564 565// SSE1 Instruction Templates:566//567// SSI - SSE1 instructions with XS prefix.568// PSI - SSE1 instructions with PS prefix.569// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.570// VSSI - SSE1 instructions with XS prefix in AVX form.571// VPSI - SSE1 instructions with PS prefix in AVX form, packed single.572 573class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,574 list<dag> pattern>575 : I<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE1]>;576class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,577 list<dag> pattern>578 : Ii8<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE1]>;579class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,580 list<dag> pattern>581 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,582 Requires<[UseSSE1]>;583class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,584 list<dag> pattern>585 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,586 Requires<[UseSSE1]>;587class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,588 list<dag> pattern>589 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, XS,590 Requires<[HasAVX]>;591class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,592 list<dag> pattern>593 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,594 TB, Requires<[HasAVX]>;595 596// SSE2 Instruction Templates:597//598// SDI - SSE2 instructions with XD prefix.599// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.600// S2SI - SSE2 instructions with XS prefix.601// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.602// PDI - SSE2 instructions with PD prefix, packed double domain.603// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.604// VSDI - SSE2 scalar instructions with XD prefix in AVX form.605// VPDI - SSE2 vector instructions with PD prefix in AVX form,606// packed double domain.607// VS2I - SSE2 scalar instructions with PD prefix in AVX form.608// S2I - SSE2 scalar instructions with PD prefix.609// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as610// MMX operands.611// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as612// MMX operands.613 614class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,615 list<dag> pattern>616 : I<o, F, outs, ins, asm, pattern>, TB, XD, Requires<[UseSSE2]>;617class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,618 list<dag> pattern>619 : Ii8<o, F, outs, ins, asm, pattern>, TB, XD, Requires<[UseSSE2]>;620class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,621 list<dag> pattern>622 : I<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE2]>;623class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,624 list<dag> pattern>625 : Ii8<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[UseSSE2]>;626class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,627 list<dag> pattern>628 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, PD,629 Requires<[UseSSE2]>;630class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,631 list<dag> pattern>632 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, PD,633 Requires<[UseSSE2]>;634class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,635 list<dag> pattern>636 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, XD,637 Requires<[UseAVX]>;638class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,639 list<dag> pattern>640 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, XS,641 Requires<[HasAVX]>;642class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,643 list<dag> pattern>644 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,645 TB, PD, Requires<[HasAVX]>;646class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,647 list<dag> pattern>648 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, PD,649 Requires<[UseAVX]>;650class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,651 list<dag> pattern>652 : I<o, F, outs, ins, asm, pattern>, TB, PD, Requires<[UseSSE2]>;653class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,654 list<dag> pattern>655 : Ii8<o, F, outs, ins, asm, pattern>, TB, XD, Requires<[HasMMX, HasSSE2]>;656class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,657 list<dag> pattern>658 : Ii8<o, F, outs, ins, asm, pattern>, TB, XS, Requires<[HasMMX, HasSSE2]>;659 660// SSE3 Instruction Templates:661//662// S3I - SSE3 instructions with PD prefixes.663// S3SI - SSE3 instructions with XS prefix.664// S3DI - SSE3 instructions with XD prefix.665 666class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,667 list<dag> pattern>668 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB, XS,669 Requires<[UseSSE3]>;670class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,671 list<dag> pattern>672 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, XD,673 Requires<[UseSSE3]>;674class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,675 list<dag> pattern>676 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, PD,677 Requires<[UseSSE3]>;678 679 680// SSSE3 Instruction Templates:681//682// SS38I - SSSE3 instructions with T8 prefix.683// SS3AI - SSSE3 instructions with TA prefix.684// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.685// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.686//687// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version688// uses the MMX registers. The 64-bit versions are grouped with the MMX689// classes. They need to be enabled even if AVX is enabled.690 691class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,692 list<dag> pattern>693 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,694 Requires<[UseSSSE3]>;695class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,696 list<dag> pattern>697 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,698 Requires<[UseSSSE3]>;699class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,700 list<dag> pattern>701 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,702 Requires<[HasMMX, HasSSSE3]>;703class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,704 list<dag> pattern>705 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,706 Requires<[HasMMX, HasSSSE3]>;707 708// SSE4.1 Instruction Templates:709//710// SS48I - SSE 4.1 instructions with T8 prefix.711// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.712//713class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,714 list<dag> pattern>715 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,716 Requires<[UseSSE41]>;717class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,718 list<dag> pattern>719 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,720 Requires<[UseSSE41]>;721 722// SSE4.2 Instruction Templates:723//724// SS428I - SSE 4.2 instructions with T8 prefix.725class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,726 list<dag> pattern>727 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,728 Requires<[UseSSE42]>;729 730// SS42AI = SSE 4.2 instructions with TA prefix731class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,732 list<dag> pattern>733 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,734 Requires<[UseSSE42]>;735 736// AVX Instruction Templates:737// Instructions introduced in AVX (no SSE equivalent forms)738//739// AVX8I - AVX instructions with T8, PD prefix.740// AVXAIi8 - AVX instructions with TA, PD prefix and ImmT = Imm8.741class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,742 list<dag> pattern>743 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,744 Requires<[HasAVX]>;745class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,746 list<dag> pattern>747 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,748 Requires<[HasAVX]>;749 750// AVX2 Instruction Templates:751// Instructions introduced in AVX2 (no SSE equivalent forms)752//753// AVX28I - AVX2 instructions with T8, PD prefix.754// AVX2AIi8 - AVX2 instructions with TA, PD prefix and ImmT = Imm8.755class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,756 list<dag> pattern>757 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,758 Requires<[HasAVX2]>;759class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,760 list<dag> pattern>761 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,762 Requires<[HasAVX2]>;763 764 765// AVX-512 Instruction Templates:766// Instructions introduced in AVX-512 (no SSE equivalent forms)767//768// AVX5128I - AVX-512 instructions with T8, PD prefix.769// AVX512AIi8 - AVX-512 instructions with TA, PD prefix and ImmT = Imm8.770// AVX512PDI - AVX-512 instructions with PD, double packed.771// AVX512PSI - AVX-512 instructions with PS, single packed.772// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.773// AVX512XSI - AVX-512 instructions with XS prefix, generic domain.774// AVX512BI - AVX-512 instructions with PD, int packed domain.775// AVX512SI - AVX-512 scalar instructions with PD prefix.776 777class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,778 list<dag> pattern>779 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,780 Requires<[HasAVX512]>;781class AVX5128IBase : T8, PD {782 Domain ExeDomain = SSEPackedInt;783}784class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,785 list<dag> pattern>786 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, XS,787 Requires<[HasAVX512]>;788class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,789 list<dag> pattern>790 : I<o, F, outs, ins, asm, pattern>, TB, XS,791 Requires<[HasAVX512]>;792class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,793 list<dag> pattern>794 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, TB, XD,795 Requires<[HasAVX512]>;796class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,797 list<dag> pattern>798 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, TB, PD,799 Requires<[HasAVX512]>;800class AVX512BIBase : TB, PD {801 Domain ExeDomain = SSEPackedInt;802}803class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,804 list<dag> pattern>805 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TB, PD,806 Requires<[HasAVX512]>;807class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,808 list<dag> pattern>809 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,810 Requires<[HasAVX512]>;811class AVX512AIi8Base : TA, PD {812 ImmType ImmT = Imm8;813}814class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,815 list<dag> pattern>816 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>,817 Requires<[HasAVX512]>;818class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,819 list<dag> pattern>820 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, PD,821 Requires<[HasAVX512]>;822class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,823 list<dag> pattern>824 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,825 Requires<[HasAVX512]>;826class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,827 list<dag> pattern, Domain d>828 : Ii8<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>;829class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,830 list<dag> pattern, Domain d>831 : I<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>;832class AVX512FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm,833 list<dag>pattern>834 : I<o, F, outs, ins, asm, pattern>, T8, PD,835 EVEX, VVVV, Requires<[HasAVX512]>;836 837class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,838 list<dag>pattern>839 : I<o, F, outs, ins, asm, pattern>, Requires<[HasAVX512]>;840 841// AES Instruction Templates:842//843// AES8I844// These use the same encoding as the SSE4.2 T8 and TA encodings.845class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,846 list<dag>pattern>847 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, PD,848 Requires<[NoAVX, HasAES]>;849 850class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,851 list<dag> pattern>852 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,853 Requires<[NoAVX, HasAES]>;854 855// PCLMUL Instruction Templates856class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,857 list<dag>pattern>858 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD;859 860// FMA3 Instruction Templates861class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,862 list<dag>pattern>863 : I<o, F, outs, ins, asm, pattern>, T8, PD,864 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>;865class FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm,866 list<dag>pattern>867 : I<o, F, outs, ins, asm, pattern>, T8, PD,868 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>;869class FMA3S_Int<bits<8> o, Format F, dag outs, dag ins, string asm,870 list<dag>pattern>871 : I<o, F, outs, ins, asm, pattern>, T8, PD,872 VEX, VVVV, FMASC, Requires<[HasFMA, NoAVX512]>;873 874// FMA4 Instruction Templates875class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,876 list<dag>pattern>877 : Ii8Reg<o, F, outs, ins, asm, pattern>, TA, PD,878 VEX, VVVV, FMASC, Requires<[HasFMA4, NoVLX]>;879class FMA4S<bits<8> o, Format F, dag outs, dag ins, string asm,880 list<dag>pattern>881 : Ii8Reg<o, F, outs, ins, asm, pattern>, TA, PD,882 VEX, VVVV, FMASC, Requires<[HasFMA4, NoAVX512]>;883class FMA4S_Int<bits<8> o, Format F, dag outs, dag ins, string asm,884 list<dag>pattern>885 : Ii8Reg<o, F, outs, ins, asm, pattern>, TA, PD,886 VEX, VVVV, FMASC, Requires<[HasFMA4]>;887 888// XOP 2, 3 and 4 Operand Instruction Template889class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,890 list<dag> pattern>891 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>,892 XOP9, Requires<[HasXOP]>;893 894// XOP 2 and 3 Operand Instruction Templates with imm byte895class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,896 list<dag> pattern>897 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>,898 XOP8, Requires<[HasXOP]>;899// XOP 4 Operand Instruction Templates with imm byte900class IXOPi8Reg<bits<8> o, Format F, dag outs, dag ins, string asm,901 list<dag> pattern>902 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedDouble>,903 XOP8, Requires<[HasXOP]>;904 905// XOP 5 operand instruction (VEX encoding!)906class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,907 list<dag>pattern>908 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, PD,909 VEX, VVVV, Requires<[HasXOP]>;910 911// X86-64 Instruction templates...912//913 914class RI<bits<8> o, Format F, dag outs, dag ins, string asm,915 list<dag> pattern>916 : I<o, F, outs, ins, asm, pattern>, REX_W;917class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,918 list<dag> pattern>919 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;920class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,921 list<dag> pattern>922 : Ii16<o, F, outs, ins, asm, pattern>, REX_W;923class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,924 list<dag> pattern>925 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;926class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,927 list<dag> pattern>928 : Ii32S<o, F, outs, ins, asm, pattern>, REX_W;929class RIi64<bits<8> o, Format F, dag outs, dag ins, string asm,930 list<dag> pattern>931 : Ii64<o, F, outs, ins, asm, pattern>, REX_W;932 933class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,934 list<dag> pattern>935 : S2I<o, F, outs, ins, asm, pattern>, REX_W;936class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,937 list<dag> pattern>938 : VS2I<o, F, outs, ins, asm, pattern>, REX_W;939 940// MMX Instruction templates941//942// MMXI - MMX instructions with TB prefix.943// MMXRI - MMX instructions with TB prefix and REX.W.944// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.945class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,946 list<dag> pattern>947 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;948class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,949 list<dag> pattern>950 : I<o, F, outs, ins, asm, pattern>, TB, REX_W,951 Requires<[HasMMX,In64BitMode]>;952class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,953 list<dag> pattern>954 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;955 956/// ITy - This instruction base class takes the type info for the instruction.957/// Using this, it:958/// 1. Concatenates together the instruction mnemonic with the appropriate959/// suffix letter, a tab, and the arguments.960/// 2. Infers whether the instruction should have a 0x40 REX_W prefix.961/// 3. Infers whether the low bit of the opcode should be 0 (for i8 operations)962/// or 1 (for i16,i32,i64 operations).963class ITy<bits<8> o, Format f, X86TypeInfo t, dag outs, dag ins, string m,964 string args, list<dag> p>965 : I<{o{7}, o{6}, o{5}, o{4}, o{3}, o{2}, o{1},966 !if(!eq(t.HasEvenOpcode, 1), 0, o{0})}, f, outs, ins,967 !strconcat(m, "{", t.InstrSuffix, "}\t", args), p>, NoCD8 {968 let hasSideEffects = 0;969 let hasREX_W = t.HasREX_W;970 let IgnoresW = !if(!eq(t.VT, i8), 1, 0);971}972 973// BinOpRR - Instructions that read "reg, reg".974class BinOpRR<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>975 : ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,976 args, p>, Sched<[WriteALU]>;977// BinOpRR_F - Instructions that read "reg, reg" and write EFLAGS only.978class BinOpRR_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>979 : BinOpRR<o, m, binop_args, t, (outs),980 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,981 DefEFLAGS;982// BinOpRR_F_Rev - Reversed encoding of BinOpRR_F983class BinOpRR_F_Rev<bits<8> o, string m, X86TypeInfo t>984 : BinOpRR_F<o, m, t, null_frag>, DisassembleOnly {985 let Form = MRMSrcReg;986}987// BinOpRR_R - Instructions that read "reg, reg" and write "reg".988class BinOpRR_R<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>989 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,990 (outs t.RegClass:$dst), []>, NDD<ndd>;991// BinOpRR_R_Rev - Reversed encoding of BinOpRR_R992class BinOpRR_R_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>993 : BinOpRR_R<o, m, t, ndd>, DisassembleOnly {994 let Form = MRMSrcReg;995}996// BinOpRR_RF - Instructions that read "reg, reg", and write "reg", EFLAGS.997class BinOpRR_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>998 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,999 (outs t.RegClass:$dst),1000 [(set t.RegClass:$dst, EFLAGS,1001 (node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;1002// BinOpRR_RF_Rev - Reversed encoding of BinOpRR_RF.1003class BinOpRR_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>1004 : BinOpRR_RF<o, m, t, null_frag, ndd>, DisassembleOnly {1005 let Form = MRMSrcReg;1006}1007// BinOpRRF_RF - Instructions that read "reg, reg", write "reg" and read/write1008// EFLAGS.1009class BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>1010 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),1011 [(set t.RegClass:$dst, EFLAGS,1012 (node t.RegClass:$src1, t.RegClass:$src2,1013 EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {1014 let SchedRW = [WriteADC];1015}1016// BinOpRRF_RF_Rev - Reversed encoding of BinOpRRF_RF1017class BinOpRRF_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>1018 : BinOpRRF_RF<o, m, t, null_frag, ndd>, DisassembleOnly {1019 let Form = MRMSrcReg;1020}1021 1022// BinOpRM - Instructions that read "reg, [mem]".1023class BinOpRM<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>1024 : ITy<o, MRMSrcMem, t, out, (ins t.RegClass:$src1, t.MemOperand:$src2), m,1025 args, p>,1026 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]> {1027 let mayLoad = 1;1028}1029// BinOpRM_F - Instructions that read "reg, [mem]" and write EFLAGS only.1030class BinOpRM_F<bits<8> o, string m, X86TypeInfo t, SDNode node>1031 : BinOpRM<o, m, binop_args, t, (outs),1032 [(set EFLAGS, (node t.RegClass:$src1,1033 (t.LoadNode addr:$src2)))]>, DefEFLAGS;1034// BinOpRM_R - Instructions that read "reg, [mem]", and write "reg".1035class BinOpRM_R<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>1036 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),1037 []>, NDD<ndd>;1038// BinOpRM_RF - Instructions that read "reg, [mem]", and write "reg", EFLAGS.1039class BinOpRM_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>1040 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),1041 [(set t.RegClass:$dst, EFLAGS, (node t.RegClass:$src1,1042 (t.LoadNode addr:$src2)))]>, DefEFLAGS, NDD<ndd>;1043// BinOpRMF_RF - Instructions that read "reg, [mem]", write "reg" and read/write1044// EFLAGS.1045class BinOpRMF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>1046 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),1047 [(set t.RegClass:$dst, EFLAGS,1048 (node t.RegClass:$src1, (t.LoadNode addr:$src2), EFLAGS))]>,1049 DefEFLAGS, UseEFLAGS, NDD<ndd> {1050 let SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold,1051 // base, scale, index, offset, segment.1052 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,1053 // implicit register read.1054 WriteADC.ReadAfterFold];1055}1056 1057// BinOpRI - Instructions that read "reg, imm".1058class BinOpRI<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out, list<dag> p>1059 : ITy<o, f, t, out, (ins t.RegClass:$src1, t.ImmOperand:$src2), m,1060 args, p>, Sched<[WriteALU]> {1061 let ImmT = t.ImmEncoding;1062}1063// BinOpRI_F - Instructions that read "reg, imm" and write EFLAGS only.1064class BinOpRI_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,1065 Format f>1066 : BinOpRI<o, m, binop_args, t, f, (outs),1067 [(set EFLAGS, (node t.RegClass:$src1,1068 t.ImmOperator:$src2))]>, DefEFLAGS;1069// BinOpRI_R - Instructions that read "reg, imm" and write "reg".1070class BinOpRI_R<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>1071 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),1072 []>, NDD<ndd>;1073// BinOpRI8U_R - Instructions that read "reg, u8imm" and write "reg".1074class BinOpRI8U_R<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>1075 : ITy<0xC1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), m,1076 !if(!eq(ndd, 0), binop_args, binop_ndd_args),1077 [(set t.RegClass:$dst, (node t.RegClass:$src1, (i8 imm:$src2)))]>, NDD<ndd> {1078 let ImmT = Imm8;1079}1080// BinOpRI_RF - Instructions that read "reg, imm" and write "reg", EFLAGS.1081class BinOpRI_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f, bit ndd = 0>1082 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),1083 [(set t.RegClass:$dst, EFLAGS,1084 (node t.RegClass:$src1, t.ImmOperator:$src2))]>, DefEFLAGS, NDD<ndd>;1085// BinOpRIF_RF - Instructions that read "reg, imm", write "reg" and read/write1086// EFLAGS.1087class BinOpRIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f, bit ndd = 0>1088 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),1089 [(set t.RegClass:$dst, EFLAGS,1090 (node t.RegClass:$src1, t.ImmOperator:$src2,1091 EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {1092 let SchedRW = [WriteADC];1093}1094// BinOpRI8 - Instructions that read "reg, imm8".1095class BinOpRI8<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out>1096 : ITy<o, f, t, out, (ins t.RegClass:$src1, t.Imm8Operand:$src2), m,1097 args, []>, Sched<[WriteALU]> {1098 let ImmT = Imm8;1099}1100// BinOpRI8_F - Instructions that read "reg, imm8" and write EFLAGS only.1101class BinOpRI8_F<bits<8> o, string m, X86TypeInfo t, Format f>1102 : BinOpRI8<o, m, binop_args, t, f, (outs)>, DefEFLAGS;1103// BinOpRI8_R - Instructions that read "reg, imm8" and write "reg".1104class BinOpRI8_R<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>1105 : BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, NDD<ndd>;1106// BinOpRI8_RF - Instructions that read "reg, imm8" and write "reg", EFLAGS.1107class BinOpRI8_RF<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>1108 : BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefEFLAGS, NDD<ndd>;1109// BinOpRI8F_RF - Instructions that read "reg, imm", write "reg" and read/write1110// EFLAGS.1111class BinOpRI8F_RF<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>1112 : BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefEFLAGS, UseEFLAGS, NDD<ndd> {1113 let SchedRW = [WriteADC];1114}1115 1116// BinOpMR - Instructions that read "[mem], reg".1117class BinOpMR<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>1118 : ITy<o, MRMDestMem, t, out, (ins t.MemOperand:$src1, t.RegClass:$src2), m,1119 args, p> {1120 let mayLoad = 1;1121 let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold];1122}1123// BinOpMR_R - Instructions that read "[mem], reg", and write "reg".1124class BinOpMR_R<bits<8> o, string m, X86TypeInfo t>1125 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst), []>, NDD<1>;1126// BinOpMR_RF - Instructions that read "[mem], reg", and write "reg", EFLAGS.1127class BinOpMR_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>1128 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),1129 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1),1130 t.RegClass:$src2))]>, DefEFLAGS, NDD<1>;1131// BinOpMR_F - Instructions that read "[mem], imm8" and write EFLAGS only.1132class BinOpMR_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>1133 : BinOpMR<o, m, binop_args, t, (outs),1134 [(set EFLAGS, (node (t.LoadNode addr:$src1), t.RegClass:$src2))]>,1135 Sched<[WriteALU.Folded, ReadDefault, ReadDefault, ReadDefault,1136 ReadDefault, ReadDefault, WriteALU.ReadAfterFold]>, DefEFLAGS;1137// BinOpMR_M - Instructions that read "[mem], reg" and write "[mem]".1138class BinOpMR_M<bits<8> o, string m, X86TypeInfo t>1139 : BinOpMR<o, m, binop_args, t, (outs), []>,1140 Sched<[WriteALURMW,1141 // base, scale, index, offset, segment1142 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault]> {1143 let mayStore = 1;1144}1145// BinOpMR_MF - Instructions that read "[mem], reg" and write "[mem]", EFLAGS.1146class BinOpMR_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>1147 : BinOpMR<o, m, binop_args, t, (outs),1148 [(store (node (load addr:$src1), t.RegClass:$src2), addr:$src1)]>,1149 Sched<[WriteALURMW,1150 // base, scale, index, offset, segment1151 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,1152 WriteALU.ReadAfterFold]>, // reg1153 DefEFLAGS {1154 let mayStore = 1;1155}1156// BinOpMRF_RF - Instructions that read "[mem], reg", write "reg" and1157// read/write EFLAGS.1158class BinOpMRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>1159 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),1160 [(set t.RegClass:$dst, EFLAGS, (node (load addr:$src1),1161 t.RegClass:$src2, EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<1>,1162 Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>;1163// BinOpMRF_MF - Instructions that read "[mem], reg", write "[mem]" and1164// read/write EFLAGS.1165class BinOpMRF_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>1166 : BinOpMR<o, m, binop_args, t, (outs),1167 [(store (node (load addr:$src1), t.RegClass:$src2, EFLAGS),1168 addr:$src1)]>,1169 Sched<[WriteADCRMW,1170 // base, scale, index, offset, segment1171 ReadDefault, ReadDefault, ReadDefault,1172 ReadDefault, ReadDefault,1173 WriteALU.ReadAfterFold, // reg1174 WriteALU.ReadAfterFold]>, // EFLAGS1175 DefEFLAGS, UseEFLAGS {1176 let mayStore = 1;1177}1178 1179// BinOpMI - Instructions that read "[mem], imm".1180class BinOpMI<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out, list<dag> p>1181 : ITy<o, f, t, out, (ins t.MemOperand:$src1, t.ImmOperand:$src2), m,1182 args, p> {1183 let ImmT = t.ImmEncoding;1184 let mayLoad = 1;1185}1186// BinOpMI_F - Instructions that read "[mem], imm" and write EFLAGS only.1187class BinOpMI_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,1188 Format f>1189 : BinOpMI<o, m, binop_args, t, f, (outs),1190 [(set EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,1191 Sched<[WriteALU.Folded]>, DefEFLAGS;1192// BinOpMI_R - Instructions that read "[mem], imm" and write "reg".1193class BinOpMI_R<bits<8> o, string m, X86TypeInfo t, Format f>1194 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst), []>,1195 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;1196// BinOpMI_R - Instructions that read "[mem], imm" and write "reg", EFLAGS.1197class BinOpMI_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,1198 Format f>1199 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),1200 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,1201 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;1202// BinOpMI_M - Instructions that read "[mem], imm" and write "[mem]".1203class BinOpMI_M<bits<8> o, string m, X86TypeInfo t, Format f>1204 : BinOpMI<o, m, binop_args, t, f, (outs), []>, Sched<[WriteALURMW]> {1205 let mayStore = 1;1206}1207// BinOpMI_MF - Instructions that read "[mem], imm" and write "[mem]", EFLAGS.1208class BinOpMI_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f>1209 : BinOpMI<o, m, binop_args, t, f, (outs),1210 [(store (node (t.VT (load addr:$src1)),1211 t.ImmOperator:$src2), addr:$src1)]>,1212 Sched<[WriteALURMW]>, DefEFLAGS {1213 let mayStore = 1;1214}1215// BinOpMIF_RF - Instructions that read "[mem], imm", write "reg" and1216// read/write EFLAGS.1217class BinOpMIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>1218 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),1219 [(set t.RegClass:$dst, EFLAGS, (node (t.VT (load addr:$src1)),1220 t.ImmOperator:$src2, EFLAGS))]>,1221 Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;1222// BinOpMIF_MF - Instructions that read "[mem], imm", write "[mem]" and1223// read/write EFLAGS.1224class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>1225 : BinOpMI<o, m, binop_args, t, f, (outs),1226 [(store (node (t.VT (load addr:$src1)),1227 t.ImmOperator:$src2, EFLAGS), addr:$src1)]>,1228 Sched<[WriteADCRMW]>, DefEFLAGS, UseEFLAGS {1229 let mayStore = 1;1230}1231 1232// BinOpMI8 - Instructions that read "[mem], imm8".1233class BinOpMI8<string m, string args, X86TypeInfo t, Format f, dag out>1234 : ITy<0x83, f, t, out, (ins t.MemOperand:$src1, t.Imm8Operand:$src2), m,1235 args, []> {1236 let ImmT = Imm8;1237 let mayLoad = 1;1238}1239// BinOpMI8U - Instructions that read "[mem], u8imm".1240class BinOpMI8U<string m, string args, X86TypeInfo t, Format f, dag out, list<dag> p>1241 : ITy<0xC1, f, t, out, (ins t.MemOperand:$src1, u8imm:$src2), m, args, p> {1242 let ImmT = Imm8;1243 let mayLoad = 1;1244}1245// BinOpMI8_F - Instructions that read "[mem], imm8" and write EFLAGS only.1246class BinOpMI8_F<string m, X86TypeInfo t, Format f>1247 : BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALU.Folded]>, DefEFLAGS;1248// BinOpMI8_R - Instructions that read "[mem], imm8" and write "reg".1249class BinOpMI8_R<string m, X86TypeInfo t, Format f>1250 : BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;1251// BinOpMI8U_R - Instructions that read "[mem], u8imm" and write "reg".1252class BinOpMI8U_R<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag>1253 : BinOpMI8U<m, binop_ndd_args, t, f, (outs t.RegClass:$dst),1254 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), (i8 imm:$src2)))]>, NDD<1>;1255// BinOpMI8_RF - Instructions that read "[mem], imm8" and write "reg"/EFLAGS.1256class BinOpMI8_RF<string m, X86TypeInfo t, Format f>1257 : BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;1258// BinOpMI8_M - Instructions that read "[mem], imm8" and write "[mem]".1259class BinOpMI8_M<string m, X86TypeInfo t, Format f>1260 : BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALURMW]> {1261 let mayStore = 1;1262}1263// BinOpMI8U_M - Instructions that read "[mem], u8imm" and write "[mem]".1264class BinOpMI8U_M<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag>1265 : BinOpMI8U<m, binop_args, t, f, (outs),1266 [(store (node (t.LoadNode addr:$src1), (i8 imm:$src2)), addr:$src1)]> {1267 let mayStore = 1;1268}1269// BinOpMI8_MF - Instructions that read "[mem], imm8" and write "[mem]", EFLAGS.1270class BinOpMI8_MF<string m, X86TypeInfo t, Format f>1271 : BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALURMW]>, DefEFLAGS {1272 let mayStore = 1;1273}1274// BinOpMI8F_RF - Instructions that read "[mem], imm8", write "reg" and1275// read/write EFLAGS.1276class BinOpMI8F_RF<string m, X86TypeInfo t, Format f>1277 : BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>,1278 Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;1279// BinOpMI8F_MF - Instructions that read "[mem], imm8", write "[mem]" and1280// read/write EFLAGS.1281class BinOpMI8F_MF<string m, X86TypeInfo t, Format f>1282 : BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteADCRMW]>, DefEFLAGS, UseEFLAGS {1283 let mayStore = 1;1284}1285 1286// BinOpAI - Instructions that read "a-reg imm" (Accumulator register).1287class BinOpAI<bits<8> o, string m, X86TypeInfo t, Register areg, string args>1288 : ITy<o, RawFrm, t, (outs), (ins t.ImmOperand:$src), m, args, []>,1289 Sched<[WriteALU]> {1290 let ImmT = t.ImmEncoding;1291 let Uses = [areg];1292}1293// BinOpAI_F - Instructions that read "a-reg imm" and write EFLAGS only.1294class BinOpAI_F<bits<8> o, string m, X86TypeInfo t, Register areg, string args>1295 : BinOpAI<o, m, t, areg, args>, DefEFLAGS;1296 1297// BinOpAI_AF - Instructions that read "a-reg imm" and write a-reg/EFLAGS.1298class BinOpAI_AF<bits<8> o, string m, X86TypeInfo t, Register areg,1299 string args> : BinOpAI<o, m, t, areg, args> {1300 let Defs = [areg, EFLAGS];1301}1302// BinOpAIF_AF - Instructions that read "a-reg imm", write a-reg and read/write1303// EFLAGS.1304class BinOpAIF_AF<bits<8> o, string m, X86TypeInfo t, Register areg,1305 string args> : BinOpAI<o, m, t, areg, args> {1306 let Uses = [areg, EFLAGS];1307 let Defs = [areg, EFLAGS];1308 let SchedRW = [WriteADC];1309}1310// BinOpRC_R - Instructions that read "reg, cl" and write reg.1311class BinOpRC_R<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>1312 : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m,1313 !if(!eq(ndd, 0), binop_cl_args, binop_cl_ndd_args),1314 [(set t.RegClass:$dst, (node t.RegClass:$src1, CL))]>, NDD<ndd> {1315 let Uses = [CL];1316}1317// BinOpMC_M - Instructions that read "[mem], cl" and write [mem].1318class BinOpMC_M<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag>1319 : ITy<0xD3, f, t, (outs), (ins t.MemOperand:$src1), m, binop_cl_args,1320 [(store (node (t.LoadNode addr:$src1), CL), addr:$src1)]> {1321 let Uses = [CL];1322 let mayLoad = 1;1323 let mayStore = 1;1324}1325// BinOpMC_R - Instructions that read "[mem], cl" and write reg.1326class BinOpMC_R<string m, Format f, X86TypeInfo t, SDPatternOperator node = null_frag>1327 : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1), m, binop_cl_ndd_args,1328 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), CL))]>, NDD<1> {1329 let Uses = [CL];1330 let mayLoad = 1;1331}1332 1333// UnaryOpR - Instructions that read "reg".1334class UnaryOpR<bits<8> o, Format f, string m, string args, X86TypeInfo t,1335 dag out, list<dag> p>1336 : ITy<o, f, t, out, (ins t.RegClass:$src1), m, args, p>, Sched<[WriteALU]>;1337// UnaryOpR_R - Instructions that read "reg" and write "reg".1338class UnaryOpR_R<bits<8> o, Format f, string m, X86TypeInfo t,1339 SDPatternOperator node = null_frag, bit ndd = 0>1340 : UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, unaryop_ndd_args), t,1341 (outs t.RegClass:$dst),1342 [(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;1343// UnaryOpR_RF - Instructions that read "reg" and write "reg"/EFLAGS.1344class UnaryOpR_RF<bits<8> o, Format f, string m, X86TypeInfo t,1345 SDPatternOperator node = null_frag, bit ndd = 0>1346 : UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, unaryop_ndd_args), t,1347 (outs t.RegClass:$dst),1348 [(set t.RegClass:$dst, (node t.RegClass:$src1))]>,1349 DefEFLAGS, NDD<ndd>;1350 1351// UnaryOpM - Instructions that read "[mem]".1352class UnaryOpM<bits<8> o, Format f, string m, string args, X86TypeInfo t,1353 dag out, list<dag> p>1354 : ITy<o, f, t, out, (ins t.MemOperand:$src1), m, args, p> {1355 let mayLoad = 1;1356}1357// UnaryOpM_R - Instructions that read "[mem]" and writes "reg".1358class UnaryOpM_R<bits<8> o, Format f, string m, X86TypeInfo t,1359 SDPatternOperator node = null_frag>1360 : UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),1361 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1)))]>,1362 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;1363// UnaryOpM_RF - Instructions that read "[mem]" and writes "reg"/EFLAGS.1364class UnaryOpM_RF<bits<8> o, Format f, string m, X86TypeInfo t,1365 SDPatternOperator node = null_frag>1366 : UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),1367 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1)))]>,1368 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;1369// UnaryOpM_M - Instructions that read "[mem]" and writes "[mem]".1370class UnaryOpM_M<bits<8> o, Format f, string m, X86TypeInfo t,1371 SDPatternOperator node = null_frag>1372 : UnaryOpM<o, f, m, unaryop_args, t, (outs),1373 [(store (node (t.LoadNode addr:$src1)), addr:$src1)]>,1374 Sched<[WriteALURMW]>{1375 let mayStore = 1;1376}1377// UnaryOpM_MF - Instructions that read "[mem]" and writes "[mem]"/EFLAGS.1378class UnaryOpM_MF<bits<8> o, Format f, string m, X86TypeInfo t,1379 SDPatternOperator node = null_frag>1380 : UnaryOpM<o, f, m, unaryop_args, t, (outs),1381 [(store (node (t.LoadNode addr:$src1)), addr:$src1)]>,1382 Sched<[WriteALURMW]>, DefEFLAGS {1383 let mayStore = 1;1384}1385