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1//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This describes the available hardware counters for various subtargets.10//11//===----------------------------------------------------------------------===//12 13def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;14def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;15 16// No default counters on X86.17def DefaultPfmCounters : ProcPfmCounters {}18def : PfmCountersDefaultBinding<DefaultPfmCounters>;19 20// Intel X86 Counters.21defvar DefaultIntelPfmValidationCounters = [22 PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,23 PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">,24 PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,25 PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,26 PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,27 PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">,28 PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES">29];30 31def PentiumPfmCounters : ProcPfmCounters {32 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;33 let UopsCounter = PfmCounter<"uops_retired">;34}35def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>;36def : PfmCountersBinding<"pentium2", PentiumPfmCounters>;37def : PfmCountersBinding<"pentium3", PentiumPfmCounters>;38def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>;39def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>;40 41def CorePfmCounters : ProcPfmCounters {42 let CycleCounter = UnhaltedCoreCyclesPfmCounter;43 let UopsCounter = PfmCounter<"uops_retired:any">;44}45def : PfmCountersBinding<"yonah", CorePfmCounters>;46def : PfmCountersBinding<"prescott", CorePfmCounters>;47 48def AtomPfmCounters : ProcPfmCounters {49 let CycleCounter = UnhaltedCoreCyclesPfmCounter;50 let UopsCounter = PfmCounter<"uops_retired:any">;51}52def : PfmCountersBinding<"bonnell", AtomPfmCounters>;53def : PfmCountersBinding<"atom", AtomPfmCounters>;54 55def SLMPfmCounters : ProcPfmCounters {56 let CycleCounter = UnhaltedCoreCyclesPfmCounter;57 let UopsCounter = PfmCounter<"uops_retired:any">;58 let IssueCounters = [59 PfmIssueCounter<"SLM_MEC_RSV", "mem_uop_retired:any_ld + mem_uop_retired:any_st">60 ];61}62def : PfmCountersBinding<"silvermont", SLMPfmCounters>;63def : PfmCountersBinding<"goldmont", SLMPfmCounters>;64def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>;65def : PfmCountersBinding<"tremont", SLMPfmCounters>;66 67def KnightPfmCounters : ProcPfmCounters {68 let CycleCounter = UnhaltedCoreCyclesPfmCounter;69 let UopsCounter = PfmCounter<"uops_retired:all">;70}71def : PfmCountersBinding<"knl", KnightPfmCounters>;72def : PfmCountersBinding<"knm", KnightPfmCounters>;73 74def Core2PfmCounters : ProcPfmCounters {75 let CycleCounter = UnhaltedCoreCyclesPfmCounter;76 let UopsCounter = PfmCounter<"uops_retired:any">;77 let IssueCounters = [78 PfmIssueCounter<"SBPort0", "rs_uops_dispatched_cycles:port_0">,79 PfmIssueCounter<"SBPort1", "rs_uops_dispatched_cycles:port_1">,80 PfmIssueCounter<"SBPort23", "rs_uops_dispatched_cycles:port_2 + rs_uops_dispatched_cycles:port_3">,81 PfmIssueCounter<"SBPort4", "rs_uops_dispatched_cycles:port_4">,82 PfmIssueCounter<"SBPort5", "rs_uops_dispatched_cycles:port_5">83 ];84}85def : PfmCountersBinding<"core2", Core2PfmCounters>;86def : PfmCountersBinding<"penryn", Core2PfmCounters>;87 88def NehalemPfmCounters : ProcPfmCounters {89 let CycleCounter = UnhaltedCoreCyclesPfmCounter;90 let UopsCounter = PfmCounter<"uops_retired:any">;91 let IssueCounters = [92 PfmIssueCounter<"SBPort0", "uops_executed:port0">,93 PfmIssueCounter<"SBPort1", "uops_executed:port1">,94 PfmIssueCounter<"SBPort23", "uops_executed:port2_core + uops_executed:port3_core">,95 PfmIssueCounter<"SBPort4", "uops_executed:port4_core">,96 PfmIssueCounter<"SBPort5", "uops_executed:port5">97 ];98}99def : PfmCountersBinding<"nehalem", NehalemPfmCounters>;100def : PfmCountersBinding<"corei7", NehalemPfmCounters>;101def : PfmCountersBinding<"westmere", NehalemPfmCounters>;102 103def SandyBridgePfmCounters : ProcPfmCounters {104 let CycleCounter = UnhaltedCoreCyclesPfmCounter;105 let UopsCounter = UopsIssuedPfmCounter;106 let IssueCounters = [107 PfmIssueCounter<"SBPort0", "uops_dispatched_port:port_0">,108 PfmIssueCounter<"SBPort1", "uops_dispatched_port:port_1">,109 PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,110 PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">,111 PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5">112 ];113 let ValidationCounters = DefaultIntelPfmValidationCounters;114}115def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;116def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>;117 118def HaswellPfmCounters : ProcPfmCounters {119 let CycleCounter = UnhaltedCoreCyclesPfmCounter;120 let UopsCounter = UopsIssuedPfmCounter;121 let IssueCounters = [122 PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">,123 PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">,124 PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">,125 PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">,126 PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">,127 PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">,128 PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">,129 PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">130 ];131 let ValidationCounters = DefaultIntelPfmValidationCounters;132}133def : PfmCountersBinding<"haswell", HaswellPfmCounters>;134 135def BroadwellPfmCounters : ProcPfmCounters {136 let CycleCounter = UnhaltedCoreCyclesPfmCounter;137 let UopsCounter = UopsIssuedPfmCounter;138 let IssueCounters = [139 PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,140 PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,141 PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,142 PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,143 PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,144 PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,145 PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,146 PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">147 ];148 let ValidationCounters = DefaultIntelPfmValidationCounters;149}150def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;151 152def SkylakeClientPfmCounters : ProcPfmCounters {153 let CycleCounter = UnhaltedCoreCyclesPfmCounter;154 let UopsCounter = UopsIssuedPfmCounter;155 let IssueCounters = [156 PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,157 PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,158 PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,159 PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,160 PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,161 PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,162 PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,163 PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">164 ];165 let ValidationCounters = DefaultIntelPfmValidationCounters;166}167def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;168 169def SkylakeServerPfmCounters : ProcPfmCounters {170 let CycleCounter = UnhaltedCoreCyclesPfmCounter;171 let UopsCounter = UopsIssuedPfmCounter;172 let IssueCounters = [173 PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,174 PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,175 PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,176 PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,177 PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,178 PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,179 PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,180 PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">181 ];182 let ValidationCounters = DefaultIntelPfmValidationCounters;183}184def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;185def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;186def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;187 188def IceLakePfmCounters : ProcPfmCounters {189 let CycleCounter = UnhaltedCoreCyclesPfmCounter;190 let UopsCounter = UopsIssuedPfmCounter;191 let IssueCounters = [192 PfmIssueCounter<"ICXPort0", "uops_dispatched:port_0">,193 PfmIssueCounter<"ICXPort1", "uops_dispatched:port_1">,194 PfmIssueCounter<"ICXPort23", "uops_dispatched:port_2_3">,195 PfmIssueCounter<"ICXPort49", "uops_dispatched:port_4_9">,196 PfmIssueCounter<"ICXPort5", "uops_dispatched:port_5">,197 PfmIssueCounter<"ICXPort6", "uops_dispatched:port_6">,198 PfmIssueCounter<"ICXPort78", "uops_dispatched:port_7_8">199 ];200 let ValidationCounters = DefaultIntelPfmValidationCounters;201}202def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>;203def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;204def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;205def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;206 207def AlderLakePfmCounters : ProcPfmCounters {208 let CycleCounter = UnhaltedCoreCyclesPfmCounter;209 let UopsCounter = UopsIssuedPfmCounter;210 let IssueCounters = [211 PfmIssueCounter<"ADLPPort00", "uops_dispatched:port_0">,212 PfmIssueCounter<"ADLPPort01", "uops_dispatched:port_1">,213 PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched:port_2_3_10">,214 PfmIssueCounter<"ADLPPort04_09", "uops_dispatched:port_4_9">,215 PfmIssueCounter<"ADLPPort05_11", "uops_dispatched:port_5_11">,216 PfmIssueCounter<"ADLPPort06", "uops_dispatched:port_6">,217 PfmIssueCounter<"ADLPPort07_08", "uops_dispatched:port_7_8">218 ];219 let ValidationCounters = DefaultIntelPfmValidationCounters;220}221def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;222 223def SapphireRapidsPfmCounters : ProcPfmCounters {224 let CycleCounter = UnhaltedCoreCyclesPfmCounter;225 let UopsCounter = UopsIssuedPfmCounter;226 let IssueCounters = [227 PfmIssueCounter<"SPRPort00", "uops_dispatched:port_0">,228 PfmIssueCounter<"SPRPort01", "uops_dispatched:port_1">,229 PfmIssueCounter<"SPRPort02_03_10", "uops_dispatched:port_2_3_10">,230 PfmIssueCounter<"SPRPort04_09", "uops_dispatched:port_4_9">,231 PfmIssueCounter<"SPRPort05_11", "uops_dispatched:port_5_11">,232 PfmIssueCounter<"SPRPort06", "uops_dispatched:port_6">,233 PfmIssueCounter<"SPRPort07_08", "uops_dispatched:port_7_8">,234 ];235 let ValidationCounters = DefaultIntelPfmValidationCounters;236}237def : PfmCountersBinding<"sapphirerapids", SapphireRapidsPfmCounters>;238 239def LunarLakePfmCounters : ProcPfmCounters {240 let CycleCounter = UnhaltedCoreCyclesPfmCounter;241 let UopsCounter = UopsIssuedPfmCounter;242 let IssueCounters = [243 // Refer: https://perfmon-events.intel.com/ section Lunar Lake Hybrid Event244 // ALU Dispatch - Any of ALUs with latency 1 cycle that is not jmp or Shift.245 PfmIssueCounter<"LNLPVPort02_03", "uops_dispatched:alu">,246 PfmIssueCounter<"LNLPPort00_01_02_03_04_05", "uops_dispatched:int_eu_all">,247 PfmIssueCounter<"LNLPPort00_02_04", "uops_dispatched:jmp">,248 PfmIssueCounter<"LNLPPort20_21_22", "uops_dispatched:load">,249 PfmIssueCounter<"LNLPPort01_03_05", "uops_dispatched:shift">,250 // Slow Dispatch - If uops latency > 1, counted as slow. TBD251 // PfmIssueCounter<"LNLPPort01_03_05", "uops_dispatched:slow">,252 PfmIssueCounter<"LNLPPort25_26_27", "uops_dispatched:sta">,253 PfmIssueCounter<"LNLPPort10_11", "uops_dispatched:std">254 ];255 let ValidationCounters = DefaultIntelPfmValidationCounters;256}257def : PfmCountersBinding<"lunarlake", LunarLakePfmCounters>;258 259// AMD X86 Counters.260defvar DefaultAMDPfmValidationCounters = [261 PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,262 PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">,263 PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">,264 PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,265 PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">,266 PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">,267 PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES">268];269 270// Set basic counters for AMD cpus that we know libpfm4 supports.271def DefaultAMDPfmCounters : ProcPfmCounters {272 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;273 let UopsCounter = PfmCounter<"retired_uops">;274}275def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>;276def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>;277def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>;278def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>;279def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>;280def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>;281def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>;282def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>;283def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>;284def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>;285def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>;286def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>;287def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>;288def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>;289 290def BdVer2PfmCounters : ProcPfmCounters {291 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;292 let UopsCounter = PfmCounter<"retired_uops">;293 let IssueCounters = [294 PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,295 PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,296 PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">,297 PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3">298 ];299}300def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>;301def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>;302 303def BdVer3PfmCounters : ProcPfmCounters {304 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;305 let UopsCounter = PfmCounter<"retired_uops">;306 let IssueCounters = [307 PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,308 PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,309 PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">310 ];311}312def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>;313def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>;314 315def BtVer1PfmCounters : ProcPfmCounters {316 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;317 let UopsCounter = PfmCounter<"retired_uops">;318 let IssueCounters = [319 PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">,320 PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1">321 ];322}323def : PfmCountersBinding<"btver1", BtVer1PfmCounters>;324 325def BtVer2PfmCounters : ProcPfmCounters {326 let CycleCounter = PfmCounter<"cpu_clk_unhalted">;327 let UopsCounter = PfmCounter<"retired_uops">;328 let IssueCounters = [329 PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,330 PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">331 ];332}333def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;334 335def ZnVer1PfmCounters : ProcPfmCounters {336 let CycleCounter = PfmCounter<"cycles_not_in_halt">;337 let UopsCounter = PfmCounter<"retired_uops">;338 let IssueCounters = [339 PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,340 PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,341 PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,342 PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,343 PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,344 PfmIssueCounter<"ZnDivider", "div_op_count">345 ];346 let ValidationCounters = DefaultAMDPfmValidationCounters;347}348def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;349 350def ZnVer2PfmCounters : ProcPfmCounters {351 let CycleCounter = PfmCounter<"cycles_not_in_halt">;352 let UopsCounter = PfmCounter<"retired_uops">;353 let IssueCounters = [354 PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,355 PfmIssueCounter<"Zn2Divider", "div_op_count">356 ];357 let ValidationCounters = DefaultAMDPfmValidationCounters;358}359def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;360 361def ZnVer3PfmCounters : ProcPfmCounters {362 let CycleCounter = PfmCounter<"cycles_not_in_halt">;363 let UopsCounter = PfmCounter<"retired_ops">;364 let IssueCounters = [365 PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,366 PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,367 PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,368 PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,369 PfmIssueCounter<"Zn3Divider", "div_op_count">370 ];371 let ValidationCounters = DefaultAMDPfmValidationCounters;372}373def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;374 375def ZnVer4PfmCounters : ProcPfmCounters {376 let CycleCounter = PfmCounter<"cycles_not_in_halt">;377 let UopsCounter = PfmCounter<"retired_ops">;378 let IssueCounters = [379 PfmIssueCounter<"Zn4Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,380 PfmIssueCounter<"Zn4FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,381 PfmIssueCounter<"Zn4Load", "ls_dispatch:ld_dispatch">,382 PfmIssueCounter<"Zn4Store", "ls_dispatch:store_dispatch">,383 PfmIssueCounter<"Zn4Divider", "div_op_count">,384 PfmIssueCounter<"Zn4AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">385 ];386 let ValidationCounters = DefaultAMDPfmValidationCounters;387}388def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;389def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>;390