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1//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the X86 implementation of the TargetRegisterInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H14#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H15 16#include "llvm/CodeGen/MachineFunction.h"17#include "llvm/CodeGen/TargetRegisterInfo.h"18 19#define GET_REGINFO_HEADER20#include "X86GenRegisterInfo.inc"21 22namespace llvm {23 class Triple;24 25class X86RegisterInfo final : public X86GenRegisterInfo {26private:27 /// Is64Bit - Is the target 64-bits.28 ///29 bool Is64Bit;30 31 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?32 bool IsTarget64BitLP64;33 34 /// IsWin64 - Is the target on of win64 flavours35 ///36 bool IsWin64;37 38 /// IsUEFI64 - Is UEFI 64 bit target.39 ///40 bool IsUEFI64;41 42 /// SlotSize - Stack slot size in bytes.43 ///44 unsigned SlotSize;45 46 /// StackPtr - X86 physical register used as stack ptr.47 ///48 unsigned StackPtr;49 50 /// FramePtr - X86 physical register used as frame ptr.51 ///52 unsigned FramePtr;53 54 /// BasePtr - X86 physical register used as a base ptr in complex stack55 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to56 /// variable size stack objects.57 unsigned BasePtr;58 59public:60 explicit X86RegisterInfo(const Triple &TT);61 62 /// Return the number of registers for the function.63 unsigned getNumSupportedRegs(const MachineFunction &MF) const override;64 65 /// getMatchingSuperRegClass - Return a subclass of the specified register66 /// class A so that each register in it has a sub-register of the67 /// specified sub-register index which is in the specified register class B.68 const TargetRegisterClass *69 getMatchingSuperRegClass(const TargetRegisterClass *A,70 const TargetRegisterClass *B,71 unsigned Idx) const override;72 73 const TargetRegisterClass *74 getSubClassWithSubReg(const TargetRegisterClass *RC,75 unsigned Idx) const override;76 77 const TargetRegisterClass *78 getLargestLegalSuperClass(const TargetRegisterClass *RC,79 const MachineFunction &MF) const override;80 81 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer82 /// values.83 const TargetRegisterClass *84 getPointerRegClass(unsigned Kind = 0) const override;85 86 /// getCrossCopyRegClass - Returns a legal register class to copy a register87 /// in the specified class to or from. Returns NULL if it is possible to copy88 /// between a two registers of the specified class.89 const TargetRegisterClass *90 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;91 92 unsigned getRegPressureLimit(const TargetRegisterClass *RC,93 MachineFunction &MF) const override;94 95 /// getCalleeSavedRegs - Return a null-terminated list of all of the96 /// callee-save registers on this target.97 const MCPhysReg *98 getCalleeSavedRegs(const MachineFunction* MF) const override;99 /// getIPRACSRegs - This API can be removed when rbp is safe to optimized out100 /// when IPRA is on.101 const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;102 const MCPhysReg *103 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;104 const uint32_t *getCallPreservedMask(const MachineFunction &MF,105 CallingConv::ID) const override;106 const uint32_t *getNoPreservedMask() const override;107 108 // Calls involved in thread-local variable lookup save more registers than109 // normal calls, so they need a different mask to represent this.110 const uint32_t *getDarwinTLSCallPreservedMask() const;111 112 /// getReservedRegs - Returns a bitset indexed by physical register number113 /// indicating if a register is a special register that has particular uses and114 /// should be considered unavailable at all times, e.g. SP, RA. This is used by115 /// register scavenger to determine what registers are free.116 BitVector getReservedRegs(const MachineFunction &MF) const override;117 118 /// isArgumentReg - Returns true if Reg can be used as an argument to a119 /// function.120 bool isArgumentRegister(const MachineFunction &MF,121 MCRegister Reg) const override;122 123 /// Return true if it is tile register class.124 bool isTileRegisterClass(const TargetRegisterClass *RC) const;125 126 /// Returns true if PhysReg is a fixed register.127 bool isFixedRegister(const MachineFunction &MF,128 MCRegister PhysReg) const override;129 130 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;131 132 bool hasBasePointer(const MachineFunction &MF) const;133 134 bool canRealignStack(const MachineFunction &MF) const override;135 136 bool shouldRealignStack(const MachineFunction &MF) const override;137 138 void eliminateFrameIndex(MachineBasicBlock::iterator II,139 unsigned FIOperandNum, Register BaseReg,140 int FIOffset) const;141 142 bool eliminateFrameIndex(MachineBasicBlock::iterator MI,143 int SPAdj, unsigned FIOperandNum,144 RegScavenger *RS = nullptr) const override;145 146 /// Process frame indices in forwards block order because147 /// X86InstrInfo::getSPAdjust relies on it when searching for the148 /// ADJCALLSTACKUP pseudo following a call.149 /// TODO: Fix this and return true like all other targets.150 bool eliminateFrameIndicesBackwards() const override { return false; }151 152 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live153 /// when it reaches the "return" instruction. We can then pop a stack object154 /// to this register without worry about clobbering it.155 unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,156 MachineBasicBlock::iterator &MBBI) const;157 158 // Debug information queries.159 Register getFrameRegister(const MachineFunction &MF) const override;160 Register getPtrSizedFrameRegister(const MachineFunction &MF) const;161 Register getPtrSizedStackRegister(const MachineFunction &MF) const;162 Register getStackRegister() const { return StackPtr; }163 Register getBaseRegister() const { return BasePtr; }164 /// Returns physical register used as frame pointer.165 /// This will always returns the frame pointer register, contrary to166 /// getFrameRegister() which returns the "base pointer" in situations167 /// involving a stack, frame and base pointer.168 Register getFramePtr() const { return FramePtr; }169 // FIXME: Move to FrameInfok170 unsigned getSlotSize() const { return SlotSize; }171 172 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,173 SmallVectorImpl<MCPhysReg> &Hints,174 const MachineFunction &MF, const VirtRegMap *VRM,175 const LiveRegMatrix *Matrix) const override;176 177 const TargetRegisterClass *178 constrainRegClassToNonRex2(const TargetRegisterClass *RC) const;179 180 bool isNonRex2RegClass(const TargetRegisterClass *RC) const;181 182 bool requiresRegisterScavenging(const MachineFunction &MF) const override {183 return true;184 }185};186 187} // End llvm namespace188 189#endif190