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1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the X86 Register file, defining the registers themselves,10// aliases between the registers, and the register classes built out of the11// registers.12//13//===----------------------------------------------------------------------===//14 15class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {16 let Namespace = "X86";17 let HWEncoding = Enc;18 let SubRegs = subregs;19}20 21// Subregister indices.22let Namespace = "X86" in {23 def sub_8bit : SubRegIndex<8>;24 def sub_8bit_hi : SubRegIndex<8, 8>;25 def sub_8bit_hi_phony : SubRegIndex<8, 8>;26 def sub_16bit : SubRegIndex<16>;27 def sub_16bit_hi : SubRegIndex<16, 16>;28 def sub_32bit : SubRegIndex<32>;29 def sub_xmm : SubRegIndex<128>;30 def sub_ymm : SubRegIndex<256>;31 def sub_mask_0 : SubRegIndex<-1>;32 def sub_mask_1 : SubRegIndex<-1, -1>;33}34 35//===----------------------------------------------------------------------===//36// Register definitions...37//38 39// In the register alias definitions below, we define which registers alias40// which others. We only specify which registers the small registers alias,41// because the register file generator is smart enough to figure out that42// AL aliases AX if we tell it that AX aliased AL (for example).43 44// Dwarf numbering is different for 32-bit and 64-bit, and there are45// variations by target as well. Currently the first entry is for X86-64,46// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux47// and debug information on X86-32/Darwin)48 49// 8-bit registers50// Low registers51def AL : X86Reg<"al", 0>;52def DL : X86Reg<"dl", 2>;53def CL : X86Reg<"cl", 1>;54def BL : X86Reg<"bl", 3>;55 56// High registers. On x86-64, these cannot be used in any instruction57// with a REX prefix.58def AH : X86Reg<"ah", 4>;59def DH : X86Reg<"dh", 6>;60def CH : X86Reg<"ch", 5>;61def BH : X86Reg<"bh", 7>;62 63// X86-64 only, requires REX.64def SIL : X86Reg<"sil", 6>;65def DIL : X86Reg<"dil", 7>;66def BPL : X86Reg<"bpl", 5>;67def SPL : X86Reg<"spl", 4>;68def R8B : X86Reg<"r8b", 8>;69def R9B : X86Reg<"r9b", 9>;70def R10B : X86Reg<"r10b", 10>;71def R11B : X86Reg<"r11b", 11>;72def R12B : X86Reg<"r12b", 12>;73def R13B : X86Reg<"r13b", 13>;74def R14B : X86Reg<"r14b", 14>;75def R15B : X86Reg<"r15b", 15>;76// RAGreedy prefers to select a cheaper register77// For x86,78// Cost(caller-save reg) < Cost(callee-save reg)79// b/c callee-save register needs push/pop in prolog/epilog.80// If both registers are callee-saved or caller-saved,81// Cost(short-encoding reg) < Cost(long-encoding reg)82//83// To achieve this, we do the following things:84// 1. Set CostPerUse=1 for registers that need prefix85// 2. Consider callee-save register is never cheaper than a register w/ cost 186// 3. List caller-save register before callee-save regsiter in RegisterClass87// or AllocationOrder88//89// NOTE:90// D133902 stopped assigning register costs for R8-R15, which brought gain91// and regression. We don't know if we should assign cost to R16-R31 w/o92// performance data.93// TODO:94// Update the comment/cost after tuning.95// APX only, requires REX2 or EVEX.96let PositionOrder = 4 in {97def R16B : X86Reg<"r16b", 16>;98def R17B : X86Reg<"r17b", 17>;99def R18B : X86Reg<"r18b", 18>;100def R19B : X86Reg<"r19b", 19>;101def R20B : X86Reg<"r20b", 20>;102def R21B : X86Reg<"r21b", 21>;103def R22B : X86Reg<"r22b", 22>;104def R23B : X86Reg<"r23b", 23>;105def R24B : X86Reg<"r24b", 24>;106def R25B : X86Reg<"r25b", 25>;107def R26B : X86Reg<"r26b", 26>;108def R27B : X86Reg<"r27b", 27>;109def R28B : X86Reg<"r28b", 28>;110def R29B : X86Reg<"r29b", 29>;111def R30B : X86Reg<"r30b", 30>;112def R31B : X86Reg<"r31b", 31>;113}114 115let isArtificial = 1 in {116// High byte of the low 16 bits of the super-register:117def SIH : X86Reg<"", -1>;118def DIH : X86Reg<"", -1>;119def BPH : X86Reg<"", -1>;120def SPH : X86Reg<"", -1>;121def R8BH : X86Reg<"", -1>;122def R9BH : X86Reg<"", -1>;123def R10BH : X86Reg<"", -1>;124def R11BH : X86Reg<"", -1>;125def R12BH : X86Reg<"", -1>;126def R13BH : X86Reg<"", -1>;127def R14BH : X86Reg<"", -1>;128def R15BH : X86Reg<"", -1>;129let PositionOrder = 4 in {130def R16BH : X86Reg<"", -1>;131def R17BH : X86Reg<"", -1>;132def R18BH : X86Reg<"", -1>;133def R19BH : X86Reg<"", -1>;134def R20BH : X86Reg<"", -1>;135def R21BH : X86Reg<"", -1>;136def R22BH : X86Reg<"", -1>;137def R23BH : X86Reg<"", -1>;138def R24BH : X86Reg<"", -1>;139def R25BH : X86Reg<"", -1>;140def R26BH : X86Reg<"", -1>;141def R27BH : X86Reg<"", -1>;142def R28BH : X86Reg<"", -1>;143def R29BH : X86Reg<"", -1>;144def R30BH : X86Reg<"", -1>;145def R31BH : X86Reg<"", -1>;146}147// High word of the low 32 bits of the super-register:148def HAX : X86Reg<"", -1>;149def HDX : X86Reg<"", -1>;150def HCX : X86Reg<"", -1>;151def HBX : X86Reg<"", -1>;152def HSI : X86Reg<"", -1>;153def HDI : X86Reg<"", -1>;154def HBP : X86Reg<"", -1>;155def HSP : X86Reg<"", -1>;156def HIP : X86Reg<"", -1>;157def R8WH : X86Reg<"", -1>;158def R9WH : X86Reg<"", -1>;159def R10WH : X86Reg<"", -1>;160def R11WH : X86Reg<"", -1>;161def R12WH : X86Reg<"", -1>;162def R13WH : X86Reg<"", -1>;163def R14WH : X86Reg<"", -1>;164def R15WH : X86Reg<"", -1>;165let PositionOrder = 4 in {166def R16WH : X86Reg<"", -1>;167def R17WH : X86Reg<"", -1>;168def R18WH : X86Reg<"", -1>;169def R19WH : X86Reg<"", -1>;170def R20WH : X86Reg<"", -1>;171def R21WH : X86Reg<"", -1>;172def R22WH : X86Reg<"", -1>;173def R23WH : X86Reg<"", -1>;174def R24WH : X86Reg<"", -1>;175def R25WH : X86Reg<"", -1>;176def R26WH : X86Reg<"", -1>;177def R27WH : X86Reg<"", -1>;178def R28WH : X86Reg<"", -1>;179def R29WH : X86Reg<"", -1>;180def R30WH : X86Reg<"", -1>;181def R31WH : X86Reg<"", -1>;182}183}184 185// 16-bit registers186let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {187def AX : X86Reg<"ax", 0, [AL,AH]>;188def DX : X86Reg<"dx", 2, [DL,DH]>;189def CX : X86Reg<"cx", 1, [CL,CH]>;190def BX : X86Reg<"bx", 3, [BL,BH]>;191}192let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {193def SI : X86Reg<"si", 6, [SIL,SIH]>;194def DI : X86Reg<"di", 7, [DIL,DIH]>;195def BP : X86Reg<"bp", 5, [BPL,BPH]>;196def SP : X86Reg<"sp", 4, [SPL,SPH]>;197}198def IP : X86Reg<"ip", 0>;199 200// X86-64 only, requires REX.201let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {202def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>;203def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>;204def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>;205def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>;206def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>;207def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>;208def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>;209def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>;210}211// APX only, requires REX2 or EVEX.212let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {213let PositionOrder = 4 in {214def R16W : X86Reg<"r16w", 16, [R16B,R16BH]>;215def R17W : X86Reg<"r17w", 17, [R17B,R17BH]>;216def R18W : X86Reg<"r18w", 18, [R18B,R18BH]>;217def R19W : X86Reg<"r19w", 19, [R19B,R19BH]>;218def R20W : X86Reg<"r20w", 20, [R20B,R20BH]>;219def R21W : X86Reg<"r21w", 21, [R21B,R21BH]>;220def R22W : X86Reg<"r22w", 22, [R22B,R22BH]>;221def R23W : X86Reg<"r23w", 23, [R23B,R23BH]>;222def R24W : X86Reg<"r24w", 24, [R24B,R24BH]>;223def R25W : X86Reg<"r25w", 25, [R25B,R25BH]>;224def R26W : X86Reg<"r26w", 26, [R26B,R26BH]>;225def R27W : X86Reg<"r27w", 27, [R27B,R27BH]>;226def R28W : X86Reg<"r28w", 28, [R28B,R28BH]>;227def R29W : X86Reg<"r29w", 29, [R29B,R29BH]>;228def R30W : X86Reg<"r30w", 30, [R30B,R30BH]>;229def R31W : X86Reg<"r31w", 31, [R31B,R31BH]>;230}231}232 233// 32-bit registers234let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {235def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;236def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;237def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;238def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;239def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;240def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;241def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;242def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;243def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;244}245 246// X86-64 only, requires REX247let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {248def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>;249def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>;250def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>;251def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>;252def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>;253def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>;254def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>;255def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>;256}257 258// APX only, requires REX2 or EVEX.259let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {260let PositionOrder = 4 in {261def R16D : X86Reg<"r16d", 16, [R16W,R16WH]>;262def R17D : X86Reg<"r17d", 17, [R17W,R17WH]>;263def R18D : X86Reg<"r18d", 18, [R18W,R18WH]>;264def R19D : X86Reg<"r19d", 19, [R19W,R19WH]>;265def R20D : X86Reg<"r20d", 20, [R20W,R20WH]>;266def R21D : X86Reg<"r21d", 21, [R21W,R21WH]>;267def R22D : X86Reg<"r22d", 22, [R22W,R22WH]>;268def R23D : X86Reg<"r23d", 23, [R23W,R23WH]>;269def R24D : X86Reg<"r24d", 24, [R24W,R24WH]>;270def R25D : X86Reg<"r25d", 25, [R25W,R25WH]>;271def R26D : X86Reg<"r26d", 26, [R26W,R26WH]>;272def R27D : X86Reg<"r27d", 27, [R27W,R27WH]>;273def R28D : X86Reg<"r28d", 28, [R28W,R28WH]>;274def R29D : X86Reg<"r29d", 29, [R29W,R29WH]>;275def R30D : X86Reg<"r30d", 30, [R30W,R30WH]>;276def R31D : X86Reg<"r31d", 31, [R31W,R31WH]>;277}278}279// 64-bit registers, X86-64 only280let SubRegIndices = [sub_32bit] in {281def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;282def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;283def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;284def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;285def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;286def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;287def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;288def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;289 290// These also require REX.291def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;292def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;293def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;294def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;295def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;296def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;297def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;298def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;299def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;300// APX only, requires REX2 or EVEX.301let PositionOrder = 4 in {302def R16 : X86Reg<"r16", 16, [R16D]>, DwarfRegNum<[130, -2, -2]>;303def R17 : X86Reg<"r17", 17, [R17D]>, DwarfRegNum<[131, -2, -2]>;304def R18 : X86Reg<"r18", 18, [R18D]>, DwarfRegNum<[132, -2, -2]>;305def R19 : X86Reg<"r19", 19, [R19D]>, DwarfRegNum<[133, -2, -2]>;306def R20 : X86Reg<"r20", 20, [R20D]>, DwarfRegNum<[134, -2, -2]>;307def R21 : X86Reg<"r21", 21, [R21D]>, DwarfRegNum<[135, -2, -2]>;308def R22 : X86Reg<"r22", 22, [R22D]>, DwarfRegNum<[136, -2, -2]>;309def R23 : X86Reg<"r23", 23, [R23D]>, DwarfRegNum<[137, -2, -2]>;310def R24 : X86Reg<"r24", 24, [R24D]>, DwarfRegNum<[138, -2, -2]>;311def R25 : X86Reg<"r25", 25, [R25D]>, DwarfRegNum<[139, -2, -2]>;312def R26 : X86Reg<"r26", 26, [R26D]>, DwarfRegNum<[140, -2, -2]>;313def R27 : X86Reg<"r27", 27, [R27D]>, DwarfRegNum<[141, -2, -2]>;314def R28 : X86Reg<"r28", 28, [R28D]>, DwarfRegNum<[142, -2, -2]>;315def R29 : X86Reg<"r29", 29, [R29D]>, DwarfRegNum<[143, -2, -2]>;316def R30 : X86Reg<"r30", 30, [R30D]>, DwarfRegNum<[144, -2, -2]>;317def R31 : X86Reg<"r31", 31, [R31D]>, DwarfRegNum<[145, -2, -2]>;318}319}320 321// MMX Registers. These are actually aliased to ST0 .. ST7322def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;323def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;324def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;325def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;326def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;327def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;328def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;329def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;330 331// Pseudo Floating Point registers332def FP0 : X86Reg<"fp0", 0>;333def FP1 : X86Reg<"fp1", 0>;334def FP2 : X86Reg<"fp2", 0>;335def FP3 : X86Reg<"fp3", 0>;336def FP4 : X86Reg<"fp4", 0>;337def FP5 : X86Reg<"fp5", 0>;338def FP6 : X86Reg<"fp6", 0>;339def FP7 : X86Reg<"fp7", 0>;340 341// XMM Registers, used by the various SSE instruction set extensions.342def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;343def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;344def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;345def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;346def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;347def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;348def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;349def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;350 351// X86-64 only352def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;353def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;354def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;355def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;356def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;357def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;358def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;359def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;360 361let PositionOrder = 2 in {362// XMM16-31 registers, used by AVX-512 instructions.363def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>;364def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>;365def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>;366def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>;367def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>;368def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>;369def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>;370def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>;371def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>;372def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>;373def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>;374def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>;375def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>;376def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>;377def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>;378def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>;379}380 381// YMM0-15 registers, used by AVX instructions and382// YMM16-31 registers, used by AVX-512 instructions.383let SubRegIndices = [sub_xmm], PositionOrder = 1 in {384 foreach Index = 0-15 in {385 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,386 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;387 }388}389let SubRegIndices = [sub_xmm], PositionOrder = 2 in {390 foreach Index = 16-31 in {391 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,392 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;393 }394}395 396 397// ZMM Registers, used by AVX-512 instructions.398let SubRegIndices = [sub_ymm], PositionOrder = 2 in {399 foreach Index = 0-31 in {400 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,401 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;402 }403}404 405let PositionOrder = 2 in {406// Mask Registers, used by AVX-512 instructions.407def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>;408def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>;409def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>;410def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>;411def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>;412def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>;413def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>;414def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>;415// Mask register pairs416def KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1],417 [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>;418}419 420// TMM registers, used by AMX instructions.421let PositionOrder = 3 in {422// Tile config registers.423def TMMCFG: X86Reg<"tmmcfg", 0>;424// Tile "registers".425def TMM0: X86Reg<"tmm0", 0>;426def TMM1: X86Reg<"tmm1", 1>;427def TMM2: X86Reg<"tmm2", 2>;428def TMM3: X86Reg<"tmm3", 3>;429def TMM4: X86Reg<"tmm4", 4>;430def TMM5: X86Reg<"tmm5", 5>;431def TMM6: X86Reg<"tmm6", 6>;432def TMM7: X86Reg<"tmm7", 7>;433}434 435// Floating point stack registers. These don't map one-to-one to the FP436// pseudo registers, but we still mark them as aliasing FP registers. That437// way both kinds can be live without exceeding the stack depth. ST registers438// are only live around inline assembly.439def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>;440def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;441def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>;442def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>;443def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>;444def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>;445def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;446def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;447 448// Floating-point status word449def FPSW : X86Reg<"fpsr", 0>;450 451// Floating-point control word452def FPCW : X86Reg<"fpcr", 0>;453 454// SIMD Floating-point control register.455// Note: We only model the "Uses" of the control bits: current rounding modes,456// DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits.457def MXCSR : X86Reg<"mxcsr", 0>;458 459// Status flags register.460//461// Note that some flags that are commonly thought of as part of the status462// flags register are modeled separately. Typically this is due to instructions463// reading and updating those flags independently of all the others. We don't464// want to create false dependencies between these instructions and so we use465// a separate register to model them.466def EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>;467def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>;468def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>;469 470// The direction flag.471def DF : X86Reg<"dirflag", 0>;472 473 474// Segment registers475def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, -2, 41]>;476def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, -2, 43]>;477def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, -2, 42]>;478def ES : X86Reg<"es", 0>, DwarfRegNum<[50, -2, 40]>;479def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, -2, 44]>;480def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, -2, 45]>;481 482def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;483def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;484 485// Debug registers486def DR0 : X86Reg<"dr0", 0>;487def DR1 : X86Reg<"dr1", 1>;488def DR2 : X86Reg<"dr2", 2>;489def DR3 : X86Reg<"dr3", 3>;490def DR4 : X86Reg<"dr4", 4>;491def DR5 : X86Reg<"dr5", 5>;492def DR6 : X86Reg<"dr6", 6>;493def DR7 : X86Reg<"dr7", 7>;494def DR8 : X86Reg<"dr8", 8>;495def DR9 : X86Reg<"dr9", 9>;496def DR10 : X86Reg<"dr10", 10>;497def DR11 : X86Reg<"dr11", 11>;498def DR12 : X86Reg<"dr12", 12>;499def DR13 : X86Reg<"dr13", 13>;500def DR14 : X86Reg<"dr14", 14>;501def DR15 : X86Reg<"dr15", 15>;502 503// Control registers504def CR0 : X86Reg<"cr0", 0>;505def CR1 : X86Reg<"cr1", 1>;506def CR2 : X86Reg<"cr2", 2>;507def CR3 : X86Reg<"cr3", 3>;508def CR4 : X86Reg<"cr4", 4>;509def CR5 : X86Reg<"cr5", 5>;510def CR6 : X86Reg<"cr6", 6>;511def CR7 : X86Reg<"cr7", 7>;512def CR8 : X86Reg<"cr8", 8>;513def CR9 : X86Reg<"cr9", 9>;514def CR10 : X86Reg<"cr10", 10>;515def CR11 : X86Reg<"cr11", 11>;516def CR12 : X86Reg<"cr12", 12>;517def CR13 : X86Reg<"cr13", 13>;518def CR14 : X86Reg<"cr14", 14>;519def CR15 : X86Reg<"cr15", 15>;520 521// Pseudo index registers522def EIZ : X86Reg<"eiz", 4>;523def RIZ : X86Reg<"riz", 4>;524 525// CET registers - Shadow Stack Pointer526def SSP : X86Reg<"ssp", 0>;527 528//===----------------------------------------------------------------------===//529// Register Class Definitions... now that we have all of the pieces, define the530// top-level register classes. The order specified in the register list is531// implicitly defined to be the register allocation order.532//533 534// List call-clobbered registers before callee-save registers. RBX, RBP, (and535// R12, R13, R14, and R15 for X86-64) are callee-save registers.536// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and537// R8B, ... R15B.538// Allocate R12, R13, R20, R21, R28 and R29 last, as these require an extra byte539// when encoded in x86_64 instructions.540// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in541// 64-bit mode. The main complication is that they cannot be encoded in an542// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.543// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"544// cannot be encoded.545def GR8 : RegisterClass<"X86", [i8], 8,546 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,547 R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R22B,548 R23B, R24B, R25B, R26B, R27B, R30B, R31B, R14B,549 R15B, R12B, R13B, R20B, R21B, R28B, R29B)> {550 let AltOrders = [(sub GR8, AH, BH, CH, DH)];551 let AltOrderSelect = [{552 return MF.getSubtarget<X86Subtarget>().is64Bit();553 }];554}555 556let isAllocatable = 0 in557def GRH8 : RegisterClass<"X86", [i8], 8,558 (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH,559 R12BH, R13BH, R14BH, R15BH, R16BH, R17BH, R18BH,560 R19BH, R20BH, R21BH, R22BH, R23BH, R24BH, R25BH,561 R26BH, R27BH, R28BH, R29BH, R30BH, R31BH)>;562def GR16 : RegisterClass<"X86", [i16], 16,563 (add AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W,564 R11W, R16W, R17W, R18W, R19W, R22W, R23W, R24W,565 R25W, R26W, R27W, R30W, R31W, R14W, R15W, R12W,566 R13W, R20W, R21W, R28W, R29W)>;567 568let isAllocatable = 0 in569def GRH16 : RegisterClass<"X86", [i16], 16,570 (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, R8WH,571 R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, R15WH, R16WH,572 R17WH, R18WH, R19WH, R20WH, R21WH, R22WH, R23WH, R24WH,573 R25WH, R26WH, R27WH, R28WH, R29WH, R30WH, R31WH)>;574def GR32 : RegisterClass<"X86", [i32], 32,575 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D,576 R10D, R11D, R16D, R17D, R18D, R19D, R22D, R23D,577 R24D, R25D, R26D, R27D, R30D, R31D, R14D, R15D,578 R12D, R13D, R20D, R21D, R28D, R29D)>;579 580// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since581// RIP isn't really a register and it can't be used anywhere except in an582// address, but it doesn't cause trouble.583// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra584// tests because of the inclusion of RIP in this register class.585def GR64 : RegisterClass<"X86", [i64], 64,586 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,587 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,588 R14, R15, R12, R13, R20, R21, R28, R29, RBP, RSP, RIP)>;589 590// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when591// emitting code for intrinsics, which use implict input registers.592def GR64PLTSafe : RegisterClass<"X86", [i64], 64,593 (add RAX, RCX, RDX, RSI, RDI, R8, R9,594 RBX, R14, R15, R12, R13, RBP)>;595 596// It includes the GPR that are used as scratch register for Linux64 calling597// convention.598def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> {599 let GeneratePressureSet = 0;600}601 602// It includes the GPR that are used as scratch register for Linux32 calling603// convention.604def GR32_ArgRef: RegisterClass<"X86", [i32], 32, (add ECX, EDX)> {605 let GeneratePressureSet = 0;606}607 608// Segment registers for use by MOV instructions (and others) that have a609// segment register as one operand. Always contain a 16-bit segment610// descriptor.611def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;612 613// Debug registers.614def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>;615 616// Control registers.617def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;618 619// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of620// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"621// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers622// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,623// and GR64_ABCD are classes for registers that support 8-bit h-register624// operations.625def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;626def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;627def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;628def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;629def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;630def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>;631def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,632 R8, R9, R11, RIP, RSP)>;633def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,634 R8, R9, R10, R11,635 RIP, RSP)>;636 637// GR8_NOREX - GR8 registers which do not require a REX prefix.638def GR8_NOREX : RegisterClass<"X86", [i8], 8,639 (add AL, CL, DL, AH, CH, DH, BL, BH)> {640 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];641 let AltOrderSelect = [{642 return MF.getSubtarget<X86Subtarget>().is64Bit();643 }];644}645// GR16_NOREX - GR16 registers which do not require a REX prefix.646def GR16_NOREX : RegisterClass<"X86", [i16], 16,647 (add AX, CX, DX, SI, DI, BX, BP, SP)>;648// GR32_NOREX - GR32 registers which do not require a REX prefix.649def GR32_NOREX : RegisterClass<"X86", [i32], 32,650 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;651// GR64_NOREX - GR64 registers which do not require a REX prefix.652def GR64_NOREX : RegisterClass<"X86", [i64], 64,653 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;654// GeneratePressureSet = 0 here is a temporary workaround for lots of655// LIT fail. Whether enabling in the future still needs discussion.656let GeneratePressureSet = 0 in {657// GR8_NOREX2 - GR8 registers which do not require a REX2 prefix.658def GR8_NOREX2 : RegisterClass<"X86", [i8], 8,659 (sub GR8, (sequence "R%uB", 16, 31))> {660 let AltOrders = [(sub GR8_NOREX2, AH, BH, CH, DH)];661 let AltOrderSelect = [{662 return MF.getSubtarget<X86Subtarget>().is64Bit();663 }];664}665// GR16_NOREX2 - GR16 registers which do not require a REX2 prefix.666def GR16_NOREX2 : RegisterClass<"X86", [i16], 16,667 (sub GR16, (sequence "R%uW", 16, 31))>;668// GR32_NOREX2 - GR32 registers which do not require a REX2 prefix.669def GR32_NOREX2 : RegisterClass<"X86", [i32], 32,670 (sub GR32, (sequence "R%uD", 16, 31))>;671// GR64_NOREX2 - GR64 registers which do not require a REX2 prefix.672def GR64_NOREX2 : RegisterClass<"X86", [i64], 64,673 (sub GR64, (sequence "R%u", 16, 31))>;674}675 676// GR32_NOSP - GR32 registers except ESP.677def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;678 679// GR64_NOSP - GR64 registers except RSP (and RIP).680def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;681 682// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except683// ESP.684def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,685 (and GR32_NOREX, GR32_NOSP)>;686 687// GR64_NOREX_NOSP - GR64_NOREX registers except RSP.688def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,689 (and GR64_NOREX, GR64_NOSP)>;690let GeneratePressureSet = 0 in {691// GR32_NOREX2_NOSP - GR32_NOREX2 registers except ESP.692def GR32_NOREX2_NOSP : RegisterClass<"X86", [i32], 32,693 (sub GR32_NOREX2, ESP)>;694 695// GR64_NOREX2_NOSP - GR64_NOREX2 registers except RSP, RIP.696def GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64,697 (sub GR64_NOREX2, RSP, RIP)>;698}699 700// Register classes used for ABIs that use 32-bit address accesses,701// while using the whole x86_64 ISA.702 703// In such cases, it is fine to use RIP as we are sure the 32 high704// bits are not set. We do not need variants for NOSP as RIP is not705// allowed there.706// RIP is not spilled anywhere for now, so stick to 32-bit alignment707// to save on memory space.708// FIXME: We could allow all 64bit registers, but we would need709// something to check that the 32 high bits are not set,710// which we do not have right now.711def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;712 713// FIXME: This is unused, but deleting it results in codegen changes714def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,715 (add LOW32_ADDR_ACCESS, RBP)>;716 717// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.718def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;719def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;720 721// Classes to support the 64-bit assembler constraint tied to a fixed722// register in 32-bit mode. The second register is always the next in723// the list. Wrap around causes an error.724def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>;725def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>;726def GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>;727def GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>;728def GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>;729def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>;730 731// Class to support Windows Import Call Optimization: all indirect jumps must732// happen through RAX.733def GR64_A : RegisterClass<"X86", [i64], 64, (add RAX)>;734 735// Scalar SSE2 floating point registers.736def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;737 738def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;739 740def FR16 : RegisterClass<"X86", [f16], 16, (add FR32)> {let Size = 32;}741 742 743// FIXME: This sets up the floating point register files as though they are f64744// values, though they really are f80 values. This will cause us to spill745// values as 64-bit quantities instead of 80-bit quantities, which is much much746// faster on common hardware. In reality, this should be controlled by a747// command line option or something.748 749 750def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;751def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;752def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;753 754// st(7) may be is not allocatable.755def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> {756 let isAllocatable = 0;757}758 759// Floating point stack registers (these are not allocatable by the760// register allocator - the floating point stackifier is responsible761// for transforming FPn allocations to STn registers)762def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {763 let isAllocatable = 0;764}765 766// Helper to allow %st to print as %st(0) when its encoded in the instruction.767def RSTi : RegisterOperand<RST, "printSTiRegOperand">;768 769// Generic vector registers: VR64 and VR128.770// Ensure that float types are declared first - only float is legal on SSE1.771def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;772def VR128 : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128],773 128, (add FR32)>;774def VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],775 256, (sequence "YMM%u", 0, 15)>;776 777// Status flags registers.778def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {779 let CopyCost = -1; // Don't allow copying of status registers.780 let isAllocatable = 0;781}782def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {783 let CopyCost = -1; // Don't allow copying of status registers.784 let isAllocatable = 0;785}786def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> {787 let CopyCost = -1; // Don't allow copying of status registers.788 let isAllocatable = 0;789}790 791// AVX-512 vector/mask registers.792def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64],793 512, (sequence "ZMM%u", 0, 31)>;794 795// Represents the lower 16 registers that have VEX/legacy encodable subregs.796def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],797 512, (sequence "ZMM%u", 0, 15)>;798 799// Scalar AVX-512 floating point registers.800def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)> {801 let AltOrders = [(add (sequence "XMM%u", 16, 31), (sequence "XMM%u", 0, 15))];802 let AltOrderSelect = [{803 return Rev;804 }];805}806 807def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)> {808 let AltOrders = [(add (sequence "XMM%u", 16, 31), (sequence "XMM%u", 0, 15))];809 let AltOrderSelect = [{810 return Rev;811 }];812}813 814def FR16X : RegisterClass<"X86", [f16], 16, (add FR32X)> {let Size = 32;}815 816// Extended VR128 and VR256 for AVX-512 instructions817def VR128X : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128],818 128, (add FR32X)> {819 let AltOrders = [(add (sequence "XMM%u", 16, 31), (sequence "XMM%u", 0, 15))];820 let AltOrderSelect = [{821 return Rev;822 }];823}824def VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],825 256, (sequence "YMM%u", 0, 31)> {826 let AltOrders = [(add (sequence "YMM%u", 16, 31), (sequence "YMM%u", 0, 15))];827 let AltOrderSelect = [{828 return Rev;829 }];830}831 832// Mask registers833def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}834def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}835def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}836def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}837def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}838def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}839def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}840 841def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}842def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}843def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}844def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}845def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}846 847def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}848def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}849def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}850def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}851def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}852def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}853def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}854 855// Tiles856let CopyCost = -1 in // Don't allow copying of tile registers857def TILE : RegisterClass<"X86", [x86amx], 8192,858 (sequence "TMM%u", 0, 7)> {let Size = 8192;}859 860//===----------------------------------------------------------------------===//861// Register categories.862//863 864// The TILE and VK*PAIR registers may not be "fixed", but we don't want them865// anyway.866def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR,867 DFCCR, TILE, VK1PAIR, VK2PAIR, VK4PAIR,868 VK8PAIR, VK16PAIR]>;869def GeneralPurposeRegisters : RegisterCategory<[GR64, GR32, GR16, GR8]>;870