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1//===- X86SchedAlderlakeP.td - X86 Alderlake-P Scheduling ----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Alderlake-P core to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14def AlderlakePModel : SchedMachineModel {15  // Alderlake-P core can allocate 6 uops per cycle.16  let IssueWidth = 6; // Based on allocator width.17  let MicroOpBufferSize = 512; // Based on the reorder buffer.18  let LoadLatency = 5;19  let MispredictPenalty = 14;20 21  // Latency for microcoded instructions or instructions without latency info.22  int MaxLatency = 100;23 24  // Based on the LSD (loop-stream detector) queue size (ST).25  let LoopMicroOpBufferSize = 72;26 27  // This flag is set to allow the scheduler to assign a default model to28  // unrecognized opcodes.29  let CompleteModel = 0;30}31 32let SchedModel = AlderlakePModel in {33 34// Alderlake-P core can issue micro-ops to 12 different ports in one cycle.35def ADLPPort00 : ProcResource<1>;36def ADLPPort01 : ProcResource<1>;37def ADLPPort02 : ProcResource<1>;38def ADLPPort03 : ProcResource<1>;39def ADLPPort04 : ProcResource<1>;40def ADLPPort05 : ProcResource<1>;41def ADLPPort06 : ProcResource<1>;42def ADLPPort07 : ProcResource<1>;43def ADLPPort08 : ProcResource<1>;44def ADLPPort09 : ProcResource<1>;45def ADLPPort10 : ProcResource<1>;46def ADLPPort11 : ProcResource<1>;47 48// Workaround to represent invalid ports. WriteRes shouldn't use this resource.49def ADLPPortInvalid : ProcResource<1>;50 51// Many micro-ops are capable of issuing on multiple ports.52def ADLPPort00_01          : ProcResGroup<[ADLPPort00, ADLPPort01]>;53def ADLPPort00_01_05       : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05]>;54def ADLPPort00_01_05_06    : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05, ADLPPort06]>;55def ADLPPort00_05          : ProcResGroup<[ADLPPort00, ADLPPort05]>;56def ADLPPort00_05_06       : ProcResGroup<[ADLPPort00, ADLPPort05, ADLPPort06]>;57def ADLPPort00_06          : ProcResGroup<[ADLPPort00, ADLPPort06]>;58def ADLPPort01_05          : ProcResGroup<[ADLPPort01, ADLPPort05]>;59def ADLPPort01_05_11       : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort11]>;60def ADLPPort02_03          : ProcResGroup<[ADLPPort02, ADLPPort03]>;61def ADLPPort02_03_07       : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>;62def ADLPPort02_03_10       : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort10]>;63def ADLPPort07_08          : ProcResGroup<[ADLPPort07, ADLPPort08]>;64 65// EU has 112 reservation stations.66def ADLPPort00_01_05_06_11 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05,67                                           ADLPPort06, ADLPPort11]> {68  let BufferSize = 112;69}70 71// STD has 48 reservation stations.72def ADLPPort04_09          : ProcResGroup<[ADLPPort04, ADLPPort09]> {73  let BufferSize = 48;74}75 76// MEM has 72 reservation stations.77def ADLPPort02_03_07_08_10 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07,78                                           ADLPPort08, ADLPPort10]> {79  let BufferSize = 72;80}81 82def ADLPPortAny : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort02, ADLPPort03,83                                ADLPPort04, ADLPPort05, ADLPPort06, ADLPPort07,84                                ADLPPort08, ADLPPort09, ADLPPort10, ADLPPort11]>;85 86// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available87// until 5 cycles after the memory operand.88def : ReadAdvance<ReadAfterLd, 5>;89 90// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available91// until 6 cycles after the memory operand.92def : ReadAdvance<ReadAfterVecLd, 6>;93def : ReadAdvance<ReadAfterVecXLd, 6>;94def : ReadAdvance<ReadAfterVecYLd, 6>;95 96def : ReadAdvance<ReadInt2Fpu, 0>;97 98// Many SchedWrites are defined in pairs with and without a folded load.99// Instructions with folded loads are usually micro-fused, so they only appear100// as two micro-ops when queued in the reservation station.101// This multiclass defines the resource usage for variants with and without102// folded loads.103multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,104                            list<ProcResourceKind> ExePorts,105                            int Lat, list<int> Res = [1], int UOps = 1,106                            int LoadLat = 5, int LoadUOps = 1> {107  // Register variant is using a single cycle on ExePort.108  def : WriteRes<SchedRW, ExePorts> {109    let Latency = Lat;110    let ReleaseAtCycles = Res;111    let NumMicroOps = UOps;112  }113 114  // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to115  // the latency (default = 5).116  def : WriteRes<SchedRW.Folded, !listconcat([ADLPPort02_03_10], ExePorts)> {117    let Latency = !add(Lat, LoadLat);118    let ReleaseAtCycles = !listconcat([1], Res);119    let NumMicroOps = !add(UOps, LoadUOps);120  }121}122 123//===----------------------------------------------------------------------===//124// The following definitons are infered by smg.125//===----------------------------------------------------------------------===//126 127// Infered SchedWrite definition.128def : WriteRes<WriteADC, [ADLPPort00_06]>;129defm : X86WriteRes<WriteADCLd, [ADLPPort00_01_05_06_11, ADLPPort00_06], 11, [1, 1], 2>;130defm : ADLPWriteResPair<WriteAESDecEnc, [ADLPPort00_01], 5, [1], 1, 7>;131defm : ADLPWriteResPair<WriteAESIMC, [ADLPPort00_01], 8, [2], 2, 7>;132defm : X86WriteRes<WriteAESKeyGen, [ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 7, [4, 1, 1, 2, 3, 3], 14>;133defm : X86WriteRes<WriteAESKeyGenLd, [ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_10, ADLPPort05], 12, [4, 1, 2, 3, 1, 3], 14>;134def : WriteRes<WriteALU, [ADLPPort00_01_05_06_11]>;135def : WriteRes<WriteALULd, [ADLPPort00_01_05_06_11]> {136  let Latency = 11;137}138defm : ADLPWriteResPair<WriteBEXTR, [ADLPPort00_06, ADLPPort01], 6, [1, 1], 2>;139defm : ADLPWriteResPair<WriteBLS, [ADLPPort01_05_11], 2, [1]>;140defm : ADLPWriteResPair<WriteBSF, [ADLPPort01], 3, [1]>;141defm : ADLPWriteResPair<WriteBSR, [ADLPPort01], 3, [1]>;142def : WriteRes<WriteBSWAP32, [ADLPPort01]>;143defm : X86WriteRes<WriteBSWAP64, [ADLPPort00_06, ADLPPort01], 2, [1, 1], 2>;144defm : ADLPWriteResPair<WriteBZHI, [ADLPPort01], 3, [1]>;145def : WriteRes<WriteBitTest, [ADLPPort01]>;146defm : X86WriteRes<WriteBitTestImmLd, [ADLPPort01, ADLPPort02_03_10], 6, [1, 1], 2>;147defm : X86WriteRes<WriteBitTestRegLd, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10], 11, [4, 2, 1, 2, 1], 10>;148def : WriteRes<WriteBitTestSet, [ADLPPort01]>;149def : WriteRes<WriteBitTestSetImmLd, [ADLPPort01]> {150  let Latency = 11;151}152defm : X86WriteRes<WriteBitTestSetRegLd, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11], 17, [3, 2, 1, 2], 8>;153defm : ADLPWriteResPair<WriteBlend, [ADLPPort01_05], 1, [1], 1, 7>;154defm : ADLPWriteResPair<WriteBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;155defm : ADLPWriteResPair<WriteCLMul, [ADLPPort05], 3, [1], 1, 7>;156defm : ADLPWriteResPair<WriteCMOV, [ADLPPort00_06], 1, [1], 1, 6>;157defm : X86WriteRes<WriteCMPXCHG, [ADLPPort00_01_05_06_11, ADLPPort00_06], 3, [3, 2], 5>;158defm : X86WriteRes<WriteCMPXCHGRMW, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08], 12, [1, 2, 1, 1, 1], 6>;159defm : ADLPWriteResPair<WriteCRC32, [ADLPPort01], 3, [1]>;160defm : X86WriteRes<WriteCvtI2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;161defm : X86WriteRes<WriteCvtI2PDLd, [ADLPPort00_01, ADLPPort02_03_10], 11, [1, 1], 2>;162defm : X86WriteRes<WriteCvtI2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;163defm : X86WriteRes<WriteCvtI2PDYLd, [ADLPPort00_01, ADLPPort02_03_10], 12, [1, 1], 2>;164defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;165defm : ADLPWriteResPair<WriteCvtI2PS, [ADLPPort00_01], 4, [1], 1, 7>;166defm : ADLPWriteResPair<WriteCvtI2PSY, [ADLPPort00_01], 4, [1], 1, 8>;167defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;168defm : X86WriteRes<WriteCvtI2SD, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;169defm : X86WriteRes<WriteCvtI2SDLd, [ADLPPort00_01, ADLPPort02_03_10], 11, [1, 1], 2>;170defm : X86WriteRes<WriteCvtI2SS, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;171defm : X86WriteRes<WriteCvtI2SSLd, [ADLPPort00_01, ADLPPort02_03_10], 11, [1, 1], 2>;172defm : ADLPWriteResPair<WriteCvtPD2I, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;173defm : ADLPWriteResPair<WriteCvtPD2IY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;174defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;175defm : ADLPWriteResPair<WriteCvtPD2PS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;176defm : ADLPWriteResPair<WriteCvtPD2PSY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;177defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;178defm : X86WriteRes<WriteCvtPH2PS, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;179defm : X86WriteRes<WriteCvtPH2PSLd, [ADLPPort00_01, ADLPPort02_03_10], 12, [1, 1], 2>;180defm : X86WriteRes<WriteCvtPH2PSY, [ADLPPort00_01, ADLPPort05], 8, [1, 1], 2>;181defm : X86WriteRes<WriteCvtPH2PSYLd, [ADLPPort00_01, ADLPPort02_03_10], 12, [1, 1], 2>;182defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;183defm : ADLPWriteResPair<WriteCvtPS2I, [ADLPPort00_01], 4, [1], 1, 7>;184defm : ADLPWriteResPair<WriteCvtPS2IY, [ADLPPort00_01], 4, [1], 1, 8>;185defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;186defm : X86WriteRes<WriteCvtPS2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;187defm : X86WriteRes<WriteCvtPS2PDLd, [ADLPPort00_01, ADLPPort02_03_10], 11, [1, 1], 2>;188defm : X86WriteRes<WriteCvtPS2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;189defm : X86WriteRes<WriteCvtPS2PDYLd, [ADLPPort00_01, ADLPPort02_03_10], 12, [1, 1], 2>;190defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;191defm : X86WriteRes<WriteCvtPS2PH, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;192defm : X86WriteRes<WriteCvtPS2PHSt, [ADLPPort00_01, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1], 3>;193defm : X86WriteRes<WriteCvtPS2PHY, [ADLPPort00_01, ADLPPort05], 8, [1, 1], 2>;194defm : X86WriteRes<WriteCvtPS2PHYSt, [ADLPPort00_01, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1], 3>;195defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;196defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;197defm : ADLPWriteResPair<WriteCvtSD2I, [ADLPPort00, ADLPPort00_01], 7, [1, 1], 2>;198defm : ADLPWriteResPair<WriteCvtSD2SS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;199defm : ADLPWriteResPair<WriteCvtSS2I, [ADLPPort00, ADLPPort00_01], 7, [1, 1], 2>;200defm : X86WriteRes<WriteCvtSS2SD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;201defm : X86WriteRes<WriteCvtSS2SDLd, [ADLPPort00_01, ADLPPort02_03_10], 11, [1, 1], 2>;202defm : ADLPWriteResPair<WriteDPPD, [ADLPPort00_01, ADLPPort01_05], 9, [2, 1], 3, 7>;203defm : ADLPWriteResPair<WriteDPPS, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 7>;204defm : ADLPWriteResPair<WriteDPPSY, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 8>;205defm : ADLPWriteResPair<WriteDiv16, [ADLPPort00_01_05_06_11, ADLPPort01], 16, [1, 3], 4, 4>;206defm : ADLPWriteResPair<WriteDiv32, [ADLPPort00_01_05_06_11, ADLPPort01], 15, [1, 3], 4, 4>;207defm : ADLPWriteResPair<WriteDiv64, [ADLPPort01], 18, [3], 3>;208defm : X86WriteRes<WriteDiv8, [ADLPPort01], 17, [3], 3>;209defm : X86WriteRes<WriteDiv8Ld, [ADLPPort01], 22, [3], 3>;210defm : X86WriteRes<WriteEMMS, [ADLPPort00, ADLPPort00_05, ADLPPort00_06], 10, [1, 8, 1], 10>;211def : WriteRes<WriteFAdd, [ADLPPort05]> {212  let Latency = 3;213}214defm : X86WriteRes<WriteFAddLd, [ADLPPort01_05, ADLPPort02_03_10], 10, [1, 1], 2>;215defm : ADLPWriteResPair<WriteFAdd64, [ADLPPort01_05], 3, [1], 1, 7>;216defm : ADLPWriteResPair<WriteFAdd64X, [ADLPPort01_05], 3, [1], 1, 7>;217defm : ADLPWriteResPair<WriteFAdd64Y, [ADLPPort01_05], 3, [1], 1, 8>;218defm : X86WriteResPairUnsupported<WriteFAdd64Z>;219defm : ADLPWriteResPair<WriteFAddX, [ADLPPort01_05], 3, [1], 1, 7>;220defm : ADLPWriteResPair<WriteFAddY, [ADLPPort01_05], 3, [1], 1, 8>;221defm : X86WriteResPairUnsupported<WriteFAddZ>;222defm : ADLPWriteResPair<WriteFBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;223defm : ADLPWriteResPair<WriteFBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;224def : WriteRes<WriteFCMOV, [ADLPPort01]> {225  let Latency = 3;226}227defm : ADLPWriteResPair<WriteFCmp, [ADLPPort00_01], 4, [1], 1, 7>;228defm : ADLPWriteResPair<WriteFCmp64, [ADLPPort00_01], 4, [1], 1, 7>;229defm : ADLPWriteResPair<WriteFCmp64X, [ADLPPort00_01], 4, [1], 1, 7>;230defm : ADLPWriteResPair<WriteFCmp64Y, [ADLPPort00_01], 4, [1], 1, 8>;231defm : X86WriteResPairUnsupported<WriteFCmp64Z>;232defm : ADLPWriteResPair<WriteFCmpX, [ADLPPort00_01], 4, [1], 1, 7>;233defm : ADLPWriteResPair<WriteFCmpY, [ADLPPort00_01], 4, [1], 1, 8>;234defm : X86WriteResPairUnsupported<WriteFCmpZ>;235def : WriteRes<WriteFCom, [ADLPPort05]>;236defm : X86WriteRes<WriteFComLd, [ADLPPort02_03, ADLPPort05], 8, [1, 1], 2>;237defm : ADLPWriteResPair<WriteFComX, [ADLPPort00], 3, [1]>;238defm : ADLPWriteResPair<WriteFDiv, [ADLPPort00], 11, [1], 1, 7>;239defm : ADLPWriteResPair<WriteFDiv64, [ADLPPort00], 14, [1]>;240defm : ADLPWriteResPair<WriteFDiv64X, [ADLPPort00], 14, [1], 1, 6>;241defm : ADLPWriteResPair<WriteFDiv64Y, [ADLPPort00], 14, [1], 1, 7>;242defm : X86WriteResPairUnsupported<WriteFDiv64Z>;243defm : ADLPWriteResPair<WriteFDivX, [ADLPPort00], 11, [1], 1, 7>;244defm : ADLPWriteResPair<WriteFDivY, [ADLPPort00], 11, [1], 1, 8>;245defm : X86WriteResPairUnsupported<WriteFDivZ>;246defm : ADLPWriteResPair<WriteFHAdd, [ADLPPort01_05, ADLPPort05], 6, [1, 2], 3, 6>;247defm : ADLPWriteResPair<WriteFHAddY, [ADLPPort01_05, ADLPPort05], 5, [1, 2], 3, 8>;248def : WriteRes<WriteFLD0, [ADLPPort00_05]>;249defm : X86WriteRes<WriteFLD1, [ADLPPort00_05], 1, [2], 2>;250defm : X86WriteRes<WriteFLDC, [ADLPPort00_05], 1, [2], 2>;251def : WriteRes<WriteFLoad, [ADLPPort02_03_10]> {252  let Latency = 7;253}254def : WriteRes<WriteFLoadX, [ADLPPort02_03_10]> {255  let Latency = 7;256}257def : WriteRes<WriteFLoadY, [ADLPPort02_03_10]> {258  let Latency = 8;259}260defm : ADLPWriteResPair<WriteFLogic, [ADLPPort00_01_05], 1, [1], 1, 7>;261defm : ADLPWriteResPair<WriteFLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;262defm : X86WriteResPairUnsupported<WriteFLogicZ>;263defm : ADLPWriteResPair<WriteFMA, [ADLPPort00_01], 4, [1], 1, 7>;264defm : ADLPWriteResPair<WriteFMAX, [ADLPPort00_01], 4, [1], 1, 7>;265defm : ADLPWriteResPair<WriteFMAY, [ADLPPort00_01], 4, [1], 1, 8>;266defm : X86WriteResPairUnsupported<WriteFMAZ>;267def : WriteRes<WriteFMOVMSK, [ADLPPort00]> {268  let Latency = 3;269}270defm : X86WriteRes<WriteFMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_10], 8, [1, 1], 2>;271defm : X86WriteRes<WriteFMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_10], 9, [1, 1], 2>;272defm : X86WriteRes<WriteFMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;273defm : X86WriteRes<WriteFMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;274defm : X86WriteRes<WriteFMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;275defm : X86WriteRes<WriteFMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;276defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;277defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;278defm : X86WriteResUnsupported<WriteFMoveZ>;279defm : ADLPWriteResPair<WriteFMul, [ADLPPort00_01], 4, [1], 1, 7>;280defm : ADLPWriteResPair<WriteFMul64, [ADLPPort00_01], 4, [1], 1, 7>;281defm : ADLPWriteResPair<WriteFMul64X, [ADLPPort00_01], 4, [1], 1, 7>;282defm : ADLPWriteResPair<WriteFMul64Y, [ADLPPort00_01], 4, [1], 1, 8>;283defm : X86WriteResPairUnsupported<WriteFMul64Z>;284defm : ADLPWriteResPair<WriteFMulX, [ADLPPort00_01], 4, [1], 1, 7>;285defm : ADLPWriteResPair<WriteFMulY, [ADLPPort00_01], 4, [1], 1, 8>;286defm : X86WriteResPairUnsupported<WriteFMulZ>;287defm : ADLPWriteResPair<WriteFRcp, [ADLPPort00], 4, [1], 1, 7>;288defm : ADLPWriteResPair<WriteFRcpX, [ADLPPort00], 4, [1], 1, 7>;289defm : ADLPWriteResPair<WriteFRcpY, [ADLPPort00], 4, [1], 1, 8>;290defm : X86WriteResPairUnsupported<WriteFRcpZ>;291defm : ADLPWriteResPair<WriteFRnd, [ADLPPort00_01], 8, [2], 2, 7>;292defm : ADLPWriteResPair<WriteFRndY, [ADLPPort00_01], 8, [2], 2, 8>;293defm : X86WriteResPairUnsupported<WriteFRndZ>;294defm : ADLPWriteResPair<WriteFRsqrt, [ADLPPort00], 4, [1], 1, 7>;295defm : ADLPWriteResPair<WriteFRsqrtX, [ADLPPort00], 4, [1], 1, 7>;296defm : ADLPWriteResPair<WriteFRsqrtY, [ADLPPort00], 4, [1], 1, 8>;297defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;298defm : ADLPWriteResPair<WriteFShuffle, [ADLPPort05], 1, [1], 1, 7>;299defm : ADLPWriteResPair<WriteFShuffle256, [ADLPPort05], 3, [1], 1, 8>;300defm : ADLPWriteResPair<WriteFShuffleY, [ADLPPort05], 1, [1], 1, 8>;301defm : X86WriteResPairUnsupported<WriteFShuffleZ>;302def : WriteRes<WriteFSign, [ADLPPort00]>;303defm : ADLPWriteResPair<WriteFSqrt, [ADLPPort00], 12, [1], 1, 7>;304defm : ADLPWriteResPair<WriteFSqrt64, [ADLPPort00], 18, [1]>;305defm : ADLPWriteResPair<WriteFSqrt64X, [ADLPPort00], 18, [1], 1, 6>;306defm : ADLPWriteResPair<WriteFSqrt64Y, [ADLPPort00], 18, [1], 1, 7>;307defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;308def : WriteRes<WriteFSqrt80, [ADLPPortInvalid, ADLPPort00]> {309  let ReleaseAtCycles = [7, 1];310  let Latency = 21;311}312defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 7>;313defm : ADLPWriteResPair<WriteFSqrtY, [ADLPPort00], 12, [1], 1, 8>;314defm : X86WriteResPairUnsupported<WriteFSqrtZ>;315defm : X86WriteRes<WriteFStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;316defm : X86WriteResUnsupported<WriteFStoreNT>;317defm : X86WriteRes<WriteFStoreNTX, [ADLPPort04_09, ADLPPort07_08], 518, [1, 1], 2>;318defm : X86WriteRes<WriteFStoreNTY, [ADLPPort04_09, ADLPPort07_08], 542, [1, 1], 2>;319defm : X86WriteRes<WriteFStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;320defm : X86WriteRes<WriteFStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;321defm : ADLPWriteResPair<WriteFTest, [ADLPPort00], 3, [1]>;322defm : ADLPWriteResPair<WriteFTestY, [ADLPPort00], 5, [1], 1, 6>;323defm : ADLPWriteResPair<WriteFVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;324defm : ADLPWriteResPair<WriteFVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;325defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;326defm : ADLPWriteResPair<WriteFVarShuffle, [ADLPPort05], 1, [1], 1, 7>;327defm : ADLPWriteResPair<WriteFVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;328defm : ADLPWriteResPair<WriteFVarShuffleY, [ADLPPort05], 1, [1], 1, 8>;329defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;330def : WriteRes<WriteFence, [ADLPPort00_06]> {331  let Latency = 2;332}333defm : ADLPWriteResPair<WriteIDiv16, [ADLPPort00_01_05_06_11, ADLPPort01], 16, [1, 3], 4, 4>;334defm : ADLPWriteResPair<WriteIDiv32, [ADLPPort00_01_05_06_11, ADLPPort01], 15, [1, 3], 4, 4>;335defm : ADLPWriteResPair<WriteIDiv64, [ADLPPort01], 18, [3], 3>;336defm : X86WriteRes<WriteIDiv8, [ADLPPort01], 17, [3], 3>;337defm : X86WriteRes<WriteIDiv8Ld, [ADLPPort01], 22, [3], 3>;338defm : ADLPWriteResPair<WriteIMul16, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01], 5, [2, 1, 1], 4>;339defm : ADLPWriteResPair<WriteIMul16Imm, [ADLPPort00_01_05_06_11, ADLPPort01], 4, [1, 1], 2>;340defm : ADLPWriteResPair<WriteIMul16Reg, [ADLPPort01], 3, [1]>;341defm : ADLPWriteResPair<WriteIMul32, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 3>;342defm : ADLPWriteResPair<WriteIMul32Imm, [ADLPPort01], 3, [1]>;343defm : ADLPWriteResPair<WriteIMul32Reg, [ADLPPort01], 3, [1]>;344defm : ADLPWriteResPair<WriteIMul64, [ADLPPort01, ADLPPort05], 4, [1, 1], 2>;345defm : ADLPWriteResPair<WriteIMul64Imm, [ADLPPort01], 3, [1]>;346defm : ADLPWriteResPair<WriteIMul64Reg, [ADLPPort01], 3, [1]>;347defm : ADLPWriteResPair<WriteIMul8, [ADLPPort01], 3, [1]>;348def : WriteRes<WriteIMulH, []> {349  let Latency = 3;350}351def : WriteRes<WriteIMulHLd, []> {352  let Latency = 3;353}354def : WriteRes<WriteJump, [ADLPPort00_06]>;355defm : X86WriteRes<WriteJumpLd, [ADLPPort00_06, ADLPPort02_03], 6, [1, 1], 2>;356def : WriteRes<WriteLAHFSAHF, [ADLPPort00_06]> {357  let Latency = 3;358}359defm : X86WriteRes<WriteLDMXCSR, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_10], 7, [1, 1, 1, 1], 4>;360def : WriteRes<WriteLEA, [ADLPPort01]>;361defm : ADLPWriteResPair<WriteLZCNT, [ADLPPort01], 3, [1]>;362def : WriteRes<WriteLoad, [ADLPPort02_03_10]> {363  let Latency = 5;364}365def : WriteRes<WriteMMXMOVMSK, [ADLPPort00]> {366  let Latency = 3;367}368defm : ADLPWriteResPair<WriteMPSAD, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 7>;369defm : ADLPWriteResPair<WriteMPSADY, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 8>;370defm : ADLPWriteResPair<WriteMULX32, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 2>;371defm : ADLPWriteResPair<WriteMULX64, [ADLPPort01, ADLPPort05], 4, [1, 1]>;372def : WriteRes<WriteMicrocoded, [ADLPPort00_01_05_06]> {373  let Latency = AlderlakePModel.MaxLatency;374}375def : WriteRes<WriteMove, [ADLPPort00_01_05_06_11]>;376defm : X86WriteRes<WriteNop, [], 1, [], 0>;377defm : X86WriteRes<WritePCmpEStrI, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort05], 16, [3, 2, 1, 1, 1], 8>;378defm : X86WriteRes<WritePCmpEStrILd, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05], 31, [3, 1, 1, 1, 1, 1], 8>;379defm : X86WriteRes<WritePCmpEStrM, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort05], 16, [3, 3, 1, 1, 1], 9>;380defm : X86WriteRes<WritePCmpEStrMLd, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05], 17, [3, 2, 1, 1, 1, 1], 9>;381defm : ADLPWriteResPair<WritePCmpIStrI, [ADLPPort00], 11, [3], 3, 20>;382defm : ADLPWriteResPair<WritePCmpIStrM, [ADLPPort00], 11, [3], 3>;383defm : ADLPWriteResPair<WritePHAdd, [ADLPPort00_05, ADLPPort05], 3, [1, 2], 3, 8>;384defm : ADLPWriteResPair<WritePHAddX, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 7>;385defm : ADLPWriteResPair<WritePHAddY, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 8>;386defm : ADLPWriteResPair<WritePHMINPOS, [ADLPPort00], 4, [1], 1, 7>;387defm : ADLPWriteResPair<WritePMULLD, [ADLPPort00_01], 10, [2], 2, 8>;388defm : ADLPWriteResPair<WritePMULLDY, [ADLPPort00_01], 10, [2], 2, 8>;389defm : X86WriteResPairUnsupported<WritePMULLDZ>;390defm : ADLPWriteResPair<WritePOPCNT, [ADLPPort01], 3, [1]>;391defm : ADLPWriteResPair<WritePSADBW, [ADLPPort05], 3, [1], 1, 8>;392defm : ADLPWriteResPair<WritePSADBWX, [ADLPPort05], 3, [1], 1, 7>;393defm : ADLPWriteResPair<WritePSADBWY, [ADLPPort05], 3, [1], 1, 8>;394defm : X86WriteResPairUnsupported<WritePSADBWZ>;395defm : X86WriteRes<WriteRMW, [ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08], 1, [1, 1, 1], 3>;396defm : X86WriteRes<WriteRotate, [ADLPPort00_01_05_06_11, ADLPPort00_06], 2, [1, 2], 3>;397defm : X86WriteRes<WriteRotateLd, [ADLPPort00_01_05_06_11, ADLPPort00_06], 12, [1, 2], 3>;398defm : X86WriteRes<WriteRotateCL, [ADLPPort00_06], 2, [2], 2>;399defm : X86WriteRes<WriteRotateCLLd, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01], 19, [2, 3, 2], 7>;400defm : X86WriteRes<WriteSETCC, [ADLPPort00_06], 2, [2], 2>;401defm : X86WriteRes<WriteSETCCStore, [ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 13, [2, 1, 1], 4>;402defm : X86WriteRes<WriteSHDmrcl, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>;403defm : X86WriteRes<WriteSHDmri, [ADLPPort00_01_05_06_11, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1], 5>;404defm : X86WriteRes<WriteSHDrrcl, [ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01], 5, [1, 1, 1], 3>;405def : WriteRes<WriteSHDrri, [ADLPPort01]> {406  let Latency = 3;407}408defm : X86WriteRes<WriteSTMXCSR, [ADLPPort00, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1], 4>;409def : WriteRes<WriteShift, [ADLPPort00_06]>;410def : WriteRes<WriteShiftLd, [ADLPPort00_06]> {411  let Latency = 12;412}413defm : X86WriteRes<WriteShiftCL, [ADLPPort00_06], 2, [2], 2>;414defm : X86WriteRes<WriteShiftCLLd, [ADLPPort00_06], 12, [2], 2>;415defm : ADLPWriteResPair<WriteShuffle, [ADLPPort05], 1, [1], 1, 8>;416defm : ADLPWriteResPair<WriteShuffle256, [ADLPPort05], 3, [1], 1, 8>;417defm : ADLPWriteResPair<WriteShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;418defm : ADLPWriteResPair<WriteShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;419defm : X86WriteResPairUnsupported<WriteShuffleZ>;420defm : X86WriteRes<WriteStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;421defm : X86WriteRes<WriteStoreNT, [ADLPPort04_09, ADLPPort07_08], 512, [1, 1], 2>;422def : WriteRes<WriteSystem, [ADLPPort00_01_05_06]> {423  let Latency = AlderlakePModel.MaxLatency;424}425defm : ADLPWriteResPair<WriteTZCNT, [ADLPPort01], 3, [1]>;426defm : ADLPWriteResPair<WriteVPMOV256, [ADLPPort05], 3, [1], 1, 8>;427defm : ADLPWriteResPair<WriteVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;428defm : ADLPWriteResPair<WriteVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;429defm : X86WriteResPairUnsupported<WriteVarBlendZ>;430defm : ADLPWriteResPair<WriteVarShuffle, [ADLPPort00, ADLPPort05], 3, [1, 1], 2, 8>;431defm : ADLPWriteResPair<WriteVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;432defm : ADLPWriteResPair<WriteVarShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;433defm : ADLPWriteResPair<WriteVarShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;434defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;435defm : ADLPWriteResPair<WriteVarVecShift, [ADLPPort00_01], 1, [1], 1, 7>;436defm : ADLPWriteResPair<WriteVarVecShiftY, [ADLPPort00_01], 1, [1], 1, 8>;437defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;438defm : ADLPWriteResPair<WriteVecALU, [ADLPPort00], 1, [1], 1, 8>;439defm : ADLPWriteResPair<WriteVecALUX, [ADLPPort00_01], 1, [1], 1, 7>;440defm : ADLPWriteResPair<WriteVecALUY, [ADLPPort00_01], 1, [1], 1, 8>;441defm : X86WriteResPairUnsupported<WriteVecALUZ>;442defm : X86WriteRes<WriteVecExtract, [ADLPPort00, ADLPPort01_05], 4, [1, 1], 2>;443defm : X86WriteRes<WriteVecExtractSt, [ADLPPort01_05, ADLPPort04_09, ADLPPort07_08], 19, [1, 1, 1], 3>;444defm : ADLPWriteResPair<WriteVecIMul, [ADLPPort00], 5, [1], 1, 8>;445defm : ADLPWriteResPair<WriteVecIMulX, [ADLPPort00_01], 5, [1], 1, 8>;446defm : ADLPWriteResPair<WriteVecIMulY, [ADLPPort00_01], 5, [1], 1, 8>;447defm : X86WriteResPairUnsupported<WriteVecIMulZ>;448defm : X86WriteRes<WriteVecInsert, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2>;449defm : X86WriteRes<WriteVecInsertLd, [ADLPPort01_05, ADLPPort02_03_10], 8, [1, 1], 2>;450def : WriteRes<WriteVecLoad, [ADLPPort02_03_10]> {451  let Latency = 7;452}453def : WriteRes<WriteVecLoadNT, [ADLPPort02_03_10]> {454  let Latency = 7;455}456def : WriteRes<WriteVecLoadNTY, [ADLPPort02_03_10]> {457  let Latency = 8;458}459def : WriteRes<WriteVecLoadX, [ADLPPort02_03_10]> {460  let Latency = 7;461}462def : WriteRes<WriteVecLoadY, [ADLPPort02_03_10]> {463  let Latency = 8;464}465defm : ADLPWriteResPair<WriteVecLogic, [ADLPPort00_05], 1, [1], 1, 8>;466defm : ADLPWriteResPair<WriteVecLogicX, [ADLPPort00_01_05], 1, [1], 1, 7>;467defm : ADLPWriteResPair<WriteVecLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;468defm : X86WriteResPairUnsupported<WriteVecLogicZ>;469def : WriteRes<WriteVecMOVMSK, [ADLPPort00]> {470  let Latency = 3;471}472def : WriteRes<WriteVecMOVMSKY, [ADLPPort00]> {473  let Latency = 4;474}475defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;476defm : X86WriteRes<WriteVecMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_10], 8, [1, 1], 2>;477defm : X86WriteRes<WriteVecMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_10], 9, [1, 1], 2>;478defm : X86WriteRes<WriteVecMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;479defm : X86WriteRes<WriteVecMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;480defm : X86WriteRes<WriteVecMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;481defm : X86WriteRes<WriteVecMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;482def : WriteRes<WriteVecMove, [ADLPPort00_05]>;483def : WriteRes<WriteVecMoveFromGpr, [ADLPPort05]> {484  let Latency = 3;485}486def : WriteRes<WriteVecMoveToGpr, [ADLPPort00]> {487  let Latency = 3;488}489defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>;490defm : X86WriteRes<WriteVecMoveY, [], 1, [], 0>;491defm : X86WriteResUnsupported<WriteVecMoveZ>;492defm : ADLPWriteResPair<WriteVecShift, [ADLPPort00], 1, [1], 1, 8>;493def : WriteRes<WriteVecShiftImm, [ADLPPort00]>;494def : WriteRes<WriteVecShiftImmX, [ADLPPort00_01]>;495defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;496def : WriteRes<WriteVecShiftImmY, [ADLPPort00_01]>;497defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;498defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;499defm : X86WriteRes<WriteVecShiftX, [ADLPPort00_01, ADLPPort01_05], 2, [1, 1], 2>;500defm : X86WriteRes<WriteVecShiftXLd, [ADLPPort00_01, ADLPPort02_03_10], 8, [1, 1], 2>;501defm : X86WriteRes<WriteVecShiftY, [ADLPPort00_01, ADLPPort05], 4, [1, 1], 2>;502defm : X86WriteRes<WriteVecShiftYLd, [ADLPPort00_01, ADLPPort02_03_10], 9, [1, 1], 2>;503defm : X86WriteResPairUnsupported<WriteVecShiftZ>;504defm : X86WriteRes<WriteVecStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;505defm : X86WriteRes<WriteVecStoreNT, [ADLPPort04_09, ADLPPort07_08], 511, [1, 1], 2>;506defm : X86WriteRes<WriteVecStoreNTY, [ADLPPort04_09, ADLPPort07_08], 507, [1, 1], 2>;507defm : X86WriteRes<WriteVecStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;508defm : X86WriteRes<WriteVecStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;509defm : ADLPWriteResPair<WriteVecTest, [ADLPPort00, ADLPPort05], 4, [1, 1], 2>;510defm : ADLPWriteResPair<WriteVecTestY, [ADLPPort00, ADLPPort05], 6, [1, 1], 2, 6>;511defm : X86WriteRes<WriteXCHG, [ADLPPort00_01_05_06_11], 2, [3], 3>;512def : WriteRes<WriteZero, []>;513 514// Infered SchedWriteRes and InstRW definition.515 516def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04]> {517  let Latency = 7;518  let NumMicroOps = 3;519}520def : InstRW<[ADLPWriteResGroup0], (instregex "^AA(D|N)D64mr$",521                                              "^A(X?)OR64mr$")>;522 523def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {524  let ReleaseAtCycles = [2, 1, 1, 1, 1];525  let Latency = 12;526  let NumMicroOps = 6;527}528def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;529 530def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10]> {531  let Latency = 6;532  let NumMicroOps = 2;533}534def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",535                                              "^RET(16|32)$",536                                              "^RORX(32|64)mi$")>;537def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",538                                                                                                                                         "^AD(C|O)X(32|64)rm$")>;539 540def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {541  let Latency = 13;542  let NumMicroOps = 5;543}544def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;545 546def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {547  let ReleaseAtCycles = [2, 1, 1, 1, 1];548  let Latency = 13;549  let NumMicroOps = 6;550}551def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;552 553def ADLPWriteResGroup5 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {554  let Latency = 6;555  let NumMicroOps = 2;556}557def : InstRW<[ADLPWriteResGroup5], (instregex "^CMP(8|16|32)mi$",558                                              "^CMP(8|16|32|64)mi8$",559                                              "^MOV(8|16)rm$",560                                              "^POP(16|32)r((mr)?)$")>;561def : InstRW<[ADLPWriteResGroup5], (instrs CMP64mi32,562                                           MOV8rm_NOREX,563                                           MOVZX16rm8)>;564def : InstRW<[ADLPWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",565                                                           "^AND(8|16|32)rm$",566                                                           "^(X?)OR(8|16|32)rm$")>;567def : InstRW<[ADLPWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;568 569def ADLPWriteResGroup6 : SchedWriteRes<[]> {570  let NumMicroOps = 0;571}572def : InstRW<[ADLPWriteResGroup6], (instregex "^(ADD|SUB)64ri8$",573                                              "^(DE|IN)C64r$",574                                              "^MOV64rr((_REV)?)$")>;575def : InstRW<[ADLPWriteResGroup6], (instrs CLC,576                                           JMP_2)>;577 578def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {579  let Latency = 13;580  let NumMicroOps = 4;581}582def : InstRW<[ADLPWriteResGroup7], (instregex "^A(D|N)D8mi(8?)$",583                                              "^(DE|IN)C8m$",584                                              "^N(EG|OT)8m$",585                                              "^(X?)OR8mi(8?)$",586                                              "^SUB8mi(8?)$")>;587def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",588                                                                                                                            "^(X?)OR8mr$")>;589def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;590 591def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {592  let Latency = 3;593}594def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)SSrr((_Int)?)$")>;595 596def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {597  let Latency = 10;598  let NumMicroOps = 2;599}600def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_F(32|64)m$",601                                              "^ILD_F(16|32|64)m$",602                                              "^SUB(R?)_F(32|64)m$")>;603 604def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {605  let ReleaseAtCycles = [1, 2];606  let Latency = 13;607  let NumMicroOps = 3;608}609def : InstRW<[ADLPWriteResGroup10], (instregex "^ADD_FI(16|32)m$",610                                               "^SUB(R?)_FI(16|32)m$")>;611 612def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_11]> {613  let Latency = 2;614}615def : InstRW<[ADLPWriteResGroup11], (instregex "^AND(8|16|32|64)r(r|i8)$",616                                               "^AND(8|16|32|64)rr_REV$",617                                               "^(AND|TEST)(32|64)i32$",618                                               "^(AND|TEST)(8|32)ri$",619                                               "^(AND|TEST)64ri32$",620                                               "^(AND|TEST)8i8$",621                                               "^(X?)OR(8|16|32|64)r(r|i8)$",622                                               "^(X?)OR(8|16|32|64)rr_REV$",623                                               "^(X?)OR(32|64)i32$",624                                               "^(X?)OR(8|32)ri$",625                                               "^(X?)OR64ri32$",626                                               "^(X?)OR8i8$",627                                               "^TEST(8|16|32|64)rr$")>;628def : InstRW<[ADLPWriteResGroup11], (instrs XOR8rr_NOREX)>;629 630def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {631  let Latency = 7;632  let NumMicroOps = 2;633}634def : InstRW<[ADLPWriteResGroup12], (instregex "^TEST(8|16|32)mi$")>;635def : InstRW<[ADLPWriteResGroup12], (instrs TEST64mi32)>;636def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instregex "^(X?)OR64rm$")>;637def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instrs AND64rm)>;638def : InstRW<[ADLPWriteResGroup12, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;639 640def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01_05_11, ADLPPort02_03_10]> {641  let Latency = 7;642  let NumMicroOps = 2;643}644def : InstRW<[ADLPWriteResGroup13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;645 646def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort01_05_11]> {647  let Latency = 2;648}649def : InstRW<[ADLPWriteResGroup14], (instregex "^ANDN(32|64)rr$")>;650 651def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10]> {652  let ReleaseAtCycles = [5, 2, 1, 1];653  let Latency = 10;654  let NumMicroOps = 9;655}656def : InstRW<[ADLPWriteResGroup15], (instrs BT64mr)>;657 658def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort01]> {659  let Latency = 3;660}661def : InstRW<[ADLPWriteResGroup16], (instregex "^BT((C|R|S)?)64rr$",662                                               "^P(DEP|EXT)(32|64)rr$")>;663 664def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {665  let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];666  let Latency = 17;667  let NumMicroOps = 10;668}669def : InstRW<[ADLPWriteResGroup17], (instregex "^BT(C|R|S)64mr$")>;670 671def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {672  let Latency = 7;673  let NumMicroOps = 5;674}675def : InstRW<[ADLPWriteResGroup18], (instregex "^CALL(16|32|64)m((_NT)?)$")>;676 677def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {678  let Latency = 3;679  let NumMicroOps = 3;680}681def : InstRW<[ADLPWriteResGroup19], (instregex "^CALL(16|32|64)r((_NT)?)$")>;682 683def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {684  let Latency = 3;685  let NumMicroOps = 2;686}687def : InstRW<[ADLPWriteResGroup20], (instrs CALL64pcrel32,688                                            MFENCE)>;689 690def ADLPWriteResGroup21 : SchedWriteRes<[ADLPPort01_05]>;691def : InstRW<[ADLPWriteResGroup21], (instregex "^C(DQ|WD)E$",692                                               "^(V?)MOVS(H|L)DUPrr$",693                                               "^(V?)SHUFP(D|S)rri$",694                                               "^VMOVS(H|L)DUPYrr$",695                                               "^VSHUFP(D|S)Yrri$")>;696def : InstRW<[ADLPWriteResGroup21], (instrs CBW,697                                            VPBLENDWYrri)>;698 699def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_06]>;700def : InstRW<[ADLPWriteResGroup22], (instregex "^C(DQ|QO)$",701                                               "^(CL|ST)AC$")>;702 703def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {704  let Latency = 3;705  let NumMicroOps = 2;706}707def : InstRW<[ADLPWriteResGroup23], (instrs CLD)>;708 709def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {710  let Latency = 3;711  let NumMicroOps = 3;712}713def : InstRW<[ADLPWriteResGroup24], (instrs CLDEMOTE)>;714 715def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {716  let Latency = 2;717  let NumMicroOps = 4;718}719def : InstRW<[ADLPWriteResGroup25], (instrs CLFLUSH)>;720 721def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {722  let Latency = 2;723  let NumMicroOps = 3;724}725def : InstRW<[ADLPWriteResGroup26], (instrs CLFLUSHOPT)>;726 727def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {728  let ReleaseAtCycles = [2, 1];729  let Latency = AlderlakePModel.MaxLatency;730  let NumMicroOps = 3;731}732def : InstRW<[ADLPWriteResGroup27], (instrs CLI)>;733 734def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {735  let ReleaseAtCycles = [6, 1, 3];736  let Latency = AlderlakePModel.MaxLatency;737  let NumMicroOps = 10;738}739def : InstRW<[ADLPWriteResGroup28], (instrs CLTS)>;740 741def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {742  let Latency = 5;743  let NumMicroOps = 3;744}745def : InstRW<[ADLPWriteResGroup29], (instregex "^MOV16o(16|32|64)a$")>;746def : InstRW<[ADLPWriteResGroup29], (instrs CLWB)>;747 748def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {749  let ReleaseAtCycles = [5, 2];750  let Latency = 6;751  let NumMicroOps = 7;752}753def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPS(B|L|Q|W)$")>;754 755def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {756  let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];757  let Latency = 32;758  let NumMicroOps = 22;759}760def : InstRW<[ADLPWriteResGroup31], (instrs CMPXCHG16B)>;761 762def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {763  let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];764  let Latency = 25;765  let NumMicroOps = 16;766}767def : InstRW<[ADLPWriteResGroup32], (instrs CMPXCHG8B)>;768 769def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {770  let ReleaseAtCycles = [1, 2, 1, 1, 1];771  let Latency = 13;772  let NumMicroOps = 6;773}774def : InstRW<[ADLPWriteResGroup33], (instrs CMPXCHG8rm)>;775 776def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {777  let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];778  let Latency = 18;779  let NumMicroOps = 26;780}781def : InstRW<[ADLPWriteResGroup34], (instrs CPUID)>;782 783def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_10]> {784  let Latency = 26;785  let NumMicroOps = 3;786}787def : InstRW<[ADLPWriteResGroup35], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>;788 789def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_10, ADLPPort05]> {790  let Latency = 12;791  let NumMicroOps = 3;792}793def : InstRW<[ADLPWriteResGroup36], (instrs CVTSI642SSrm)>;794def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;795def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;796 797def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {798  let ReleaseAtCycles = [1, 2];799  let Latency = 8;800  let NumMicroOps = 3;801}802def : InstRW<[ADLPWriteResGroup37, ReadInt2Fpu], (instrs CVTSI642SSrr)>;803def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;804def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;805 806def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {807  let Latency = 8;808  let NumMicroOps = 3;809}810def : InstRW<[ADLPWriteResGroup38], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;811def : InstRW<[ADLPWriteResGroup38, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;812 813def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {814  let Latency = 2;815  let NumMicroOps = 2;816}817def : InstRW<[ADLPWriteResGroup39], (instregex "^J(E|R)CXZ$")>;818def : InstRW<[ADLPWriteResGroup39], (instrs CWD)>;819 820def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_01_05_06]>;821def : InstRW<[ADLPWriteResGroup40], (instregex "^(LD|ST)_Frr$",822                                               "^MOV16s(m|r)$",823                                               "^MOV(32|64)sr$")>;824def : InstRW<[ADLPWriteResGroup40], (instrs DEC16r_alt,825                                            SALC,826                                            ST_FPrr,827                                            SYSCALL)>;828 829def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {830  let Latency = 7;831}832def : InstRW<[ADLPWriteResGroup41], (instrs DEC32r_alt)>;833 834def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {835  let Latency = 27;836  let NumMicroOps = 2;837}838def : InstRW<[ADLPWriteResGroup42], (instregex "^DIVR_F(32|64)m$")>;839 840def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {841  let Latency = 30;842  let NumMicroOps = 3;843}844def : InstRW<[ADLPWriteResGroup43], (instregex "^DIVR_FI(16|32)m$")>;845 846def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00]> {847  let Latency = 15;848}849def : InstRW<[ADLPWriteResGroup44], (instregex "^DIVR_F(P?)rST0$")>;850def : InstRW<[ADLPWriteResGroup44], (instrs DIVR_FST0r)>;851 852def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_10]> {853  let Latency = 20;854  let NumMicroOps = 2;855}856def : InstRW<[ADLPWriteResGroup45, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;857 858def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {859  let Latency = 22;860  let NumMicroOps = 2;861}862def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_F(32|64)m$")>;863 864def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {865  let Latency = 25;866  let NumMicroOps = 3;867}868def : InstRW<[ADLPWriteResGroup47], (instregex "^DIV_FI(16|32)m$")>;869 870def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00]> {871  let Latency = 20;872}873def : InstRW<[ADLPWriteResGroup48], (instregex "^DIV_F(P?)rST0$")>;874def : InstRW<[ADLPWriteResGroup48], (instrs DIV_FST0r)>;875 876def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {877  let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];878  let Latency = 126;879  let NumMicroOps = 57;880}881def : InstRW<[ADLPWriteResGroup49], (instrs ENTER)>;882 883def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {884  let Latency = 12;885  let NumMicroOps = 3;886}887def : InstRW<[ADLPWriteResGroup50], (instregex "^(V?)EXTRACTPSmri$")>;888def : InstRW<[ADLPWriteResGroup50], (instrs SMSW16m)>;889 890def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {891  let Latency = 4;892  let NumMicroOps = 2;893}894def : InstRW<[ADLPWriteResGroup51], (instregex "^(V?)EXTRACTPSrri$")>;895def : InstRW<[ADLPWriteResGroup51], (instrs MMX_PEXTRWrri)>;896 897def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {898  let Latency = 7;899  let NumMicroOps = 5;900}901def : InstRW<[ADLPWriteResGroup52], (instrs FARCALL64m)>;902 903def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {904  let Latency = 6;905  let NumMicroOps = 2;906}907def : InstRW<[ADLPWriteResGroup53], (instrs FARJMP64m,908                                            JMP64m_REX)>;909 910def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {911  let NumMicroOps = 2;912}913def : InstRW<[ADLPWriteResGroup54], (instregex "^(V?)MASKMOVDQU((64)?)$",914                                               "^ST_FP(32|64|80)m$")>;915def : InstRW<[ADLPWriteResGroup54], (instrs FBSTPm,916                                            VMPTRSTm)>;917 918def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]> {919  let ReleaseAtCycles = [2];920  let Latency = 2;921  let NumMicroOps = 2;922}923def : InstRW<[ADLPWriteResGroup55], (instrs FDECSTP)>;924 925def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {926  let ReleaseAtCycles = [1, 2];927  let Latency = 11;928  let NumMicroOps = 3;929}930def : InstRW<[ADLPWriteResGroup56], (instregex "^FICOM(P?)(16|32)m$")>;931 932def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00_05]>;933def : InstRW<[ADLPWriteResGroup57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;934def : InstRW<[ADLPWriteResGroup57], (instrs FINCSTP,935                                            FNOP)>;936 937def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {938  let Latency = 7;939  let NumMicroOps = 3;940}941def : InstRW<[ADLPWriteResGroup58], (instrs FLDCW16m)>;942 943def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {944  let ReleaseAtCycles = [2, 39, 5, 10, 8];945  let Latency = 62;946  let NumMicroOps = 64;947}948def : InstRW<[ADLPWriteResGroup59], (instrs FLDENVm)>;949 950def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06]> {951  let ReleaseAtCycles = [4];952  let Latency = 4;953  let NumMicroOps = 4;954}955def : InstRW<[ADLPWriteResGroup60], (instrs FNCLEX)>;956 957def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {958  let ReleaseAtCycles = [6, 3, 6];959  let Latency = 75;960  let NumMicroOps = 15;961}962def : InstRW<[ADLPWriteResGroup61], (instrs FNINIT)>;963 964def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {965  let Latency = 2;966  let NumMicroOps = 3;967}968def : InstRW<[ADLPWriteResGroup62], (instrs FNSTCW16m)>;969 970def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {971  let Latency = 3;972  let NumMicroOps = 2;973}974def : InstRW<[ADLPWriteResGroup63], (instrs FNSTSW16r)>;975 976def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {977  let Latency = 3;978  let NumMicroOps = 3;979}980def : InstRW<[ADLPWriteResGroup64], (instrs FNSTSWm)>;981 982def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {983  let ReleaseAtCycles = [9, 30, 21, 1, 11, 11, 16, 1];984  let Latency = 106;985  let NumMicroOps = 100;986}987def : InstRW<[ADLPWriteResGroup65], (instrs FSTENVm)>;988 989def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {990  let ReleaseAtCycles = [4, 47, 1, 2, 1, 33, 2];991  let Latency = 63;992  let NumMicroOps = 90;993}994def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR)>;995 996def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {997  let ReleaseAtCycles = [4, 45, 1, 2, 1, 31, 4];998  let Latency = 63;999  let NumMicroOps = 88;1000}1001def : InstRW<[ADLPWriteResGroup67], (instrs FXRSTOR64)>;1002 1003def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1004  let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];1005  let Latency = AlderlakePModel.MaxLatency;1006  let NumMicroOps = 110;1007}1008def : InstRW<[ADLPWriteResGroup68], (instregex "^FXSAVE((64)?)$")>;1009 1010def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_10]> {1011  let Latency = 12;1012  let NumMicroOps = 2;1013}1014def : InstRW<[ADLPWriteResGroup69, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",1015                                                                "^(V?)GF2P8MULBrm$")>;1016def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$")>;1017def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instrs VGF2P8MULBYrm)>;1018 1019def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00_01]> {1020  let Latency = 5;1021}1022def : InstRW<[ADLPWriteResGroup70], (instregex "^(V?)GF2P8MULBrr$")>;1023def : InstRW<[ADLPWriteResGroup70], (instrs VGF2P8MULBYrr)>;1024 1025def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1026  let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];1027  let Latency = 35;1028  let NumMicroOps = 87;1029}1030def : InstRW<[ADLPWriteResGroup71], (instrs IN16ri)>;1031 1032def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1033  let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];1034  let Latency = 35;1035  let NumMicroOps = 87;1036}1037def : InstRW<[ADLPWriteResGroup72], (instrs IN16rr)>;1038 1039def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1040  let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];1041  let Latency = 35;1042  let NumMicroOps = 94;1043}1044def : InstRW<[ADLPWriteResGroup73], (instrs IN32ri)>;1045 1046def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1047  let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];1048  let NumMicroOps = 99;1049}1050def : InstRW<[ADLPWriteResGroup74], (instrs IN32rr)>;1051 1052def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1053  let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];1054  let Latency = 35;1055  let NumMicroOps = 87;1056}1057def : InstRW<[ADLPWriteResGroup75], (instrs IN8ri)>;1058 1059def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort05]> {1060  let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];1061  let Latency = 35;1062  let NumMicroOps = 86;1063}1064def : InstRW<[ADLPWriteResGroup76], (instrs IN8rr)>;1065 1066def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort00_06]> {1067  let NumMicroOps = 4;1068}1069def : InstRW<[ADLPWriteResGroup77], (instrs INC16r_alt)>;1070 1071def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort02_03_10]> {1072  let Latency = 7;1073}1074def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",1075                                               "^VPBROADCAST(D|Q)rm$")>;1076def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,1077                                            VBROADCASTSSrm)>;1078 1079def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1080  let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];1081  let Latency = 20;1082  let NumMicroOps = 83;1083}1084def : InstRW<[ADLPWriteResGroup79], (instrs INSB)>;1085 1086def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1087  let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];1088  let Latency = 20;1089  let NumMicroOps = 92;1090}1091def : InstRW<[ADLPWriteResGroup80], (instrs INSL)>;1092 1093def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1094  let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];1095  let Latency = 20;1096  let NumMicroOps = 86;1097}1098def : InstRW<[ADLPWriteResGroup81], (instrs INSW)>;1099 1100def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1101  let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];1102  let Latency = AlderlakePModel.MaxLatency;1103  let NumMicroOps = 42;1104}1105def : InstRW<[ADLPWriteResGroup82], (instrs INVLPG)>;1106 1107def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {1108  let Latency = 4;1109  let NumMicroOps = 3;1110}1111def : InstRW<[ADLPWriteResGroup83], (instregex "^IST(T?)_FP(16|32|64)m$",1112                                               "^IST_F(16|32)m$")>;1113 1114def ADLPWriteResGroup84 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {1115  let Latency = 2;1116  let NumMicroOps = 2;1117}1118def : InstRW<[ADLPWriteResGroup84], (instrs JCXZ)>;1119 1120def ADLPWriteResGroup85 : SchedWriteRes<[ADLPPort06]>;1121def : InstRW<[ADLPWriteResGroup85], (instrs JMP64r_REX)>;1122 1123def ADLPWriteResGroup86 : SchedWriteRes<[]> {1124  let Latency = 0;1125  let NumMicroOps = 0;1126}1127def : InstRW<[ADLPWriteResGroup86], (instregex "^JMP_(1|4)$")>;1128def : InstRW<[ADLPWriteResGroup86], (instrs VZEROUPPER)>;1129 1130def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1131  let ReleaseAtCycles = [8, 2, 14, 3, 1];1132  let Latency = 198;1133  let NumMicroOps = 81;1134}1135def : InstRW<[ADLPWriteResGroup87], (instrs LAR16rm)>;1136 1137def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort05]> {1138  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];1139  let Latency = 66;1140  let NumMicroOps = 22;1141}1142def : InstRW<[ADLPWriteResGroup88], (instrs LAR16rr)>;1143 1144def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1145  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];1146  let Latency = 71;1147  let NumMicroOps = 85;1148}1149def : InstRW<[ADLPWriteResGroup89], (instrs LAR32rm)>;1150 1151def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort05]> {1152  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];1153  let Latency = 65;1154  let NumMicroOps = 22;1155}1156def : InstRW<[ADLPWriteResGroup90], (instregex "^LAR(32|64)rr$")>;1157 1158def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1159  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];1160  let Latency = 71;1161  let NumMicroOps = 87;1162}1163def : InstRW<[ADLPWriteResGroup91], (instrs LAR64rm)>;1164 1165def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort02_03]> {1166  let Latency = 7;1167}1168def : InstRW<[ADLPWriteResGroup92], (instregex "^LD_F(32|64|80)m$")>;1169 1170def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01]> {1171  let Latency = 2;1172  let NumMicroOps = 2;1173}1174def : InstRW<[ADLPWriteResGroup93], (instrs LEA16r)>;1175 1176def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {1177  let ReleaseAtCycles = [3, 1];1178  let Latency = 6;1179  let NumMicroOps = 4;1180}1181def : InstRW<[ADLPWriteResGroup94], (instregex "^LODS(B|W)$",1182                                               "^SCAS(B|L|Q|W)$")>;1183def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE)>;1184 1185def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {1186  let ReleaseAtCycles = [2, 1];1187  let Latency = 6;1188  let NumMicroOps = 3;1189}1190def : InstRW<[ADLPWriteResGroup95], (instrs LEAVE64)>;1191 1192def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1193  let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];1194  let Latency = AlderlakePModel.MaxLatency;1195  let NumMicroOps = 14;1196}1197def : InstRW<[ADLPWriteResGroup96], (instrs LGDT64m)>;1198 1199def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1200  let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];1201  let Latency = AlderlakePModel.MaxLatency;1202  let NumMicroOps = 14;1203}1204def : InstRW<[ADLPWriteResGroup97], (instrs LIDT64m)>;1205 1206def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1207  let ReleaseAtCycles = [5, 3, 2, 1, 1];1208  let Latency = AlderlakePModel.MaxLatency;1209  let NumMicroOps = 12;1210}1211def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16m)>;1212 1213def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1214  let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];1215  let Latency = AlderlakePModel.MaxLatency;1216  let NumMicroOps = 11;1217}1218def : InstRW<[ADLPWriteResGroup99], (instrs LLDT16r)>;1219 1220def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1221  let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];1222  let Latency = AlderlakePModel.MaxLatency;1223  let NumMicroOps = 27;1224}1225def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16m)>;1226 1227def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1228  let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];1229  let Latency = AlderlakePModel.MaxLatency;1230  let NumMicroOps = 22;1231}1232def : InstRW<[ADLPWriteResGroup101], (instrs LMSW16r)>;1233 1234def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {1235  let ReleaseAtCycles = [2, 1];1236  let Latency = 5;1237  let NumMicroOps = 3;1238}1239def : InstRW<[ADLPWriteResGroup102], (instregex "^LODS(L|Q)$")>;1240 1241def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1242  let ReleaseAtCycles = [2, 4, 1];1243  let Latency = 3;1244  let NumMicroOps = 7;1245}1246def : InstRW<[ADLPWriteResGroup103], (instrs LOOP)>;1247 1248def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1249  let ReleaseAtCycles = [4, 6, 1];1250  let Latency = 3;1251  let NumMicroOps = 11;1252}1253def : InstRW<[ADLPWriteResGroup104], (instrs LOOPE)>;1254 1255def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1256  let ReleaseAtCycles = [4, 6, 1];1257  let Latency = 2;1258  let NumMicroOps = 11;1259}1260def : InstRW<[ADLPWriteResGroup105], (instrs LOOPNE)>;1261 1262def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {1263  let Latency = 7;1264  let NumMicroOps = 3;1265}1266def : InstRW<[ADLPWriteResGroup106], (instrs LRET64)>;1267 1268def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1269  let ReleaseAtCycles = [1, 5, 3, 3, 1];1270  let Latency = 70;1271  let NumMicroOps = 13;1272}1273def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rm$")>;1274 1275def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1276  let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];1277  let Latency = 63;1278  let NumMicroOps = 15;1279}1280def : InstRW<[ADLPWriteResGroup108], (instregex "^LSL(16|32|64)rr$")>;1281 1282def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_10, ADLPPort05]> {1283  let Latency = 24;1284  let NumMicroOps = 3;1285}1286def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVT(T?)PD2PIrm$")>;1287 1288def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {1289  let Latency = 8;1290  let NumMicroOps = 2;1291}1292def : InstRW<[ADLPWriteResGroup110], (instregex "^MMX_CVT(T?)PD2PIrr$")>;1293 1294def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {1295  let Latency = 6;1296  let NumMicroOps = 2;1297}1298def : InstRW<[ADLPWriteResGroup111], (instrs MMX_CVTPI2PDrr)>;1299 1300def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {1301  let Latency = 7;1302  let NumMicroOps = 2;1303}1304def : InstRW<[ADLPWriteResGroup112], (instrs MMX_CVTPI2PSrr)>;1305 1306def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_10]> {1307  let Latency = 13;1308  let NumMicroOps = 2;1309}1310def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_CVT(T?)PS2PIrm$")>;1311 1312def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {1313  let Latency = 9;1314  let NumMicroOps = 2;1315}1316def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_CVT(T?)PS2PIrr$")>;1317 1318def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {1319  let ReleaseAtCycles = [2, 1, 1];1320  let Latency = 12;1321  let NumMicroOps = 4;1322}1323def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MASKMOVQ((64)?)$")>;1324 1325def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1326  let Latency = 18;1327  let NumMicroOps = 2;1328}1329def : InstRW<[ADLPWriteResGroup116], (instrs MMX_MOVD64mr)>;1330 1331def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_10]> {1332  let Latency = 8;1333}1334def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",1335                                                "^VBROADCAST(F|I)128rm$",1336                                                "^VBROADCASTS(D|S)Yrm$",1337                                                "^VMOV(D|SH|SL)DUPYrm$",1338                                                "^VPBROADCAST(D|Q)Yrm$")>;1339def : InstRW<[ADLPWriteResGroup117], (instrs MMX_MOVD64to64rm)>;1340 1341def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {1342  let Latency = 3;1343  let NumMicroOps = 2;1344}1345def : InstRW<[ADLPWriteResGroup118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;1346 1347def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {1348  let Latency = 3;1349  let NumMicroOps = 2;1350}1351def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;1352 1353def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {1354  let ReleaseAtCycles = [1, 2];1355  let Latency = 12;1356  let NumMicroOps = 3;1357}1358def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;1359def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;1360 1361def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort05]> {1362  let ReleaseAtCycles = [2];1363  let Latency = 4;1364  let NumMicroOps = 2;1365}1366def : InstRW<[ADLPWriteResGroup121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;1367def : InstRW<[ADLPWriteResGroup121], (instrs MMX_PACKUSWBrr)>;1368def : InstRW<[ADLPWriteResGroup121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrri)>;1369 1370def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_10]> {1371  let Latency = 9;1372  let NumMicroOps = 2;1373}1374def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;1375 1376def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_10, ADLPPort05]> {1377  let ReleaseAtCycles = [1, 1, 2];1378  let Latency = 11;1379  let NumMicroOps = 4;1380}1381def : InstRW<[ADLPWriteResGroup123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;1382 1383def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {1384  let ReleaseAtCycles = [1, 2];1385  let Latency = 3;1386  let NumMicroOps = 3;1387}1388def : InstRW<[ADLPWriteResGroup124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;1389 1390def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {1391  let Latency = 9;1392  let NumMicroOps = 2;1393}1394def : InstRW<[ADLPWriteResGroup125], (instregex "^VPBROADCAST(B|W)Yrm$")>;1395def : InstRW<[ADLPWriteResGroup125, ReadAfterLd], (instrs MMX_PINSRWrmi)>;1396def : InstRW<[ADLPWriteResGroup125, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;1397 1398def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {1399  let Latency = 5;1400  let NumMicroOps = 2;1401}1402def : InstRW<[ADLPWriteResGroup126], (instregex "^MOV16ao(16|32|64)$")>;1403 1404def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {1405  let Latency = 12;1406  let NumMicroOps = 3;1407}1408def : InstRW<[ADLPWriteResGroup127], (instregex "^PUSH(F|G)S(16|32)$")>;1409def : InstRW<[ADLPWriteResGroup127], (instrs MOV16ms,1410                                             MOVBE32mr)>;1411 1412def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01]> {1413  let NumMicroOps = 2;1414}1415def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(16|32|64)rs$",1416                                                "^S(TR|LDT)16r$")>;1417 1418def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort02_03_10]>;1419def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV32ao(16|32|64)$")>;1420def : InstRW<[ADLPWriteResGroup129], (instrs MOV64ao64)>;1421 1422def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {1423  let NumMicroOps = 3;1424}1425def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV(8|32)o(16|32)a$",1426                                                "^MOV(8|32|64)o64a$")>;1427 1428def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_01_05_06_11]> {1429  let Latency = 0;1430}1431def : InstRW<[ADLPWriteResGroup131], (instregex "^MOV32rr((_REV)?)$",1432                                                "^MOVZX(32|64)rr8$")>;1433def : InstRW<[ADLPWriteResGroup131], (instrs MOVZX32rr8_NOREX)>;1434 1435def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort02_03_10]> {1436  let Latency = 5;1437}1438def : InstRW<[ADLPWriteResGroup132], (instrs MOV64ao32)>;1439 1440def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1441  let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];1442  let Latency = 217;1443  let NumMicroOps = 48;1444}1445def : InstRW<[ADLPWriteResGroup133], (instrs MOV64dr)>;1446 1447def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1448  let Latency = 12;1449  let NumMicroOps = 2;1450}1451def : InstRW<[ADLPWriteResGroup134], (instrs MOV64o32a)>;1452 1453def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort05]> {1454  let Latency = AlderlakePModel.MaxLatency;1455  let NumMicroOps = 3;1456}1457def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rc)>;1458 1459def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort05]> {1460  let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];1461  let Latency = 181;1462  let NumMicroOps = 24;1463}1464def : InstRW<[ADLPWriteResGroup136], (instrs MOV64rd)>;1465 1466def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {1467  let NumMicroOps = 2;1468}1469def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV8ao(16|32|64)$")>;1470 1471def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1472  let Latency = 13;1473  let NumMicroOps = 2;1474}1475def : InstRW<[ADLPWriteResGroup138], (instregex "^MOV8m(i|r)$")>;1476def : InstRW<[ADLPWriteResGroup138], (instrs MOV8mr_NOREX)>;1477 1478def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {1479  let Latency = 12;1480  let NumMicroOps = 3;1481}1482def : InstRW<[ADLPWriteResGroup139], (instrs MOVBE16mr)>;1483 1484def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort02_03_10]> {1485  let Latency = 7;1486  let NumMicroOps = 3;1487}1488def : InstRW<[ADLPWriteResGroup140], (instrs MOVBE16rm)>;1489 1490def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_10]> {1491  let Latency = 6;1492  let NumMicroOps = 2;1493}1494def : InstRW<[ADLPWriteResGroup141], (instrs MOVBE32rm)>;1495 1496def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {1497  let Latency = 12;1498  let NumMicroOps = 4;1499}1500def : InstRW<[ADLPWriteResGroup142], (instrs MOVBE64mr,1501                                             PUSHF16,1502                                             SLDT16m,1503                                             STRm)>;1504 1505def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_10]> {1506  let Latency = 7;1507  let NumMicroOps = 3;1508}1509def : InstRW<[ADLPWriteResGroup143], (instrs MOVBE64rm)>;1510 1511def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1512  let NumMicroOps = 4;1513}1514def : InstRW<[ADLPWriteResGroup144], (instregex "^MOVDIR64B(16|32|64)$")>;1515 1516def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1517  let Latency = 511;1518  let NumMicroOps = 2;1519}1520def : InstRW<[ADLPWriteResGroup145], (instrs MOVDIRI32)>;1521 1522def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1523  let Latency = 514;1524  let NumMicroOps = 2;1525}1526def : InstRW<[ADLPWriteResGroup146], (instrs MOVDIRI64)>;1527 1528def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_10]> {1529  let Latency = 8;1530  let NumMicroOps = 2;1531}1532def : InstRW<[ADLPWriteResGroup147, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",1533                                                                 "^(V?)SHUFP(D|S)rmi$")>;1534 1535def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1536  let Latency = 512;1537  let NumMicroOps = 2;1538}1539def : InstRW<[ADLPWriteResGroup148], (instrs MOVNTDQmr)>;1540 1541def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1542  let Latency = 518;1543  let NumMicroOps = 2;1544}1545def : InstRW<[ADLPWriteResGroup149], (instrs MOVNTImr)>;1546 1547def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1548  let ReleaseAtCycles = [4, 1, 1, 1];1549  let Latency = 8;1550  let NumMicroOps = 7;1551}1552def : InstRW<[ADLPWriteResGroup150], (instrs MOVSB)>;1553 1554def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05]>;1555def : InstRW<[ADLPWriteResGroup151], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",1556                                                "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",1557                                                "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;1558def : InstRW<[ADLPWriteResGroup151], (instrs VPBLENDDrri)>;1559 1560def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1561  let ReleaseAtCycles = [4, 1, 1, 1];1562  let Latency = 7;1563  let NumMicroOps = 7;1564}1565def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVS(L|Q|W)$")>;1566 1567def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_10]> {1568  let Latency = 6;1569}1570def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(16|32|64)rm(16|32)$",1571                                                "^MOVSX(32|64)rm8$")>;1572def : InstRW<[ADLPWriteResGroup153], (instrs MOVSX32rm8_NOREX)>;1573 1574def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort01_05_11, ADLPPort02_03_10]> {1575  let Latency = 6;1576  let NumMicroOps = 2;1577}1578def : InstRW<[ADLPWriteResGroup154], (instrs MOVSX16rm8)>;1579 1580def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort01_05_11]>;1581def : InstRW<[ADLPWriteResGroup155], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;1582def : InstRW<[ADLPWriteResGroup155], (instrs MOVSX32rr8_NOREX)>;1583 1584def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {1585  let Latency = 11;1586  let NumMicroOps = 2;1587}1588def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_F(32|64)m$")>;1589 1590def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {1591  let Latency = 14;1592  let NumMicroOps = 3;1593}1594def : InstRW<[ADLPWriteResGroup157], (instregex "^MUL_FI(16|32)m$")>;1595 1596def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00]> {1597  let Latency = 4;1598}1599def : InstRW<[ADLPWriteResGroup158], (instregex "^MUL_F(P?)rST0$")>;1600def : InstRW<[ADLPWriteResGroup158], (instrs MUL_FST0r)>;1601 1602def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {1603  let ReleaseAtCycles = [7, 1, 2];1604  let Latency = 20;1605  let NumMicroOps = 10;1606}1607def : InstRW<[ADLPWriteResGroup159], (instrs MWAITrr)>;1608 1609def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1610  let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];1611  let Latency = 35;1612  let NumMicroOps = 79;1613}1614def : InstRW<[ADLPWriteResGroup160], (instrs OUT16ir)>;1615 1616def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1617  let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];1618  let Latency = 35;1619  let NumMicroOps = 79;1620}1621def : InstRW<[ADLPWriteResGroup161], (instrs OUT16rr)>;1622 1623def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1624  let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];1625  let Latency = 35;1626  let NumMicroOps = 85;1627}1628def : InstRW<[ADLPWriteResGroup162], (instrs OUT32ir)>;1629 1630def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1631  let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];1632  let Latency = 35;1633  let NumMicroOps = 85;1634}1635def : InstRW<[ADLPWriteResGroup163], (instrs OUT32rr)>;1636 1637def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1638  let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];1639  let Latency = 35;1640  let NumMicroOps = 73;1641}1642def : InstRW<[ADLPWriteResGroup164], (instrs OUT8ir)>;1643 1644def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1645  let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];1646  let Latency = 35;1647  let NumMicroOps = 73;1648}1649def : InstRW<[ADLPWriteResGroup165], (instrs OUT8rr)>;1650 1651def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1652  let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];1653  let Latency = AlderlakePModel.MaxLatency;1654  let NumMicroOps = 80;1655}1656def : InstRW<[ADLPWriteResGroup166], (instrs OUTSB)>;1657 1658def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1659  let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];1660  let Latency = AlderlakePModel.MaxLatency;1661  let NumMicroOps = 89;1662}1663def : InstRW<[ADLPWriteResGroup167], (instrs OUTSL)>;1664 1665def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {1666  let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];1667  let Latency = AlderlakePModel.MaxLatency;1668  let NumMicroOps = 83;1669}1670def : InstRW<[ADLPWriteResGroup168], (instrs OUTSW)>;1671 1672def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {1673  let Latency = 10;1674  let NumMicroOps = 2;1675}1676def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",1677                                                                 "^(V?)PCMPGTQrm$")>;1678 1679def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort05]> {1680  let Latency = 3;1681}1682def : InstRW<[ADLPWriteResGroup170], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",1683                                                "^(V?)PCMPGTQrr$",1684                                                "^VPACK(S|U)S(DW|WB)Yrr$")>;1685def : InstRW<[ADLPWriteResGroup170], (instrs VPCMPGTQYrr)>;1686 1687def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_10]> {1688  let Latency = 8;1689  let NumMicroOps = 2;1690}1691def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;1692def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;1693 1694def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {1695  let Latency = 8;1696  let NumMicroOps = 2;1697}1698def : InstRW<[ADLPWriteResGroup172], (instregex "^VPBROADCAST(B|W)rm$")>;1699def : InstRW<[ADLPWriteResGroup172, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;1700 1701def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort05]>;1702def : InstRW<[ADLPWriteResGroup173], (instregex "^(V?)PALIGNRrri$",1703                                                "^VPBROADCAST(B|D|Q|W)rr$")>;1704def : InstRW<[ADLPWriteResGroup173], (instrs VPALIGNRYrri)>;1705 1706def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {1707  let Latency = 4;1708  let NumMicroOps = 2;1709}1710def : InstRW<[ADLPWriteResGroup174], (instrs PAUSE)>;1711 1712def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_10]> {1713  let Latency = 8;1714  let NumMicroOps = 2;1715}1716def : InstRW<[ADLPWriteResGroup175, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;1717 1718def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {1719  let Latency = 12;1720  let NumMicroOps = 3;1721}1722def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PEXTR(D|Q)mri$")>;1723 1724def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_10]> {1725  let ReleaseAtCycles = [1, 2, 1];1726  let Latency = 9;1727  let NumMicroOps = 4;1728}1729def : InstRW<[ADLPWriteResGroup177, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;1730 1731def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {1732  let ReleaseAtCycles = [1, 2];1733  let Latency = 2;1734  let NumMicroOps = 3;1735}1736def : InstRW<[ADLPWriteResGroup178], (instregex "^(V?)PH(ADD|SUB)SWrr$",1737                                                "^VPH(ADD|SUB)SWYrr$")>;1738 1739def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1740  let Latency = 12;1741  let NumMicroOps = 3;1742}1743def : InstRW<[ADLPWriteResGroup179], (instregex "^POP(16|32|64)rmm$",1744                                                "^PUSH(16|32)rmm$")>;1745 1746def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort02_03]> {1747  let Latency = 5;1748}1749def : InstRW<[ADLPWriteResGroup180], (instregex "^POPA(16|32)$",1750                                                "^PREFETCHIT(0|1)$")>;1751def : InstRW<[ADLPWriteResGroup180], (instrs POPF32)>;1752 1753def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10]> {1754  let ReleaseAtCycles = [6, 2, 1, 1];1755  let Latency = 5;1756  let NumMicroOps = 10;1757}1758def : InstRW<[ADLPWriteResGroup181], (instrs POPF16)>;1759 1760def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_10]> {1761  let ReleaseAtCycles = [2, 1, 1];1762  let Latency = 5;1763  let NumMicroOps = 7;1764}1765def : InstRW<[ADLPWriteResGroup182], (instrs POPF64)>;1766 1767def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort02_03_10]> {1768  let Latency = 0;1769}1770def : InstRW<[ADLPWriteResGroup183], (instregex "^PREFETCHT(0|1|2)$")>;1771def : InstRW<[ADLPWriteResGroup183], (instrs PREFETCHNTA)>;1772 1773def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10, ADLPPort06]> {1774  let ReleaseAtCycles = [1, 1, 2];1775  let Latency = AlderlakePModel.MaxLatency;1776  let NumMicroOps = 4;1777}1778def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITE((64)?)m$")>;1779 1780def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort06]> {1781  let ReleaseAtCycles = [1, 2];1782  let Latency = AlderlakePModel.MaxLatency;1783  let NumMicroOps = 3;1784}1785def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITE64r)>;1786 1787def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort06]> {1788  let ReleaseAtCycles = [2, 2];1789  let Latency = AlderlakePModel.MaxLatency;1790  let NumMicroOps = 4;1791}1792def : InstRW<[ADLPWriteResGroup186], (instrs PTWRITEr)>;1793 1794def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {1795  let NumMicroOps = 2;1796}1797def : InstRW<[ADLPWriteResGroup187], (instregex "^PUSH64r((mr)?)$")>;1798 1799def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {1800  let NumMicroOps = 3;1801}1802def : InstRW<[ADLPWriteResGroup188], (instrs PUSH64rmm)>;1803 1804def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;1805def : InstRW<[ADLPWriteResGroup189], (instregex "^PUSHA(16|32)$",1806                                                "^ST_F(32|64)m$")>;1807def : InstRW<[ADLPWriteResGroup189], (instrs PUSHF32)>;1808 1809def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {1810  let Latency = 4;1811  let NumMicroOps = 4;1812}1813def : InstRW<[ADLPWriteResGroup190], (instrs PUSHF64)>;1814 1815def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {1816  let NumMicroOps = 3;1817}1818def : InstRW<[ADLPWriteResGroup191], (instregex "^PUSH(F|G)S64$")>;1819 1820def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1821  let ReleaseAtCycles = [2, 3, 2];1822  let Latency = 8;1823  let NumMicroOps = 7;1824}1825def : InstRW<[ADLPWriteResGroup192], (instregex "^RC(L|R)(16|32|64)rCL$")>;1826 1827def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {1828  let ReleaseAtCycles = [1, 2];1829  let Latency = 13;1830  let NumMicroOps = 3;1831}1832def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;1833 1834def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1835  let ReleaseAtCycles = [1, 5, 2];1836  let Latency = 20;1837  let NumMicroOps = 8;1838}1839def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instrs RCL8mCL)>;1840 1841def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1842  let ReleaseAtCycles = [2, 5, 2];1843  let Latency = 7;1844  let NumMicroOps = 9;1845}1846def : InstRW<[ADLPWriteResGroup195], (instrs RCL8rCL)>;1847 1848def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1849  let ReleaseAtCycles = [2, 4, 3];1850  let Latency = 20;1851  let NumMicroOps = 9;1852}1853def : InstRW<[ADLPWriteResGroup196, WriteRMW], (instrs RCR8mCL)>;1854 1855def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1856  let ReleaseAtCycles = [3, 4, 3];1857  let Latency = 9;1858  let NumMicroOps = 10;1859}1860def : InstRW<[ADLPWriteResGroup197], (instrs RCR8rCL)>;1861 1862def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_11, ADLPPort05]> {1863  let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];1864  let Latency = AlderlakePModel.MaxLatency;1865  let NumMicroOps = 54;1866}1867def : InstRW<[ADLPWriteResGroup198], (instrs RDMSR)>;1868 1869def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort01]> {1870  let Latency = AlderlakePModel.MaxLatency;1871}1872def : InstRW<[ADLPWriteResGroup199], (instrs RDPID64)>;1873 1874def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {1875  let Latency = AlderlakePModel.MaxLatency;1876  let NumMicroOps = 3;1877}1878def : InstRW<[ADLPWriteResGroup200], (instrs RDPKRUr)>;1879 1880def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort05]> {1881  let ReleaseAtCycles = [9, 6, 2, 1];1882  let Latency = AlderlakePModel.MaxLatency;1883  let NumMicroOps = 18;1884}1885def : InstRW<[ADLPWriteResGroup201], (instrs RDPMC)>;1886 1887def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort05]> {1888  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];1889  let Latency = 1386;1890  let NumMicroOps = 25;1891}1892def : InstRW<[ADLPWriteResGroup202], (instrs RDRAND16r)>;1893 1894def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort05]> {1895  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];1896  let Latency = AlderlakePModel.MaxLatency;1897  let NumMicroOps = 25;1898}1899def : InstRW<[ADLPWriteResGroup203], (instregex "^RDRAND(32|64)r$")>;1900 1901def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1902  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];1903  let Latency = 1381;1904  let NumMicroOps = 25;1905}1906def : InstRW<[ADLPWriteResGroup204], (instrs RDSEED16r)>;1907 1908def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort05]> {1909  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];1910  let Latency = AlderlakePModel.MaxLatency;1911  let NumMicroOps = 25;1912}1913def : InstRW<[ADLPWriteResGroup205], (instregex "^RDSEED(32|64)r$")>;1914 1915def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort05]> {1916  let ReleaseAtCycles = [5, 6, 3, 1];1917  let Latency = 18;1918  let NumMicroOps = 15;1919}1920def : InstRW<[ADLPWriteResGroup206], (instrs RDTSC)>;1921 1922def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {1923  let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];1924  let Latency = 42;1925  let NumMicroOps = 21;1926}1927def : InstRW<[ADLPWriteResGroup207], (instrs RDTSCP)>;1928 1929def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10]> {1930  let Latency = 7;1931  let NumMicroOps = 2;1932}1933def : InstRW<[ADLPWriteResGroup208], (instrs RET64)>;1934 1935def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10]> {1936  let ReleaseAtCycles = [2, 1];1937  let Latency = 6;1938  let NumMicroOps = 3;1939}1940def : InstRW<[ADLPWriteResGroup209], (instregex "^RETI(16|32|64)$")>;1941 1942def ADLPWriteResGroup210 : SchedWriteRes<[]>;1943def : InstRW<[ADLPWriteResGroup210], (instrs REX64_PREFIX)>;1944 1945def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {1946  let ReleaseAtCycles = [2];1947  let Latency = 12;1948  let NumMicroOps = 2;1949}1950def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;1951 1952def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {1953  let ReleaseAtCycles = [2];1954  let NumMicroOps = 2;1955}1956def : InstRW<[ADLPWriteResGroup212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;1957 1958def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {1959  let ReleaseAtCycles = [2];1960  let Latency = 13;1961  let NumMicroOps = 2;1962}1963def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",1964                                                          "^(RO|SH)L8mCL$",1965                                                          "^(RO|SA|SH)R8mCL$")>;1966 1967def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {1968  let ReleaseAtCycles = [2];1969  let Latency = 4;1970  let NumMicroOps = 2;1971}1972def : InstRW<[ADLPWriteResGroup214], (instrs SAHF)>;1973 1974def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {1975  let Latency = 13;1976}1977def : InstRW<[ADLPWriteResGroup215, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",1978                                                          "^SHL8m(1|i)$")>;1979 1980def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_10]> {1981  let Latency = 8;1982  let NumMicroOps = 2;1983}1984def : InstRW<[ADLPWriteResGroup216, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",1985                                                                                                                              "^SHLX(32|64)rm$")>;1986 1987def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_06]> {1988  let Latency = 3;1989}1990def : InstRW<[ADLPWriteResGroup217], (instregex "^S(A|H)RX(32|64)rr$",1991                                                "^SHLX(32|64)rr$")>;1992 1993def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {1994  let ReleaseAtCycles = [2, 2, 1, 1, 1];1995  let Latency = AlderlakePModel.MaxLatency;1996  let NumMicroOps = 7;1997}1998def : InstRW<[ADLPWriteResGroup218], (instrs SERIALIZE)>;1999 2000def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {2001  let Latency = 2;2002  let NumMicroOps = 2;2003}2004def : InstRW<[ADLPWriteResGroup219], (instrs SFENCE)>;2005 2006def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {2007  let ReleaseAtCycles = [1, 2, 2, 2];2008  let Latency = 21;2009  let NumMicroOps = 7;2010}2011def : InstRW<[ADLPWriteResGroup220], (instregex "^S(G|I)DT64m$")>;2012 2013def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_10, ADLPPort05]> {2014  let Latency = 9;2015  let NumMicroOps = 3;2016}2017def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;2018 2019def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {2020  let Latency = 2;2021  let NumMicroOps = 2;2022}2023def : InstRW<[ADLPWriteResGroup222], (instrs SHA1MSG1rr)>;2024 2025def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_10]> {2026  let ReleaseAtCycles = [2, 2, 1, 2, 1];2027  let Latency = 13;2028  let NumMicroOps = 8;2029}2030def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;2031 2032def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {2033  let ReleaseAtCycles = [2, 2, 1, 2];2034  let Latency = 6;2035  let NumMicroOps = 7;2036}2037def : InstRW<[ADLPWriteResGroup224], (instrs SHA1MSG2rr)>;2038 2039def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_10]> {2040  let Latency = 8;2041  let NumMicroOps = 4;2042}2043def : InstRW<[ADLPWriteResGroup225, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;2044 2045def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {2046  let Latency = 3;2047  let NumMicroOps = 3;2048}2049def : InstRW<[ADLPWriteResGroup226], (instrs SHA1NEXTErr)>;2050 2051def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {2052  let Latency = 13;2053  let NumMicroOps = 2;2054}2055def : InstRW<[ADLPWriteResGroup227, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,2056                                                              SHA256RNDS2rm)>;2057 2058def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort05]> {2059  let Latency = 6;2060}2061def : InstRW<[ADLPWriteResGroup228], (instrs SHA1RNDS4rri,2062                                             SHA256RNDS2rr)>;2063 2064def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_10, ADLPPort05]> {2065  let ReleaseAtCycles = [3, 2, 1, 1, 1];2066  let Latency = 12;2067  let NumMicroOps = 8;2068}2069def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;2070 2071def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {2072  let ReleaseAtCycles = [3, 2, 1, 1];2073  let Latency = 5;2074  let NumMicroOps = 7;2075}2076def : InstRW<[ADLPWriteResGroup230], (instrs SHA256MSG1rr)>;2077 2078def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {2079  let ReleaseAtCycles = [1, 2];2080  let Latency = 13;2081  let NumMicroOps = 3;2082}2083def : InstRW<[ADLPWriteResGroup231, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;2084 2085def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort05]> {2086  let ReleaseAtCycles = [2];2087  let Latency = 6;2088  let NumMicroOps = 2;2089}2090def : InstRW<[ADLPWriteResGroup232], (instrs SHA256MSG2rr)>;2091 2092def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort07_08]> {2093  let Latency = 13;2094  let NumMicroOps = 5;2095}2096def : InstRW<[ADLPWriteResGroup233], (instrs SHRD16mri8)>;2097 2098def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01]> {2099  let Latency = 6;2100  let NumMicroOps = 2;2101}2102def : InstRW<[ADLPWriteResGroup234], (instregex "^SLDT(32|64)r$")>;2103 2104def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort05]> {2105  let NumMicroOps = 2;2106}2107def : InstRW<[ADLPWriteResGroup235], (instrs SMSW16r)>;2108 2109def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort05]> {2110  let Latency = AlderlakePModel.MaxLatency;2111  let NumMicroOps = 2;2112}2113def : InstRW<[ADLPWriteResGroup236], (instregex "^SMSW(32|64)r$")>;2114 2115def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_10]> {2116  let Latency = 24;2117  let NumMicroOps = 2;2118}2119def : InstRW<[ADLPWriteResGroup237, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;2120 2121def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {2122  let Latency = 6;2123  let NumMicroOps = 2;2124}2125def : InstRW<[ADLPWriteResGroup238], (instrs STD)>;2126 2127def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01]> {2128  let ReleaseAtCycles = [1, 4, 1];2129  let Latency = AlderlakePModel.MaxLatency;2130  let NumMicroOps = 6;2131}2132def : InstRW<[ADLPWriteResGroup239], (instrs STI)>;2133 2134def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {2135  let ReleaseAtCycles = [2, 1, 1];2136  let Latency = 8;2137  let NumMicroOps = 4;2138}2139def : InstRW<[ADLPWriteResGroup240], (instrs STOSB)>;2140 2141def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort04_09, ADLPPort07_08]> {2142  let ReleaseAtCycles = [2, 1, 1];2143  let Latency = 7;2144  let NumMicroOps = 4;2145}2146def : InstRW<[ADLPWriteResGroup241], (instregex "^STOS(L|Q|W)$")>;2147 2148def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort01]> {2149  let Latency = 5;2150  let NumMicroOps = 2;2151}2152def : InstRW<[ADLPWriteResGroup242], (instregex "^STR(32|64)r$")>;2153 2154def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00]> {2155  let Latency = 2;2156}2157def : InstRW<[ADLPWriteResGroup243], (instregex "^(TST|XAM)_F$")>;2158def : InstRW<[ADLPWriteResGroup243], (instrs UCOM_FPPr)>;2159 2160def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_10]> {2161  let ReleaseAtCycles = [3, 1];2162  let Latency = 9;2163  let NumMicroOps = 4;2164}2165def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;2166def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;2167 2168def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {2169  let ReleaseAtCycles = [3];2170  let Latency = 3;2171  let NumMicroOps = 3;2172}2173def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rrr$")>;2174def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrrr)>;2175 2176def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_10]> {2177  let ReleaseAtCycles = [6, 7, 18];2178  let Latency = 81;2179  let NumMicroOps = 31;2180}2181def : InstRW<[ADLPWriteResGroup246], (instrs VERRm)>;2182 2183def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_10]> {2184  let ReleaseAtCycles = [6, 7, 17];2185  let Latency = 74;2186  let NumMicroOps = 30;2187}2188def : InstRW<[ADLPWriteResGroup247], (instrs VERRr)>;2189 2190def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_10]> {2191  let ReleaseAtCycles = [5, 8, 21];2192  let Latency = 81;2193  let NumMicroOps = 34;2194}2195def : InstRW<[ADLPWriteResGroup248], (instrs VERWm)>;2196 2197def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_10]> {2198  let ReleaseAtCycles = [5, 8, 20];2199  let Latency = 74;2200  let NumMicroOps = 33;2201}2202def : InstRW<[ADLPWriteResGroup249], (instrs VERWr)>;2203 2204def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_10]> {2205  let ReleaseAtCycles = [1, 1, 2, 4];2206  let Latency = 29;2207  let NumMicroOps = 8;2208}2209def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",2210                                                                               "^VPGATHER(D|Q)QYrm$")>;2211def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,2212                                                                            VPGATHERQDYrm)>;2213 2214def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_10]> {2215  let ReleaseAtCycles = [1, 1, 1, 2];2216  let Latency = 20;2217  let NumMicroOps = 5;2218}2219def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",2220                                                                               "^VPGATHER(D|Q)Qrm$")>;2221def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,2222                                                                            VPGATHERQDrm)>;2223 2224def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_10]> {2225  let ReleaseAtCycles = [1, 1, 2, 8];2226  let Latency = 30;2227  let NumMicroOps = 12;2228}2229def : InstRW<[ADLPWriteResGroup252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,2230                                                                            VPGATHERDDYrm)>;2231 2232def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_10]> {2233  let ReleaseAtCycles = [1, 1, 2, 4];2234  let Latency = 28;2235  let NumMicroOps = 8;2236}2237def : InstRW<[ADLPWriteResGroup253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,2238                                                                            VPGATHERDDrm)>;2239 2240def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {2241  let ReleaseAtCycles = [1, 2];2242  let Latency = 5;2243  let NumMicroOps = 3;2244}2245def : InstRW<[ADLPWriteResGroup254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;2246 2247def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_10]> {2248  let Latency = 9;2249  let NumMicroOps = 2;2250}2251def : InstRW<[ADLPWriteResGroup255, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$",2252                                                                 "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;2253 2254def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_10]> {2255  let Latency = 7;2256  let NumMicroOps = 3;2257}2258def : InstRW<[ADLPWriteResGroup256], (instrs VLDMXCSR)>;2259 2260def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {2261  let ReleaseAtCycles = [8, 1, 1, 1, 1, 1, 2, 3];2262  let Latency = 40;2263  let NumMicroOps = 18;2264}2265def : InstRW<[ADLPWriteResGroup257], (instrs VMCLEARm)>;2266 2267def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort00]> {2268  let Latency = 5;2269}2270def : InstRW<[ADLPWriteResGroup258], (instregex "^VMOVMSKP(D|S)Yrr$")>;2271 2272def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {2273  let Latency = 521;2274  let NumMicroOps = 2;2275}2276def : InstRW<[ADLPWriteResGroup259], (instrs VMOVNTDQmr)>;2277 2278def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {2279  let Latency = 473;2280  let NumMicroOps = 2;2281}2282def : InstRW<[ADLPWriteResGroup260], (instrs VMOVNTPDmr)>;2283 2284def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {2285  let Latency = 494;2286  let NumMicroOps = 2;2287}2288def : InstRW<[ADLPWriteResGroup261], (instrs VMOVNTPSYmr)>;2289 2290def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {2291  let Latency = 470;2292  let NumMicroOps = 2;2293}2294def : InstRW<[ADLPWriteResGroup262], (instrs VMOVNTPSmr)>;2295 2296def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort02_03_10, ADLPPort05]> {2297  let Latency = 11;2298  let NumMicroOps = 2;2299}2300def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;2301def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;2302def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrmi)>;2303 2304def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_10]> {2305  let Latency = 9;2306  let NumMicroOps = 2;2307}2308def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;2309def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;2310 2311def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_10]> {2312  let ReleaseAtCycles = [1, 2, 1];2313  let Latency = 10;2314  let NumMicroOps = 4;2315}2316def : InstRW<[ADLPWriteResGroup266, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;2317 2318def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11]> {2319  let ReleaseAtCycles = [1, 2, 3, 3, 1];2320  let Latency = 16;2321  let NumMicroOps = 10;2322}2323def : InstRW<[ADLPWriteResGroup267], (instrs VZEROALL)>;2324 2325def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06]> {2326  let ReleaseAtCycles = [2];2327  let Latency = 2;2328  let NumMicroOps = 2;2329}2330def : InstRW<[ADLPWriteResGroup268], (instrs WAIT)>;2331 2332def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2333  let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];2334  let Latency = AlderlakePModel.MaxLatency;2335  let NumMicroOps = 144;2336}2337def : InstRW<[ADLPWriteResGroup269], (instrs WRMSR)>;2338 2339def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06, ADLPPort01, ADLPPort05]> {2340  let ReleaseAtCycles = [2, 1, 4, 1];2341  let Latency = AlderlakePModel.MaxLatency;2342  let NumMicroOps = 8;2343}2344def : InstRW<[ADLPWriteResGroup270], (instrs WRPKRUr)>;2345 2346def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_11]> {2347  let ReleaseAtCycles = [2];2348  let Latency = 12;2349  let NumMicroOps = 2;2350}2351def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;2352 2353def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_11]> {2354  let ReleaseAtCycles = [2];2355  let Latency = 13;2356  let NumMicroOps = 2;2357}2358def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XADD8rm)>;2359 2360def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {2361  let ReleaseAtCycles = [4, 1];2362  let Latency = 39;2363  let NumMicroOps = 5;2364}2365def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;2366 2367def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {2368  let ReleaseAtCycles = [5, 1];2369  let Latency = 39;2370  let NumMicroOps = 6;2371}2372def : InstRW<[ADLPWriteResGroup274, WriteRMW], (instrs XCHG64rm)>;2373 2374def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_06]> {2375  let ReleaseAtCycles = [4, 1];2376  let Latency = 40;2377  let NumMicroOps = 5;2378}2379def : InstRW<[ADLPWriteResGroup275, WriteRMW], (instrs XCHG8rm)>;2380 2381def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {2382  let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];2383  let Latency = 17;2384  let NumMicroOps = 15;2385}2386def : InstRW<[ADLPWriteResGroup276], (instrs XCH_F)>;2387 2388def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {2389  let ReleaseAtCycles = [7, 3, 8, 5];2390  let Latency = 4;2391  let NumMicroOps = 23;2392}2393def : InstRW<[ADLPWriteResGroup277], (instrs XGETBV)>;2394 2395def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01_05_06_11, ADLPPort02_03_10]> {2396  let ReleaseAtCycles = [2, 1];2397  let Latency = 7;2398  let NumMicroOps = 3;2399}2400def : InstRW<[ADLPWriteResGroup278], (instrs XLAT)>;2401 2402def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {2403  let ReleaseAtCycles = [21, 1, 1, 8];2404  let Latency = 37;2405  let NumMicroOps = 31;2406}2407def : InstRW<[ADLPWriteResGroup279], (instregex "^XRSTOR((S|64)?)$")>;2408def : InstRW<[ADLPWriteResGroup279], (instrs XRSTORS64)>;2409 2410def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2411  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];2412  let Latency = 42;2413  let NumMicroOps = 140;2414}2415def : InstRW<[ADLPWriteResGroup280], (instrs XSAVE)>;2416 2417def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2418  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];2419  let Latency = 41;2420  let NumMicroOps = 140;2421}2422def : InstRW<[ADLPWriteResGroup281], (instrs XSAVE64)>;2423 2424def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2425  let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];2426  let Latency = 42;2427  let NumMicroOps = 151;2428}2429def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEC)>;2430 2431def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2432  let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];2433  let Latency = 42;2434  let NumMicroOps = 152;2435}2436def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEC64)>;2437 2438def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2439  let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];2440  let Latency = 46;2441  let NumMicroOps = 155;2442}2443def : InstRW<[ADLPWriteResGroup284], (instrs XSAVEOPT)>;2444 2445def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2446  let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];2447  let Latency = 46;2448  let NumMicroOps = 156;2449}2450def : InstRW<[ADLPWriteResGroup285], (instrs XSAVEOPT64)>;2451 2452def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2453  let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];2454  let Latency = 42;2455  let NumMicroOps = 184;2456}2457def : InstRW<[ADLPWriteResGroup286], (instrs XSAVES)>;2458 2459def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {2460  let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];2461  let Latency = 42;2462  let NumMicroOps = 186;2463}2464def : InstRW<[ADLPWriteResGroup287], (instrs XSAVES64)>;2465 2466def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_11, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_11, ADLPPort05]> {2467  let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];2468  let Latency = 5;2469  let NumMicroOps = 54;2470}2471def : InstRW<[ADLPWriteResGroup288], (instrs XSETBV)>;2472 2473}2474