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1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Haswell to support instruction10// scheduling and other instruction cost heuristics.11//12// Note that we define some instructions here that are not supported by haswell,13// but we still have to define them because KNL uses the HSW model.14// They are currently tagged with a comment `Unsupported = 1`.15// FIXME: Use Unsupported = 1 once KNL has its own model.16//17//===----------------------------------------------------------------------===//18 19def HaswellModel : SchedMachineModel {20 // All x86 instructions are modeled as a single micro-op, and HW can decode 421 // instructions per cycle.22 let IssueWidth = 4;23 let MicroOpBufferSize = 192; // Based on the reorder buffer.24 let LoadLatency = 5;25 let MispredictPenalty = 16;26 27 // Based on the LSD (loop-stream detector) queue size and benchmarking data.28 let LoopMicroOpBufferSize = 50;29 30 // This flag is set to allow the scheduler to assign a default model to31 // unrecognized opcodes.32 let CompleteModel = 0;33}34 35let SchedModel = HaswellModel in {36 37// Haswell can issue micro-ops to 8 different ports in one cycle.38 39// Ports 0, 1, 5, and 6 handle all computation.40// Port 4 gets the data half of stores. Store data can be available later than41// the store address, but since we don't model the latency of stores, we can42// ignore that.43// Ports 2 and 3 are identical. They handle loads and the address half of44// stores. Port 7 can handle address calculations.45def HWPort0 : ProcResource<1>;46def HWPort1 : ProcResource<1>;47def HWPort2 : ProcResource<1>;48def HWPort3 : ProcResource<1>;49def HWPort4 : ProcResource<1>;50def HWPort5 : ProcResource<1>;51def HWPort6 : ProcResource<1>;52def HWPort7 : ProcResource<1>;53 54// Many micro-ops are capable of issuing on multiple ports.55def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;56def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;57def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;58def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;59def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;60def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;61def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;62def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;63def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>;64def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;65def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;66def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;67 68// 60 Entry Unified Scheduler69def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,70 HWPort5, HWPort6, HWPort7]> {71 let BufferSize=60;72}73 74// Integer division issued on port 0.75def HWDivider : ProcResource<1>;76// FP division and sqrt on port 0.77def HWFPDivider : ProcResource<1>;78 79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 580// cycles after the memory operand.81def : ReadAdvance<ReadAfterLd, 5>;82 83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available84// until 5/6/7 cycles after the memory operand.85def : ReadAdvance<ReadAfterVecLd, 5>;86def : ReadAdvance<ReadAfterVecXLd, 6>;87def : ReadAdvance<ReadAfterVecYLd, 7>;88 89def : ReadAdvance<ReadInt2Fpu, 0>;90 91// Many SchedWrites are defined in pairs with and without a folded load.92// Instructions with folded loads are usually micro-fused, so they only appear93// as two micro-ops when queued in the reservation station.94// This multiclass defines the resource usage for variants with and without95// folded loads.96multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,97 list<ProcResourceKind> ExePorts,98 int Lat, list<int> Res = [1], int UOps = 1,99 int LoadLat = 5, int LoadUOps = 1> {100 // Register variant is using a single cycle on ExePort.101 def : WriteRes<SchedRW, ExePorts> {102 let Latency = Lat;103 let ReleaseAtCycles = Res;104 let NumMicroOps = UOps;105 }106 107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to108 // the latency (default = 5).109 def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {110 let Latency = !add(Lat, LoadLat);111 let ReleaseAtCycles = !listconcat([1], Res);112 let NumMicroOps = !add(UOps, LoadUOps);113 }114}115 116// A folded store needs a cycle on port 4 for the store data, and an extra port117// 2/3/7 cycle to recompute the address.118def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;119 120// Loads, stores, and moves, not folded with other operations.121// Store_addr on 237.122// Store_data on 4.123defm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>;124defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;125defm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>;126defm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>;127 128// Idioms that clear a register, like xorps %xmm0, %xmm0.129// These can often bypass execution ports completely.130def : WriteRes<WriteZero, []>;131 132// Model the effect of clobbering the read-write mask operand of the GATHER operation.133// Does not cost anything by itself, only has latency, matching that of the WriteLoad,134defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;135 136// Arithmetic.137defm : HWWriteResPair<WriteALU, [HWPort0156], 1>;138defm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>;139 140// Integer multiplication.141defm : HWWriteResPair<WriteIMul8, [HWPort1], 3>;142defm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>;143defm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>;144defm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;145defm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>;146defm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;147defm : HWWriteResPair<WriteMULX32, [HWPort1,HWPort06,HWPort0156], 3, [1,1,1], 3>;148defm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>;149defm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>;150defm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>;151defm : HWWriteResPair<WriteMULX64, [HWPort1,HWPort6], 3, [1,1], 2>;152defm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>;153defm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>;154def HWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }155def : WriteRes<WriteIMulHLd, []> {156 let Latency = !add(HWWriteIMulH.Latency, HaswellModel.LoadLatency);157}158 159defm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>;160defm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>;161defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;162defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;163defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;164 165// Integer shifts and rotates.166defm : HWWriteResPair<WriteShift, [HWPort06], 1>;167defm : HWWriteResPair<WriteShiftCL, [HWPort06], 3, [3], 3>;168defm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>;169defm : HWWriteResPair<WriteRotateCL, [HWPort06], 3, [3], 3>;170 171// SHLD/SHRD.172defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;173defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>;174defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>;175defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>;176 177// Branches don't produce values, so they have no latency, but they still178// consume resources. Indirect branches can fold loads.179defm : HWWriteResPair<WriteJump, [HWPort06], 1>;180 181defm : HWWriteResPair<WriteCRC32, [HWPort1], 3>;182 183defm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.184defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move.185 186def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.187def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {188 let Latency = 2;189 let NumMicroOps = 3;190}191 192defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;193defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;194defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;195defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;196defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;197defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>;198//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>;199 200// This is for simple LEAs with one or two input operands.201// The complex ones can only execute on port 1, and they require two cycles on202// the port to read all inputs. We don't model that.203def : WriteRes<WriteLEA, [HWPort15]>;204 205// Bit counts.206defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;207defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;208defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>;209defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>;210defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>;211 212// BMI1 BEXTR/BLS, BMI2 BZHI213defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;214defm : HWWriteResPair<WriteBLS, [HWPort15], 1>;215defm : HWWriteResPair<WriteBZHI, [HWPort15], 1>;216 217// TODO: Why isn't the HWDivider used?218defm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>;219defm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;220defm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;221defm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;222defm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;223defm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;224defm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;225defm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;226 227defm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>;228defm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;229defm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;230defm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;231defm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;232defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;233defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;234defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;235 236// Floating point. This covers both scalar and vector operations.237defm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>;238defm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>;239defm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>;240defm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>;241defm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>;242defm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>;243defm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>;244defm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>;245defm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>;246defm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>;247defm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>;248defm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>;249defm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>;250defm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>;251 252defm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;253defm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;254defm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;255defm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;256 257defm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>;258defm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>;259defm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>;260defm : X86WriteRes<WriteFMoveZ, [HWPort5], 1, [1], 1>; // Unsupported = 1261defm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;262 263defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>;264defm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>;265defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>;266defm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1267defm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>;268defm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>;269defm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>;270defm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1271 272defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>;273defm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>;274defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>;275defm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1276defm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>;277defm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>;278defm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>;279defm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1280 281defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;282defm : HWWriteResPair<WriteFComX, [HWPort1], 3>;283 284defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>;285defm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>;286defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>;287defm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1288defm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>;289defm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>;290defm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>;291defm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1292 293defm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;294defm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;295defm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;296defm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1297defm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>;298defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>;299defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;300defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1301 302defm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>;303defm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>;304defm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>;305defm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1306 307defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>;308defm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>;309defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>;310defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1311 312defm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>;313defm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>;314defm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;315defm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1316defm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>;317defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>;318defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;319defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1320defm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>;321 322defm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>;323defm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>;324defm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>;325defm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1326defm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>;327defm : X86WriteRes<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4>;328defm : X86WriteRes<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4>;329defm : X86WriteRes<WriteDPPSLd, [HWPort0,HWPort1,HWPort5,HWPort06,HWPort23], 20, [2,1,1,1,1], 6>;330defm : X86WriteRes<WriteDPPSYLd, [HWPort0,HWPort1,HWPort5,HWPort06,HWPort23], 21, [2,1,1,1,1], 6>;331defm : HWWriteResPair<WriteFSign, [HWPort0], 1>;332defm : HWWriteResPair<WriteFRnd, [HWPort1], 6, [2], 2, 6>;333defm : HWWriteResPair<WriteFRndY, [HWPort1], 6, [2], 2, 7>;334defm : HWWriteResPair<WriteFRndZ, [HWPort1], 6, [2], 2, 7>; // Unsupported = 1335defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>;336defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;337defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1338defm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>;339defm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>;340defm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1341defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>;342defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;343defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1344defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>;345defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>;346defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1347defm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>;348defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>;349defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1350defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>;351defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>;352defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>;353defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>;354defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1355 356// Conversion between integer and float.357defm : HWWriteResPair<WriteCvtSD2I, [HWPort1,HWPort0], 4, [1,1], 2, 5>;358defm : HWWriteResPair<WriteCvtPD2I, [HWPort1,HWPort5], 4, [1,1], 2, 6>;359defm : HWWriteResPair<WriteCvtPD2IY, [HWPort1,HWPort5], 6, [1,1], 2, 6>;360defm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1,HWPort5], 6, [1,1], 2, 6>; // Unsupported = 1361defm : HWWriteResPair<WriteCvtSS2I, [HWPort1,HWPort0], 4, [1,1], 2, 5>;362defm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3, [1], 1, 6>;363defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3, [1], 1, 7>;364defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1365 366defm : X86WriteRes<WriteCvtI2SD, [HWPort1,HWPort5], 4, [1,1], 2>;367defm : X86WriteRes<WriteCvtI2PD, [HWPort1,HWPort5], 4, [1,1], 2>;368defm : X86WriteRes<WriteCvtI2PDY, [HWPort1,HWPort5], 6, [1,1], 2>;369defm : X86WriteRes<WriteCvtI2PDZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1370defm : X86WriteRes<WriteCvtI2SDLd, [HWPort1,HWPort23], 9, [1,1], 2>;371defm : X86WriteRes<WriteCvtI2PDLd, [HWPort1,HWPort23],10, [1,1], 2>;372defm : X86WriteRes<WriteCvtI2PDYLd, [HWPort1,HWPort23],12, [1,1], 2>;373defm : X86WriteRes<WriteCvtI2PDZLd, [HWPort1,HWPort23],12, [1,1], 2>; // Unsupported = 1374defm : X86WriteRes<WriteCvtI2SS, [HWPort1,HWPort5], 4, [1,1], 2>;375defm : X86WriteRes<WriteCvtI2PS, [HWPort1], 3, [1], 1>;376defm : X86WriteRes<WriteCvtI2PSY, [HWPort1], 3, [1], 1>;377defm : X86WriteRes<WriteCvtI2PSZ, [HWPort1], 3, [1], 1>; // Unsupported = 1378defm : X86WriteRes<WriteCvtI2SSLd, [HWPort1,HWPort23], 9, [1,1], 2>;379defm : X86WriteRes<WriteCvtI2PSLd, [HWPort1,HWPort23], 9, [1,1], 2>;380defm : X86WriteRes<WriteCvtI2PSYLd, [HWPort1,HWPort23],10, [1,1], 2>;381defm : X86WriteRes<WriteCvtI2PSZLd, [HWPort1,HWPort23],10, [1,1], 2>; // Unsupported = 1382 383defm : X86WriteRes<WriteCvtSS2SD, [HWPort0,HWPort5], 2, [1,1], 2>;384defm : X86WriteRes<WriteCvtPS2PD, [HWPort0,HWPort5], 2, [1,1], 2>;385defm : X86WriteRes<WriteCvtPS2PDY, [HWPort0,HWPort5], 4, [1,1], 2>;386defm : X86WriteRes<WriteCvtPS2PDZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1387defm : X86WriteRes<WriteCvtSS2SDLd, [HWPort0,HWPort23], 7, [1,1], 2>;388defm : X86WriteRes<WriteCvtPS2PDLd, [HWPort0,HWPort23], 6, [1,1], 2>;389defm : X86WriteRes<WriteCvtPS2PDYLd, [HWPort0,HWPort23],10, [1,1], 2>;390defm : X86WriteRes<WriteCvtPS2PDZLd, [HWPort0,HWPort23],10, [1,1], 2>; // Unsupported = 1391defm : HWWriteResPair<WriteCvtSD2SS, [HWPort1,HWPort5], 4, [1,1], 2, 5>;392defm : HWWriteResPair<WriteCvtPD2PS, [HWPort1,HWPort5], 4, [1,1], 2, 6>;393defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1,HWPort5], 6, [1,1], 2, 6>;394defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1,HWPort5], 4, [1,1], 2, 6>; // Unsupported = 1395 396defm : X86WriteRes<WriteCvtPH2PS, [HWPort1,HWPort5], 2, [1,1], 2>;397defm : X86WriteRes<WriteCvtPH2PSY, [HWPort1,HWPort5], 2, [1,1], 2>;398defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort1,HWPort5], 2, [1,1], 2>; // Unsupported = 1399defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort1,HWPort23], 6, [1,1], 2>;400defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort1,HWPort23], 7, [1,1], 2>;401defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort1,HWPort23], 7, [1,1], 2>; // Unsupported = 1402 403defm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>;404defm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>;405defm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1406defm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>;407defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>;408defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1409 410// Vector integer operations.411defm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>;412defm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>;413defm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>;414defm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>;415defm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>;416defm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>;417defm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>;418defm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>;419defm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>;420defm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>;421defm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>;422defm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>;423defm : X86WriteRes<WriteVecMaskedStore32, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;424defm : X86WriteRes<WriteVecMaskedStore32Y, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;425defm : X86WriteRes<WriteVecMaskedStore64, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;426defm : X86WriteRes<WriteVecMaskedStore64Y, [HWPort0,HWPort4,HWPort23,HWPort1], 5, [1,1,1,1], 4>;427defm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>;428defm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>;429defm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>;430defm : X86WriteRes<WriteVecMoveZ, [HWPort015], 1, [1], 1>; // Unsupported = 1431defm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>;432defm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>;433 434defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>;435defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>;436defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;437defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1438defm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>;439defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;440defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1441defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>;442defm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>;443defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>;444defm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1445defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>;446defm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>;447defm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>;448defm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1449defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>;450defm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>;451defm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1452defm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>;453defm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>;454defm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>;455defm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1456defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>;457defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>;458defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;459defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1460defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>;461defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;462defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1463defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;464defm : HWWriteResPair<WriteVPMOV256, [HWPort5], 3, [1], 1, 7>;465defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;466defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>;467defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;468defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1469defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>;470defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>;471defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1472defm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>;473defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>;474defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>;475defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1476defm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>;477 478// Vector integer shifts.479defm : X86WriteRes<WriteVecShift, [HWPort0], 1, [1], 1>;480defm : X86WriteRes<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2>;481defm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>;482defm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1483defm : X86WriteRes<WriteVecShiftLd, [HWPort0,HWPort23], 6, [1,1], 2>;484defm : X86WriteRes<WriteVecShiftXLd, [HWPort0,HWPort23], 8, [1,1], 2>;485defm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>;486defm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1487 488defm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>;489defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>;490defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>;491defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1492defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>;493defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;494defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1495 496// Vector insert/extract operations.497def : WriteRes<WriteVecInsert, [HWPort5]> {498 let Latency = 2;499 let NumMicroOps = 2;500 let ReleaseAtCycles = [2];501}502def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {503 let Latency = 6;504 let NumMicroOps = 2;505}506def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;507 508def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {509 let Latency = 2;510 let NumMicroOps = 2;511}512def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {513 let Latency = 2;514 let NumMicroOps = 3;515}516 517// String instructions.518 519// Packed Compare Implicit Length Strings, Return Mask520def : WriteRes<WritePCmpIStrM, [HWPort0]> {521 let Latency = 11;522 let NumMicroOps = 3;523 let ReleaseAtCycles = [3];524}525def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {526 let Latency = 17;527 let NumMicroOps = 4;528 let ReleaseAtCycles = [3,1];529}530 531// Packed Compare Explicit Length Strings, Return Mask532def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {533 let Latency = 19;534 let NumMicroOps = 9;535 let ReleaseAtCycles = [4,3,1,1];536}537def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {538 let Latency = 25;539 let NumMicroOps = 10;540 let ReleaseAtCycles = [4,3,1,1,1];541}542 543// Packed Compare Implicit Length Strings, Return Index544def : WriteRes<WritePCmpIStrI, [HWPort0]> {545 let Latency = 11;546 let NumMicroOps = 3;547 let ReleaseAtCycles = [3];548}549def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {550 let Latency = 17;551 let NumMicroOps = 4;552 let ReleaseAtCycles = [3,1];553}554 555// Packed Compare Explicit Length Strings, Return Index556def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {557 let Latency = 18;558 let NumMicroOps = 8;559 let ReleaseAtCycles = [4,3,1];560}561def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {562 let Latency = 24;563 let NumMicroOps = 9;564 let ReleaseAtCycles = [4,3,1,1];565}566 567// MOVMSK Instructions.568def : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; }569def : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; }570def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }571def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; }572 573// AES Instructions.574def : WriteRes<WriteAESDecEnc, [HWPort5]> {575 let Latency = 7;576 let NumMicroOps = 1;577 let ReleaseAtCycles = [1];578}579def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {580 let Latency = 13;581 let NumMicroOps = 2;582 let ReleaseAtCycles = [1,1];583}584 585def : WriteRes<WriteAESIMC, [HWPort5]> {586 let Latency = 14;587 let NumMicroOps = 2;588 let ReleaseAtCycles = [2];589}590def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {591 let Latency = 20;592 let NumMicroOps = 3;593 let ReleaseAtCycles = [2,1];594}595 596def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {597 let Latency = 29;598 let NumMicroOps = 11;599 let ReleaseAtCycles = [2,7,2];600}601def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {602 let Latency = 34;603 let NumMicroOps = 11;604 let ReleaseAtCycles = [2,7,1,1];605}606 607// Carry-less multiplication instructions.608def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {609 let Latency = 11;610 let NumMicroOps = 3;611 let ReleaseAtCycles = [2,1];612}613def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {614 let Latency = 17;615 let NumMicroOps = 4;616 let ReleaseAtCycles = [2,1,1];617}618 619// Load/store MXCSR.620def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }621def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }622 623// Catch-all for expensive system instructions.624def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }625 626// Old microcoded instructions that nobody use.627def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }628 629// Fence instructions.630def : WriteRes<WriteFence, [HWPort23, HWPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }631 632// Nop, not very useful expect it provides a model for nops!633def : WriteRes<WriteNop, []>;634 635////////////////////////////////////////////////////////////////////////////////636// Horizontal add/sub instructions.637////////////////////////////////////////////////////////////////////////////////638 639defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>;640defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>;641defm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>;642defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>;643defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>;644 645//================ Exceptions ================//646 647//-- Specific Scheduling Models --//648 649// Starting with P0.650def HWWriteP0 : SchedWriteRes<[HWPort0]>;651 652def HWWriteP01 : SchedWriteRes<[HWPort01]>;653 654def HWWrite2P01 : SchedWriteRes<[HWPort01]> {655 let NumMicroOps = 2;656}657def HWWrite3P01 : SchedWriteRes<[HWPort01]> {658 let NumMicroOps = 3;659}660 661def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {662 let NumMicroOps = 2;663}664 665def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {666 let NumMicroOps = 3;667 let ReleaseAtCycles = [2, 1];668}669 670// Starting with P1.671def HWWriteP1 : SchedWriteRes<[HWPort1]>;672 673 674def HWWrite2P1 : SchedWriteRes<[HWPort1]> {675 let NumMicroOps = 2;676 let ReleaseAtCycles = [2];677}678 679// Notation:680// - r: register.681// - mm: 64 bit mmx register.682// - x = 128 bit xmm register.683// - (x)mm = mmx or xmm register.684// - y = 256 bit ymm register.685// - v = any vector register.686// - m = memory.687 688//=== Integer Instructions ===//689//-- Move instructions --//690 691// XLAT.692def HWWriteXLAT : SchedWriteRes<[]> {693 let Latency = 7;694 let NumMicroOps = 3;695}696def : InstRW<[HWWriteXLAT], (instrs XLAT)>;697 698// PUSHA.699def HWWritePushA : SchedWriteRes<[]> {700 let NumMicroOps = 19;701}702def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;703 704// POPA.705def HWWritePopA : SchedWriteRes<[]> {706 let NumMicroOps = 18;707}708def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;709 710//-- Arithmetic instructions --//711 712// BTR BTS BTC.713// m,r.714def HWWriteBTRSCmr : SchedWriteRes<[]> {715 let NumMicroOps = 11;716}717def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;718 719//-- Control transfer instructions --//720 721// CALL.722// i.723def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {724 let NumMicroOps = 4;725 let ReleaseAtCycles = [1, 2, 1];726}727def : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>;728 729// BOUND.730// r,m.731def HWWriteBOUND : SchedWriteRes<[]> {732 let NumMicroOps = 15;733}734def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;735 736// INTO.737def HWWriteINTO : SchedWriteRes<[]> {738 let NumMicroOps = 4;739}740def : InstRW<[HWWriteINTO], (instrs INTO)>;741 742//-- String instructions --//743 744// LODSB/W.745def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;746 747// LODSD/Q.748def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;749 750// MOVS.751def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {752 let Latency = 4;753 let NumMicroOps = 5;754 let ReleaseAtCycles = [2, 1, 2];755}756def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;757 758// CMPS.759def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {760 let Latency = 4;761 let NumMicroOps = 5;762 let ReleaseAtCycles = [2, 3];763}764def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;765 766//-- Other --//767 768// RDPMC.f769def HWWriteRDPMC : SchedWriteRes<[]> {770 let NumMicroOps = 34;771}772def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;773 774// RDRAND.775def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {776 let NumMicroOps = 17;777 let ReleaseAtCycles = [1, 16];778}779def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;780 781//=== Floating Point x87 Instructions ===//782//-- Move instructions --//783 784// FLD.785// m80.786def : InstRW<[HWWriteP01], (instrs LD_Frr)>;787 788// FBLD.789// m80.790def HWWriteFBLD : SchedWriteRes<[]> {791 let Latency = 47;792 let NumMicroOps = 43;793}794def : InstRW<[HWWriteFBLD], (instrs FBLDm)>;795 796// FST(P).797// r.798def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;799 800// FFREE.801def : InstRW<[HWWriteP01], (instregex "FFREE")>;802 803// FNSAVE.804def HWWriteFNSAVE : SchedWriteRes<[]> {805 let NumMicroOps = 147;806}807def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>;808 809// FRSTOR.810def HWWriteFRSTOR : SchedWriteRes<[]> {811 let NumMicroOps = 90;812}813def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>;814 815//-- Arithmetic instructions --//816 817// FCOMPP FUCOMPP.818// r.819def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;820 821// FCOMI(P) FUCOMI(P).822// m.823def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;824 825// FTST.826def : InstRW<[HWWriteP1], (instregex "TST_F")>;827 828// FXAM.829def : InstRW<[HWWrite2P1], (instrs XAM_F)>;830 831// FPREM.832def HWWriteFPREM : SchedWriteRes<[]> {833 let Latency = 19;834 let NumMicroOps = 28;835}836def : InstRW<[HWWriteFPREM], (instrs FPREM)>;837 838// FPREM1.839def HWWriteFPREM1 : SchedWriteRes<[]> {840 let Latency = 27;841 let NumMicroOps = 41;842}843def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;844 845// FRNDINT.846def HWWriteFRNDINT : SchedWriteRes<[]> {847 let Latency = 11;848 let NumMicroOps = 17;849}850def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;851 852//-- Math instructions --//853 854// FSCALE.855def HWWriteFSCALE : SchedWriteRes<[]> {856 let Latency = 75; // 49-125857 let NumMicroOps = 50; // 25-75858}859def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;860 861// FXTRACT.862def HWWriteFXTRACT : SchedWriteRes<[]> {863 let Latency = 15;864 let NumMicroOps = 17;865}866def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;867 868//=== Floating Point XMM and YMM Instructions ===//869 870// Remaining instrs.871 872def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {873 let Latency = 6;874 let NumMicroOps = 1;875 let ReleaseAtCycles = [1];876}877def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;878def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",879 "(V?)MOVSLDUPrm",880 "(V?)MOVDDUPrm",881 "VPBROADCAST(D|Q)rm")>;882 883def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {884 let Latency = 7;885 let NumMicroOps = 1;886 let ReleaseAtCycles = [1];887}888def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm,889 VBROADCASTI128rm,890 VBROADCASTSDYrm,891 VBROADCASTSSYrm,892 VMOVDDUPYrm,893 VMOVSHDUPYrm,894 VMOVSLDUPYrm)>;895def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",896 "VPBROADCAST(D|Q)Yrm")>;897 898def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {899 let Latency = 1;900 let NumMicroOps = 2;901 let ReleaseAtCycles = [1,1];902}903def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;904def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;905 906def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {907 let Latency = 1;908 let NumMicroOps = 1;909 let ReleaseAtCycles = [1];910}911def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",912 "VPSRLVQ(Y?)rr")>;913 914def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {915 let Latency = 1;916 let NumMicroOps = 1;917 let ReleaseAtCycles = [1];918}919def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",920 "UCOM_F(P?)r")>;921 922def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {923 let Latency = 1;924 let NumMicroOps = 1;925 let ReleaseAtCycles = [1];926}927def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;928 929def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {930 let Latency = 1;931 let NumMicroOps = 1;932 let ReleaseAtCycles = [1];933}934def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;935 936def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {937 let Latency = 1;938 let NumMicroOps = 1;939 let ReleaseAtCycles = [1];940}941def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;942 943def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {944 let Latency = 1;945 let NumMicroOps = 1;946 let ReleaseAtCycles = [1];947}948def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;949 950def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {951 let Latency = 1;952 let NumMicroOps = 1;953 let ReleaseAtCycles = [1];954}955def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;956 957def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {958 let Latency = 1;959 let NumMicroOps = 1;960 let ReleaseAtCycles = [1];961}962def: InstRW<[HWWriteResGroup10], (instrs SGDT64m,963 SIDT64m,964 SMSW16m,965 STRm,966 SYSCALL)>;967 968def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {969 let Latency = 7;970 let NumMicroOps = 2;971 let ReleaseAtCycles = [1,1];972}973def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;974 975def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {976 let Latency = 8;977 let NumMicroOps = 2;978 let ReleaseAtCycles = [1,1];979}980def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;981 982def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {983 let Latency = 8;984 let NumMicroOps = 2;985 let ReleaseAtCycles = [1,1];986}987def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;988 989def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {990 let Latency = 6;991 let NumMicroOps = 2;992 let ReleaseAtCycles = [1,1];993}994def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",995 "(V?)PMOV(SX|ZX)BQrm",996 "(V?)PMOV(SX|ZX)BWrm",997 "(V?)PMOV(SX|ZX)DQrm",998 "(V?)PMOV(SX|ZX)WDrm",999 "(V?)PMOV(SX|ZX)WQrm")>;1000 1001def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {1002 let Latency = 8;1003 let NumMicroOps = 2;1004 let ReleaseAtCycles = [1,1];1005}1006def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,1007 VPMOVSXBQYrm,1008 VPMOVSXWQYrm)>;1009 1010def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {1011 let Latency = 6;1012 let NumMicroOps = 2;1013 let ReleaseAtCycles = [1,1];1014}1015def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>;1016def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;1017 1018def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {1019 let Latency = 6;1020 let NumMicroOps = 2;1021 let ReleaseAtCycles = [1,1];1022}1023def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",1024 "MOVBE(16|32|64)rm")>;1025 1026def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {1027 let Latency = 7;1028 let NumMicroOps = 2;1029 let ReleaseAtCycles = [1,1];1030}1031def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rmi,1032 VINSERTI128rmi,1033 VPBLENDDrmi)>;1034 1035def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {1036 let Latency = 8;1037 let NumMicroOps = 2;1038 let ReleaseAtCycles = [1,1];1039}1040def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;1041 1042def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {1043 let Latency = 6;1044 let NumMicroOps = 2;1045 let ReleaseAtCycles = [1,1];1046}1047def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;1048def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;1049 1050def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {1051 let Latency = 2;1052 let NumMicroOps = 3;1053 let ReleaseAtCycles = [1,1,1];1054}1055def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;1056 1057def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {1058 let Latency = 2;1059 let NumMicroOps = 3;1060 let ReleaseAtCycles = [1,1,1];1061}1062def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;1063 1064def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {1065 let Latency = 2;1066 let NumMicroOps = 3;1067 let ReleaseAtCycles = [1,1,1];1068}1069def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;1070 1071def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {1072 let Latency = 2;1073 let NumMicroOps = 3;1074 let ReleaseAtCycles = [1,1,1];1075}1076def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,1077 STOSB, STOSL, STOSQ, STOSW)>;1078def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;1079 1080def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {1081 let Latency = 7;1082 let NumMicroOps = 4;1083 let ReleaseAtCycles = [1,1,1,1];1084}1085def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",1086 "SHL(8|16|32|64)m(1|i)",1087 "SHR(8|16|32|64)m(1|i)")>;1088 1089def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {1090 let Latency = 7;1091 let NumMicroOps = 4;1092 let ReleaseAtCycles = [1,1,1,1];1093}1094def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",1095 "PUSH(16|32|64)rmm")>;1096 1097def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {1098 let Latency = 2;1099 let NumMicroOps = 2;1100 let ReleaseAtCycles = [2];1101}1102def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;1103 1104def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {1105 let Latency = 2;1106 let NumMicroOps = 2;1107 let ReleaseAtCycles = [2];1108}1109def: InstRW<[HWWriteResGroup30], (instrs LFENCE,1110 WAIT,1111 XGETBV)>;1112 1113def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {1114 let Latency = 2;1115 let NumMicroOps = 2;1116 let ReleaseAtCycles = [1,1];1117}1118def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;1119 1120def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {1121 let Latency = 2;1122 let NumMicroOps = 2;1123 let ReleaseAtCycles = [1,1];1124}1125def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;1126 1127def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {1128 let Latency = 2;1129 let NumMicroOps = 2;1130 let ReleaseAtCycles = [1,1];1131}1132def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;1133 1134def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {1135 let Latency = 7;1136 let NumMicroOps = 3;1137 let ReleaseAtCycles = [2,1];1138}1139def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm,1140 MMX_PACKSSWBrm,1141 MMX_PACKUSWBrm)>;1142 1143def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {1144 let Latency = 7;1145 let NumMicroOps = 3;1146 let ReleaseAtCycles = [1,2];1147}1148def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,1149 SCASB, SCASL, SCASQ, SCASW)>;1150 1151def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {1152 let Latency = 7;1153 let NumMicroOps = 3;1154 let ReleaseAtCycles = [1,1,1];1155}1156def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;1157 1158def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {1159 let Latency = 7;1160 let NumMicroOps = 3;1161 let ReleaseAtCycles = [1,1,1];1162}1163def: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>;1164 1165def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {1166 let Latency = 3;1167 let NumMicroOps = 4;1168 let ReleaseAtCycles = [1,1,1,1];1169}1170def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;1171 1172def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {1173 let Latency = 3;1174 let NumMicroOps = 4;1175 let ReleaseAtCycles = [1,1,1,1];1176}1177def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;1178 1179def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {1180 let Latency = 8;1181 let NumMicroOps = 5;1182 let ReleaseAtCycles = [1,1,1,2];1183}1184def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",1185 "ROR(8|16|32|64)m(1|i)")>;1186 1187def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {1188 let Latency = 2;1189 let NumMicroOps = 2;1190 let ReleaseAtCycles = [2];1191}1192def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,1193 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;1194 1195def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {1196 let Latency = 8;1197 let NumMicroOps = 5;1198 let ReleaseAtCycles = [1,1,1,2];1199}1200def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;1201 1202def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {1203 let Latency = 8;1204 let NumMicroOps = 5;1205 let ReleaseAtCycles = [1,1,1,1,1];1206}1207def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;1208def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;1209 1210def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {1211 let Latency = 3;1212 let NumMicroOps = 1;1213 let ReleaseAtCycles = [1];1214}1215def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr")>;1216 1217def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {1218 let Latency = 3;1219 let NumMicroOps = 1;1220 let ReleaseAtCycles = [1];1221}1222def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;1223 1224def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {1225 let Latency = 10;1226 let NumMicroOps = 2;1227 let ReleaseAtCycles = [1,1];1228}1229def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",1230 "ILD_F(16|32|64)m")>;1231 1232def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {1233 let Latency = 9;1234 let NumMicroOps = 2;1235 let ReleaseAtCycles = [1,1];1236}1237def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,1238 VPMOVSXDQYrm,1239 VPMOVSXWDYrm,1240 VPMOVZXWDYrm)>;1241 1242def HWWriteResGroup57 : SchedWriteRes<[HWPort5]> {1243 let Latency = 3;1244 let NumMicroOps = 2;1245 let ReleaseAtCycles = [2];1246}1247def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr,1248 MMX_PACKSSWBrr,1249 MMX_PACKUSWBrr)>;1250 1251def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {1252 let Latency = 3;1253 let NumMicroOps = 3;1254 let ReleaseAtCycles = [1,2];1255}1256def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;1257 1258def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {1259 let Latency = 2;1260 let NumMicroOps = 3;1261 let ReleaseAtCycles = [1,2];1262}1263def: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,1264 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;1265 1266def HWWriteResGroup60 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {1267 let Latency = 5;1268 let NumMicroOps = 8;1269 let ReleaseAtCycles = [2,4,2];1270}1271def: InstRW<[HWWriteResGroup60], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;1272 1273def HWWriteResGroup60b : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {1274 let Latency = 6;1275 let NumMicroOps = 8;1276 let ReleaseAtCycles = [2,4,2];1277}1278def: InstRW<[HWWriteResGroup60b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;1279 1280def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {1281 let Latency = 4;1282 let NumMicroOps = 3;1283 let ReleaseAtCycles = [1,1,1];1284}1285def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;1286 1287def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {1288 let Latency = 4;1289 let NumMicroOps = 3;1290 let ReleaseAtCycles = [1,1,1];1291}1292def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",1293 "IST_F(16|32)m")>;1294 1295def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {1296 let Latency = 9;1297 let NumMicroOps = 5;1298 let ReleaseAtCycles = [1,1,1,2];1299}1300def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",1301 "RCR(8|16|32|64)m(1|i)")>;1302 1303def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {1304 let Latency = 9;1305 let NumMicroOps = 6;1306 let ReleaseAtCycles = [1,1,1,3];1307}1308def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;1309 1310def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {1311 let Latency = 9;1312 let NumMicroOps = 6;1313 let ReleaseAtCycles = [1,1,1,2,1];1314}1315def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",1316 "ROR(8|16|32|64)mCL",1317 "SAR(8|16|32|64)mCL",1318 "SHL(8|16|32|64)mCL",1319 "SHR(8|16|32|64)mCL")>;1320def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;1321 1322def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {1323 let Latency = 4;1324 let NumMicroOps = 2;1325 let ReleaseAtCycles = [1,1];1326}1327def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;1328 1329def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {1330 let Latency = 4;1331 let NumMicroOps = 2;1332 let ReleaseAtCycles = [1,1];1333}1334def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr,1335 MMX_CVTTPS2PIrr)>;1336 1337def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {1338 let Latency = 11;1339 let NumMicroOps = 3;1340 let ReleaseAtCycles = [2,1];1341}1342def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;1343 1344def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {1345 let Latency = 9;1346 let NumMicroOps = 3;1347 let ReleaseAtCycles = [1,1,1];1348}1349def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;1350 1351def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {1352 let Latency = 4;1353 let NumMicroOps = 4;1354 let ReleaseAtCycles = [4];1355}1356def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;1357 1358def HWWriteResGroup82 : SchedWriteRes<[]> {1359 let Latency = 0;1360 let NumMicroOps = 4;1361 let ReleaseAtCycles = [];1362}1363def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;1364 1365def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {1366 let Latency = 4;1367 let NumMicroOps = 4;1368 let ReleaseAtCycles = [1,1,2];1369}1370def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;1371 1372def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {1373 let Latency = 9;1374 let NumMicroOps = 5;1375 let ReleaseAtCycles = [1,2,1,1];1376}1377def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",1378 "LSL(16|32|64)rm")>;1379 1380def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {1381 let Latency = 5;1382 let NumMicroOps = 6;1383 let ReleaseAtCycles = [1,1,4];1384}1385def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;1386 1387def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {1388 let Latency = 5;1389 let NumMicroOps = 1;1390 let ReleaseAtCycles = [1];1391}1392def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;1393 1394def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {1395 let Latency = 11;1396 let NumMicroOps = 2;1397 let ReleaseAtCycles = [1,1];1398}1399def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;1400 1401def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {1402 let Latency = 12;1403 let NumMicroOps = 2;1404 let ReleaseAtCycles = [1,1];1405}1406def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;1407def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;1408 1409def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {1410 let Latency = 5;1411 let NumMicroOps = 3;1412 let ReleaseAtCycles = [1,2];1413}1414def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;1415 1416def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {1417 let Latency = 5;1418 let NumMicroOps = 3;1419 let ReleaseAtCycles = [1,1,1];1420}1421def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;1422 1423def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {1424 let Latency = 5;1425 let NumMicroOps = 5;1426 let ReleaseAtCycles = [1,4];1427}1428def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;1429 1430def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {1431 let Latency = 5;1432 let NumMicroOps = 5;1433 let ReleaseAtCycles = [1,4];1434}1435def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;1436 1437def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {1438 let Latency = 13;1439 let NumMicroOps = 3;1440 let ReleaseAtCycles = [2,1];1441}1442def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;1443 1444def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {1445 let Latency = 6;1446 let NumMicroOps = 4;1447 let ReleaseAtCycles = [1,1,1,1];1448}1449def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;1450 1451def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {1452 let Latency = 6;1453 let NumMicroOps = 6;1454 let ReleaseAtCycles = [1,5];1455}1456def: InstRW<[HWWriteResGroup108], (instrs STD)>;1457 1458def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {1459 let Latency = 7;1460 let NumMicroOps = 7;1461 let ReleaseAtCycles = [2,2,1,2];1462}1463def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;1464 1465def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {1466 let Latency = 15;1467 let NumMicroOps = 3;1468 let ReleaseAtCycles = [1,1,1];1469}1470def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;1471 1472def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {1473 let Latency = 16;1474 let NumMicroOps = 10;1475 let ReleaseAtCycles = [1,1,1,4,1,2];1476}1477def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;1478 1479def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {1480 let Latency = 11;1481 let NumMicroOps = 7;1482 let ReleaseAtCycles = [2,2,3];1483}1484def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",1485 "RCR(16|32|64)rCL")>;1486 1487def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {1488 let Latency = 11;1489 let NumMicroOps = 9;1490 let ReleaseAtCycles = [1,4,1,3];1491}1492def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;1493 1494def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {1495 let Latency = 11;1496 let NumMicroOps = 11;1497 let ReleaseAtCycles = [2,9];1498}1499def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;1500 1501def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {1502 let Latency = 17;1503 let NumMicroOps = 14;1504 let ReleaseAtCycles = [1,1,1,4,2,5];1505}1506def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;1507 1508def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {1509 let Latency = 19;1510 let NumMicroOps = 11;1511 let ReleaseAtCycles = [2,1,1,3,1,3];1512}1513def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;1514 1515def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {1516 let Latency = 14;1517 let NumMicroOps = 10;1518 let ReleaseAtCycles = [2,3,1,4];1519}1520def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;1521 1522def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {1523 let Latency = 19;1524 let NumMicroOps = 15;1525 let ReleaseAtCycles = [1,14];1526}1527def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;1528 1529def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {1530 let Latency = 21;1531 let NumMicroOps = 8;1532 let ReleaseAtCycles = [1,1,1,1,1,1,2];1533}1534def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;1535 1536def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {1537 let Latency = 8;1538 let NumMicroOps = 20;1539 let ReleaseAtCycles = [1,1];1540}1541def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;1542 1543def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {1544 let Latency = 22;1545 let NumMicroOps = 19;1546 let ReleaseAtCycles = [2,1,4,1,1,4,6];1547}1548def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;1549 1550def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {1551 let Latency = 17;1552 let NumMicroOps = 15;1553 let ReleaseAtCycles = [2,1,2,4,2,4];1554}1555def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;1556 1557def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {1558 let Latency = 18;1559 let NumMicroOps = 8;1560 let ReleaseAtCycles = [1,1,1,5];1561}1562def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;1563 1564def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {1565 let Latency = 23;1566 let NumMicroOps = 19;1567 let ReleaseAtCycles = [3,1,15];1568}1569def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;1570 1571def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {1572 let Latency = 20;1573 let NumMicroOps = 1;1574 let ReleaseAtCycles = [1];1575}1576def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;1577 1578def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {1579 let Latency = 27;1580 let NumMicroOps = 2;1581 let ReleaseAtCycles = [1,1];1582}1583def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;1584 1585def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {1586 let Latency = 20;1587 let NumMicroOps = 10;1588 let ReleaseAtCycles = [1,2,7];1589}1590def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;1591 1592def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {1593 let Latency = 30;1594 let NumMicroOps = 3;1595 let ReleaseAtCycles = [1,1,1];1596}1597def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;1598 1599def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {1600 let Latency = 24;1601 let NumMicroOps = 1;1602 let ReleaseAtCycles = [1];1603}1604def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;1605 1606def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {1607 let Latency = 31;1608 let NumMicroOps = 2;1609 let ReleaseAtCycles = [1,1];1610}1611def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;1612 1613def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {1614 let Latency = 30;1615 let NumMicroOps = 27;1616 let ReleaseAtCycles = [1,5,1,1,19];1617}1618def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;1619 1620def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {1621 let Latency = 31;1622 let NumMicroOps = 28;1623 let ReleaseAtCycles = [1,6,1,1,19];1624}1625def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;1626def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;1627 1628def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {1629 let Latency = 34;1630 let NumMicroOps = 3;1631 let ReleaseAtCycles = [1,1,1];1632}1633def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;1634 1635def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {1636 let Latency = 35;1637 let NumMicroOps = 23;1638 let ReleaseAtCycles = [1,5,3,4,10];1639}1640def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",1641 "IN(8|16|32)rr")>;1642 1643def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {1644 let Latency = 36;1645 let NumMicroOps = 23;1646 let ReleaseAtCycles = [1,5,2,1,4,10];1647}1648def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",1649 "OUT(8|16|32)rr")>;1650 1651def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {1652 let Latency = 41;1653 let NumMicroOps = 18;1654 let ReleaseAtCycles = [1,1,2,3,1,1,1,8];1655}1656def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;1657 1658def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {1659 let Latency = 42;1660 let NumMicroOps = 22;1661 let ReleaseAtCycles = [2,20];1662}1663def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;1664 1665def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {1666 let Latency = 61;1667 let NumMicroOps = 64;1668 let ReleaseAtCycles = [2,2,8,1,10,2,39];1669}1670def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;1671 1672def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {1673 let Latency = 64;1674 let NumMicroOps = 88;1675 let ReleaseAtCycles = [4,4,31,1,2,1,45];1676}1677def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;1678 1679def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {1680 let Latency = 64;1681 let NumMicroOps = 90;1682 let ReleaseAtCycles = [4,2,33,1,2,1,47];1683}1684def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;1685 1686def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {1687 let Latency = 75;1688 let NumMicroOps = 15;1689 let ReleaseAtCycles = [6,3,6];1690}1691def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;1692 1693def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {1694 let Latency = 115;1695 let NumMicroOps = 100;1696 let ReleaseAtCycles = [9,9,11,8,1,11,21,30];1697}1698def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;1699 1700def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1701 let Latency = 14;1702 let NumMicroOps = 12;1703 let ReleaseAtCycles = [2,2,2,1,3,2];1704}1705def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>;1706 1707def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1708 let Latency = 17;1709 let NumMicroOps = 20;1710 let ReleaseAtCycles = [3,3,4,1,5,4];1711}1712def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>;1713 1714def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1715 let Latency = 16;1716 let NumMicroOps = 20;1717 let ReleaseAtCycles = [3,3,4,1,5,4];1718}1719def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>;1720 1721def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1722 let Latency = 22;1723 let NumMicroOps = 34;1724 let ReleaseAtCycles = [5,3,8,1,9,8];1725}1726def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;1727 1728def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1729 let Latency = 15;1730 let NumMicroOps = 14;1731 let ReleaseAtCycles = [3,3,2,1,3,2];1732}1733def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>;1734 1735def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1736 let Latency = 17;1737 let NumMicroOps = 22;1738 let ReleaseAtCycles = [5,3,4,1,5,4];1739}1740def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,1741 VGATHERQPSYrm, VPGATHERQDYrm)>;1742 1743def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {1744 let Latency = 16;1745 let NumMicroOps = 15;1746 let ReleaseAtCycles = [3,3,2,1,4,2];1747}1748def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>;1749 1750def: InstRW<[WriteZero], (instrs CLC)>;1751 1752 1753// Instruction variants handled by the renamer. These might not need execution1754// ports in certain conditions.1755// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",1756// section "Haswell and Broadwell Pipeline" > "Register allocation and1757// renaming".1758// These can be investigated with llvm-exegesis, e.g.1759// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-1760// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-1761 1762def HWWriteZeroLatency : SchedWriteRes<[]> {1763 let Latency = 0;1764}1765 1766def HWWriteZeroIdiom : SchedWriteVariant<[1767 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1768 SchedVar<NoSchedPred, [WriteALU]>1769]>;1770def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,1771 XOR32rr, XOR64rr)>;1772 1773def HWWriteFZeroIdiom : SchedWriteVariant<[1774 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1775 SchedVar<NoSchedPred, [WriteFLogic]>1776]>;1777def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,1778 VXORPDrr)>;1779 1780def HWWriteFZeroIdiomY : SchedWriteVariant<[1781 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1782 SchedVar<NoSchedPred, [WriteFLogicY]>1783]>;1784def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;1785 1786def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[1787 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1788 SchedVar<NoSchedPred, [WriteVecLogicX]>1789]>;1790def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;1791 1792def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[1793 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1794 SchedVar<NoSchedPred, [WriteVecLogicY]>1795]>;1796def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;1797 1798def HWWriteVZeroIdiomALUX : SchedWriteVariant<[1799 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1800 SchedVar<NoSchedPred, [WriteVecALUX]>1801]>;1802def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,1803 PSUBDrr, VPSUBDrr,1804 PSUBQrr, VPSUBQrr,1805 PSUBWrr, VPSUBWrr,1806 PCMPGTBrr, VPCMPGTBrr,1807 PCMPGTDrr, VPCMPGTDrr,1808 PCMPGTWrr, VPCMPGTWrr)>;1809 1810def HWWriteVZeroIdiomALUY : SchedWriteVariant<[1811 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1812 SchedVar<NoSchedPred, [WriteVecALUY]>1813]>;1814def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,1815 VPSUBDYrr,1816 VPSUBQYrr,1817 VPSUBWYrr,1818 VPCMPGTBYrr,1819 VPCMPGTDYrr,1820 VPCMPGTWYrr)>;1821 1822def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {1823 let Latency = 5;1824 let NumMicroOps = 1;1825 let ReleaseAtCycles = [1];1826}1827 1828def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[1829 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,1830 SchedVar<NoSchedPred, [HWWritePCMPGTQ]>1831]>;1832def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,1833 VPCMPGTQYrr)>;1834 1835 1836// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require1837// a single uop. It does not apply to the GR8 encoding. And only applies to the1838// 8-bit immediate since using larger immediate for 0 would be silly.1839// Unfortunately, this optimization does not apply to the AX/EAX/RAX short1840// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since1841// we schedule before that point.1842// TODO: Should we disable using the short encodings on these CPUs?1843def HWFastADC0 : MCSchedPredicate<1844 CheckAll<[1845 CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0.1846 CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX1847 CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX1848 CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX1849 ]>1850>;1851 1852def HWWriteADC0 : SchedWriteRes<[HWPort06]> {1853 let Latency = 1;1854 let NumMicroOps = 1;1855 let ReleaseAtCycles = [1];1856}1857 1858def HWWriteADC : SchedWriteVariant<[1859 SchedVar<HWFastADC0, [HWWriteADC0]>,1860 SchedVar<NoSchedPred, [WriteADC]>1861]>;1862 1863def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,1864 SBB16ri8, SBB32ri8, SBB64ri8)>;1865 1866// CMOVs that use both Z and C flag require an extra uop.1867def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {1868 let Latency = 3;1869 let ReleaseAtCycles = [1,2];1870 let NumMicroOps = 3;1871}1872 1873def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {1874 let Latency = 8;1875 let ReleaseAtCycles = [1,1,2];1876 let NumMicroOps = 4;1877}1878 1879def HWCMOVA_CMOVBErr : SchedWriteVariant<[1880 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>,1881 SchedVar<NoSchedPred, [WriteCMOV]>1882]>;1883 1884def HWCMOVA_CMOVBErm : SchedWriteVariant<[1885 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,1886 SchedVar<NoSchedPred, [WriteCMOV.Folded]>1887]>;1888 1889def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;1890def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;1891 1892// SETCCs that use both Z and C flag require an extra uop.1893def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {1894 let Latency = 2;1895 let ReleaseAtCycles = [1,1];1896 let NumMicroOps = 2;1897}1898 1899def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {1900 let Latency = 3;1901 let ReleaseAtCycles = [1,1,1,1];1902 let NumMicroOps = 4;1903}1904 1905def HWSETA_SETBErr : SchedWriteVariant<[1906 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,1907 SchedVar<NoSchedPred, [WriteSETCC]>1908]>;1909 1910def HWSETA_SETBErm : SchedWriteVariant<[1911 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>,1912 SchedVar<NoSchedPred, [WriteSETCCStore]>1913]>;1914 1915def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>;1916def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>;1917 1918///////////////////////////////////////////////////////////////////////////////1919// Dependency breaking instructions.1920///////////////////////////////////////////////////////////////////////////////1921 1922def : IsZeroIdiomFunction<[1923 // GPR Zero-idioms.1924 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,1925 1926 // SSE Zero-idioms.1927 DepBreakingClass<[1928 // fp variants.1929 XORPSrr, XORPDrr,1930 1931 // int variants.1932 PXORrr,1933 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,1934 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr1935 ], ZeroIdiomPredicate>,1936 1937 // AVX Zero-idioms.1938 DepBreakingClass<[1939 // xmm fp variants.1940 VXORPSrr, VXORPDrr,1941 1942 // xmm int variants.1943 VPXORrr,1944 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,1945 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,1946 1947 // ymm variants.1948 VXORPSYrr, VXORPDYrr, VPXORYrr,1949 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,1950 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr1951 ], ZeroIdiomPredicate>,1952]>;1953 1954} // SchedModel1955