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1//=----- X86SchedLunarlakeP.td - X86 LunarlakeP Scheduling *- tablegen -----*=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for LunarlakeP to support instruction10// scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13def LunarlakePModel : SchedMachineModel {14 // LunarlakeP can allocate 8 uops per cycle.15 // Max micro-ops that may be scheduled per cycle.16 // Based on Allocator Width17 let IssueWidth = 8; 18 // Max micro-ops that can be buffered. 19 // Based on size of ROB20 let MicroOpBufferSize = 792;21 // INT LOAD takes 4 cycles22 let LoadLatency = 4;23 let MispredictPenalty = 14;24 // Latency for microcoded instructions or instructions without latency info.25 int MaxLatency = 100;26 // Based on the LSD (loop-stream detector) queue size (ST).27 // LSD is 200 uops per logical processor in single threaded mode28 // For SMT 100 uops/thread, LionCove removed SMT in HW.29 let LoopMicroOpBufferSize = 200;30 // This flag is set to allow the scheduler to assign a default model to31 // unrecognized opcodes.32 let CompleteModel = 0;33}34 35let SchedModel = LunarlakePModel in {36 37// LunarlakeP can issue micro-ops to 18 different ports in one cycle.38// Lion Cove architectural spec uses port naming that is not sequential39// for better comprehension we opt for sequential naming since this ports40// serve logical information for schedule only.41// 6 INT ALU Ports {P0 to P5}42def LNLPPort00 : ProcResource<1>;43def LNLPPort01 : ProcResource<1>;44def LNLPPort02 : ProcResource<1>;45def LNLPPort03 : ProcResource<1>;46def LNLPPort04 : ProcResource<1>;47def LNLPPort05 : ProcResource<1>;48// 4 VEC ALU Ports {V0 to V3}49def LNLPVPort00 : ProcResource<1>;50def LNLPVPort01 : ProcResource<1>;51def LNLPVPort02 : ProcResource<1>;52def LNLPVPort03 : ProcResource<1>;53// 2 Store Data Ports {P10 to P11}54def LNLPPort10 : ProcResource<1>;55def LNLPPort11 : ProcResource<1>;56// 6 MEM Ports 6 AGU shared with 3 LD, 3 ST57// AGU LD {P20 to P22}58def LNLPPort20 : ProcResource<1>;59def LNLPPort21 : ProcResource<1>;60def LNLPPort22 : ProcResource<1>;61// AGU ST {P25 to P27}62def LNLPPort25 : ProcResource<1>;63def LNLPPort26 : ProcResource<1>;64def LNLPPort27 : ProcResource<1>;65 66// Workaround to represent invalid ports. WriteRes shouldn't use this resource.67def LNLPPortInvalid :ProcResource<1>;68 69// Many micro-ops are capable of issuing on multiple ports.70def LNLPVPort00_01 : ProcResGroup<[LNLPVPort00, LNLPVPort01]>;71def LNLPVPort02_03 : ProcResGroup<[LNLPVPort02, LNLPVPort03]>;72def LNLPPort00_02_04 : ProcResGroup<[LNLPPort00, LNLPPort02, LNLPPort04]>;73def LNLPPort01_03_05 : ProcResGroup<[LNLPPort01, LNLPPort03, LNLPPort05]>;74def LNLPPort20_21_22 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22]>;75def LNLPPort25_26_27 : ProcResGroup<[LNLPPort25, LNLPPort26, LNLPPort27]>;76 77// INT EU has 112 reservation stations.78def LNLPPort00_01_02_03_04_05 : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02,79 LNLPPort03, LNLPPort04, LNLPPort05]>{ 80 let BufferSize = 110; // Reduced from 128 in GLC81}82 83// VEC EU has 180 reservation stations.84def LNLPVPort00_01_02_03 : ProcResGroup<[LNLPVPort00, LNLPVPort01, LNLPVPort02,85 LNLPVPort03]>{86 let BufferSize = 180; // EU for INT and VEC are seperated 87 // VEC QUEUE SIZE = 60 + VEC EU RS (60+60)88}89// STD has 48 reservation stations.90def LNLPPort10_11 : ProcResGroup<[LNLPPort10, LNLPPort11]> {91 let BufferSize = 48;92}93 94// MEM has 72 reservation stations.95def LNLPPort20_21_22_25_26_27 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22,96 LNLPPort25, LNLPPort26, LNLPPort27]> {97 let BufferSize = 72;98}99 100def LNLPPortAny : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02, LNLPPort03,101 LNLPPort04, LNLPPort05, LNLPVPort00, LNLPVPort01,102 LNLPVPort02, LNLPVPort03, LNLPPort10, LNLPPort11,103 LNLPPort20, LNLPPort21, LNLPPort22, LNLPPort25,104 LNLPPort26, LNLPPort27]>;105 106// Integer loads are 4 cycles, so ReadAfterLd registers needn't be available107// until 4 cycles after the memory operand.108def : ReadAdvance<ReadAfterLd, 4>;109 110// TODO: 6 Cycle latency for Vec load comes from ADL111// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available112// until 6 cycles after the memory operand.113def : ReadAdvance<ReadAfterVecLd, 6>;114def : ReadAdvance<ReadAfterVecXLd, 6>;115def : ReadAdvance<ReadAfterVecYLd, 6>;116 117def : ReadAdvance<ReadInt2Fpu, 0>;118 119// Many SchedWrites are defined in pairs with and without a folded load.120// Instructions with folded loads are usually micro-fused, so they only appear121// as two micro-ops when queued in the reservation station.122// This multiclass defines the resource usage for variants with and without123// folded loads.124multiclass LNLPWriteResPair<X86FoldableSchedWrite SchedRW,125 list<ProcResourceKind> ExePorts,126 int Lat, list<int> Res = [1], int UOps = 1,127 int LoadLat = 4, int LoadUOps = 1> {128 // Register variant is using a single cycle on ExePort.129 def : WriteRes<SchedRW, ExePorts> {130 let Latency = Lat;131 let ReleaseAtCycles = Res;132 let NumMicroOps = UOps;133 }134 135 // Memory variant also uses a cycle on port 20/21/22 and adds LoadLat cycles to136 // the latency (default = 4).137 def : WriteRes<SchedRW.Folded, !listconcat([LNLPPort20_21_22], ExePorts)> {138 let Latency = !add(Lat, LoadLat);139 let ReleaseAtCycles = !listconcat([1], Res);140 let NumMicroOps = !add(UOps, LoadUOps);141 }142}143 144defm : X86WriteResUnsupported<WriteBEXTRLd>;145 146//===----------------------------------------------------------------------===//147// The following definitons are infered by smg.148//===----------------------------------------------------------------------===//149 150def : WriteRes<WriteADC, [LNLPPort00_02_04]>;151defm : X86WriteRes<WriteADCLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04], 11, [1, 1], 2>;152def : WriteRes<WriteAESDecEnc, [LNLPVPort00_01]> {153 let ReleaseAtCycles = [4];154 let Latency = 3;155}156defm : X86WriteRes<WriteAESDecEncLd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [4, 7], 2>;157defm : X86WriteResPairUnsupported<WriteAESIMC>;158defm : X86WriteResPairUnsupported<WriteAESKeyGen>;159def : WriteRes<WriteALU, [LNLPPort01_03_05]>;160def : WriteRes<WriteALULd, [LNLPPort01_03_05, LNLPPort20_21_22]> {161 let Latency = 11;162}163defm : X86WriteRes<WriteBEXTR, [LNLPPort01_03_05], 6, [2], 2>;164def : WriteRes<WriteBLS, [LNLPPort01_03_05]>;165defm : X86WriteRes<WriteBLSLd, [LNLPPort01_03_05, LNLPPort20_21_22], 5, [1, 4], 2>;166defm : LNLPWriteResPair<WriteBSF, [LNLPPort01_03_05], 3, [1]>;167defm : LNLPWriteResPair<WriteBSR, [LNLPPort01_03_05], 3, [1]>;168def : WriteRes<WriteBSWAP32, [LNLPPort01_03_05]>;169defm : X86WriteRes<WriteBSWAP64, [LNLPPort01_03_05, LNLPPort01_03_05], 2, [1, 1], 2>;170defm : LNLPWriteResPair<WriteBZHI, [LNLPPort01_03_05], 3, [1]>;171def : WriteRes<WriteBitTestSet, [LNLPPort01_03_05]>;172def : WriteRes<WriteBitTestSetImmLd, [LNLPPort01_03_05]> {173 let Latency = 11;174}175defm : X86WriteRes<WriteBitTestSetRegLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort00_02_04, LNLPPort01_03_05], 17, [3, 2, 1, 2], 8>;176def : WriteRes<WriteBitTest, [LNLPPort01_03_05]>;177defm : X86WriteRes<WriteBitTestImmLd, [LNLPPort01_03_05, LNLPPort20_21_22], 6, [1, 1], 2>;178defm : X86WriteRes<WriteBitTestRegLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22], 11, [4, 2, 1, 2, 1], 10>;179 180def : WriteRes<WriteBlend, [LNLPVPort00_01_02_03]>;181defm : X86WriteRes<WriteBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;182def : WriteRes<WriteBlendY, [LNLPVPort00_01_02_03]>;183defm : X86WriteRes<WriteBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;184 185defm : LNLPWriteResPair<WriteCLMul, [LNLPVPort02_03], 3, [1], 1, 7>;186def : WriteRes<WriteCMOV, [LNLPPort00_01_02_03_04_05]>;187def : WriteRes<WriteCMOVLd, [LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {188 let ReleaseAtCycles = [1, 4];189 let Latency = 5;190}191defm : X86WriteRes<WriteCMPXCHG, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04], 3, [3, 2], 5>;192defm : X86WriteRes<WriteCMPXCHGRMW, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort20_21_22], 12, [1, 2, 1, 1, 1], 6>;193 194def : WriteRes<WriteCRC32, [LNLPPort01_03_05]> {195 let ReleaseAtCycles = [3];196 let Latency = 3;197}198def : WriteRes<WriteCRC32Ld, [LNLPPort01_03_05, LNLPPort20_21_22]> {199 let ReleaseAtCycles = [3, 4];200 let Latency = 7;201}202 203defm : X86WriteRes<WriteCvtI2PD, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;204defm : X86WriteRes<WriteCvtI2PDLd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [1,1], 2>; 205defm : X86WriteRes<WriteCvtI2PDY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;206def : WriteRes<WriteCvtI2PDYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {207 let ReleaseAtCycles = [4, 7];208 let Latency = 11;209}210defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;211def : WriteRes<WriteCvtI2PS, [LNLPVPort00_01]> {212 let ReleaseAtCycles = [4];213 let Latency = 4;214}215def : WriteRes<WriteCvtI2PSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {216 let ReleaseAtCycles = [4, 6];217 let Latency = 10;218}219defm : LNLPWriteResPair<WriteCvtI2PSY, [LNLPVPort00_01], 4, [1], 1, 8>;220defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;221defm : X86WriteRes<WriteCvtI2SD, [LNLPPort01_03_05, LNLPVPort00_01], 8, [4, 4], 2>;222def : WriteRes<WriteCvtI2SDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {223 let ReleaseAtCycles = [4, 6];224 let Latency = 10;225}226defm : X86WriteRes<WriteCvtI2SS, [LNLPPort01_03_05, LNLPVPort00_01], 8, [4, 4], 2>;227def : WriteRes<WriteCvtI2SSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {228 let ReleaseAtCycles = [4, 6];229 let Latency = 10;230}231 232defm : LNLPWriteResPair<WriteCvtPD2I, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2, 7>;233defm : LNLPWriteResPair<WriteCvtPD2IY, [LNLPVPort00_01, LNLPVPort02_03], 7, [1, 1], 2, 8>;234defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;235defm : LNLPWriteResPair<WriteCvtPD2PS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2, 7>;236defm : LNLPWriteResPair<WriteCvtPD2PSY, [LNLPVPort00_01, LNLPVPort02_03], 7, [1, 1], 2, 8>;237defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;238defm : X86WriteRes<WriteCvtPH2PS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;239defm : X86WriteRes<WriteCvtPH2PSLd, [LNLPVPort00_01, LNLPPort20_21_22], 12, [1, 1], 2>;240defm : X86WriteRes<WriteCvtPH2PSY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;241def : WriteRes<WriteCvtPH2PSYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {242 let ReleaseAtCycles = [4, 7];243 let Latency = 11;244}245defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;246def : WriteRes<WriteCvtPS2I, [LNLPVPort00_01]> {247 let ReleaseAtCycles = [4];248 let Latency = 4;249}250defm : X86WriteRes<WriteCvtPS2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 10, [4, 6], 2>;251def : WriteRes<WriteCvtPS2IY, [LNLPVPort00_01]> {252 let ReleaseAtCycles = [4];253 let Latency = 4;254}255def : WriteRes<WriteCvtPS2IYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {256 let ReleaseAtCycles = [4, 7];257 let Latency = 11;258}259defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;260defm : X86WriteRes<WriteCvtPS2PD, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;261def : WriteRes<WriteCvtPS2PDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {262 let ReleaseAtCycles = [4, 6];263 let Latency = 10;264}265defm : X86WriteRes<WriteCvtPS2PDY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;266def : WriteRes<WriteCvtPS2PDYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {267 let ReleaseAtCycles = [4, 7];268 let Latency = 11;269}270defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;271defm : X86WriteRes<WriteCvtPS2PH, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;272defm : X86WriteRes<WriteCvtPS2PHSt, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 5, [4, 1, 1], 2>;273defm : X86WriteRes<WriteCvtPS2PHY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;274defm : X86WriteRes<WriteCvtPS2PHYSt, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 5, [4, 1, 1], 3>;275defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;276defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;277defm : X86WriteRes<WriteCvtSD2I, [LNLPVPort00_01], 7, [7], 2>;278defm : X86WriteRes<WriteCvtSD2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [7, 4], 3>;279defm : X86WriteRes<WriteCvtSD2SS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;280defm : X86WriteRes<WriteCvtSD2SSLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 11, [4, 1, 6], 3>;281defm : X86WriteRes<WriteCvtSS2I, [LNLPVPort00_01], 7, [7], 2>;282defm : X86WriteRes<WriteCvtSS2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [7, 4], 2>;283defm : X86WriteRes<WriteCvtSS2SD, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;284def : WriteRes<WriteCvtSS2SDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {285 let ReleaseAtCycles = [4, 6];286 let Latency = 10;287}288defm : X86WriteRes<WriteDPPD, [LNLPVPort00_01, LNLPVPort02_03], 8, [2, 1], 3>;289defm : X86WriteRes<WriteDPPDLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 13, [2, 1, 1], 4>;290//defm : X86WriteRes<WriteDPPS, [LNLPVPort00_01, LNLPVPort02_03], 99, [7, 5], 5>;291// FIXME: Incompleted schedwrite.292//defm : X86WriteResUnsupported<WriteDPPSLd>;293defm : LNLPWriteResPair<WriteDPPS, [LNLPVPort00_01, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort00_01], 11, [2, 1, 1, 1, 1], 5, 7>;294//defm : X86WriteRes<WriteDPPSY, [LNLPVPort00_01, LNLPVPort02_03], 12, [7, 5], 5>;295// FIXME: Incompleted schedwrite.296//defm : X86WriteResUnsupported<WriteDPPSYLd>;297defm : LNLPWriteResPair<WriteDPPSY, [LNLPVPort00_01, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort00_01], 12, [2, 1, 1, 1, 1], 5, 7>;298 299defm : LNLPWriteResPair<WriteDiv16, [LNLPPort00_01_02_03_04_05, LNLPPort01], 16, [1, 3], 4, 4>;300defm : LNLPWriteResPair<WriteDiv32, [LNLPPort00_01_02_03_04_05, LNLPPort01], 15, [1, 3], 4, 4>;301defm : LNLPWriteResPair<WriteDiv64, [LNLPPort01], 18, [3], 3>;302defm : X86WriteRes<WriteDiv8, [LNLPPort01], 17, [3], 3>;303defm : X86WriteRes<WriteDiv8Ld, [LNLPPort01], 22, [3], 3>;304defm : X86WriteRes<WriteEMMS, [LNLPPort01, LNLPVPort00_01, LNLPVPort02_03], 10, [1, 8, 1], 10>;305def : WriteRes<WriteFAdd, [LNLPVPort02_03]> {306 let Latency = 2;307}308// FIXME: Latency309defm : X86WriteRes<WriteFAddLd, [LNLPVPort02_03, LNLPPort20_21_22], 10, [1,1], 2>; // 8310defm : LNLPWriteResPair<WriteFAdd64, [LNLPVPort02_03], 3, [1], 1, 7>;311defm : LNLPWriteResPair<WriteFAdd64X, [LNLPVPort02_03], 3, [1], 1, 7>;312defm : LNLPWriteResPair<WriteFAdd64Y, [LNLPVPort02_03], 3, [1], 1, 8>;313defm : X86WriteResPairUnsupported<WriteFAdd64Z>;314defm : LNLPWriteResPair<WriteFAddX, [LNLPVPort02_03], 3, [1], 1, 7>;315defm : LNLPWriteResPair<WriteFAddY, [LNLPVPort02_03], 3, [1], 1, 8>;316defm : X86WriteResPairUnsupported<WriteFAddZ>;317def : WriteRes<WriteFBlend, [LNLPVPort00_01_02_03]>;318defm : X86WriteRes<WriteFBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;319def : WriteRes<WriteFBlendY, [LNLPVPort00_01_02_03]>;320defm : X86WriteRes<WriteFBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;321def : WriteRes<WriteFCMOV, [LNLPVPort00_01]> {322 let Latency = 3;323}324def : WriteRes<WriteFCmp, [LNLPVPort00_01]> {325 let ReleaseAtCycles = [4];326 let Latency = 4;327}328def : WriteRes<WriteFCmpLd, [LNLPVPort00_01, LNLPPort20_21_22]> {329 let ReleaseAtCycles = [4, 6];330 let Latency = 10;331}332def : WriteRes<WriteFCmp64, [LNLPVPort00_01]> {333 let ReleaseAtCycles = [4];334 let Latency = 4;335}336def : WriteRes<WriteFCmp64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {337 let ReleaseAtCycles = [4, 6];338 let Latency = 10;339}340def : WriteRes<WriteFCmp64X, [LNLPVPort00_01]> {341 let ReleaseAtCycles = [4];342 let Latency = 4;343}344def : WriteRes<WriteFCmp64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {345 let ReleaseAtCycles = [4, 6];346 let Latency = 10;347}348def : WriteRes<WriteFCmp64Y, [LNLPVPort00_01]> {349 let ReleaseAtCycles = [4];350 let Latency = 4;351}352def : WriteRes<WriteFCmp64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {353 let ReleaseAtCycles = [4, 7];354 let Latency = 11;355}356defm : X86WriteResPairUnsupported<WriteFCmp64Z>;357def : WriteRes<WriteFCmpX, [LNLPVPort00_01]> {358 let ReleaseAtCycles = [4];359 let Latency = 4;360}361def : WriteRes<WriteFCmpXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {362 let ReleaseAtCycles = [4, 6];363 let Latency = 10;364}365def : WriteRes<WriteFCmpY, [LNLPVPort00_01]> {366 let ReleaseAtCycles = [4];367 let Latency = 4;368}369def : WriteRes<WriteFCmpYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {370 let ReleaseAtCycles = [4, 7];371 let Latency = 11;372}373defm : X86WriteResPairUnsupported<WriteFCmpZ>;374def : WriteRes<WriteFCom, [LNLPVPort00_01]>;375defm : X86WriteRes<WriteFComLd, [LNLPVPort00_01, LNLPPort20_21_22], 8, [1, 1], 2>;376def : WriteRes<WriteFComX, [LNLPVPort00_01]> {377 let ReleaseAtCycles = [3];378 let Latency = 3;379}380defm : X86WriteRes<WriteFComXLd, [LNLPVPort00_01, LNLPPort20_21_22], 9, [3, 6], 2>;381def : WriteRes<WriteFDiv, [LNLPVPort00_01]> {382 let ReleaseAtCycles = [7];383 let Latency = 7;384}385def : WriteRes<WriteFDivLd, [LNLPVPort00_01, LNLPPort20_21_22]> {386 let ReleaseAtCycles = [7, 6];387 let Latency = 13;388}389def : WriteRes<WriteFDiv64, [LNLPVPort00_01]> {390 let ReleaseAtCycles = [10];391 let Latency = 10;392}393def : WriteRes<WriteFDiv64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {394 let ReleaseAtCycles = [10, 6];395 let Latency = 16;396}397def : WriteRes<WriteFDiv64X, [LNLPVPort00_01]> {398 let ReleaseAtCycles = [10];399 let Latency = 10;400}401def : WriteRes<WriteFDiv64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {402 let ReleaseAtCycles = [10, 6];403 let Latency = 16;404}405def : WriteRes<WriteFDiv64Y, [LNLPVPort00_01]> {406 let ReleaseAtCycles = [10];407 let Latency = 10;408}409def : WriteRes<WriteFDiv64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {410 let ReleaseAtCycles = [10, 7];411 let Latency = 17;412}413defm : X86WriteResPairUnsupported<WriteFDiv64Z>;414def : WriteRes<WriteFDivX, [LNLPVPort00_01]> {415 let ReleaseAtCycles = [7];416 let Latency = 7;417}418def : WriteRes<WriteFDivXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {419 let ReleaseAtCycles = [7, 6];420 let Latency = 13;421}422def : WriteRes<WriteFDivY, [LNLPVPort00_01]> {423 let ReleaseAtCycles = [7];424 let Latency = 7;425}426def : WriteRes<WriteFDivYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {427 let ReleaseAtCycles = [7, 7];428 let Latency = 14;429}430defm : X86WriteResPairUnsupported<WriteFDivZ>;431defm : X86WriteRes<WriteFHAdd, [LNLPVPort02_03], 4, [5], 3>;432defm : X86WriteRes<WriteFHAddLd, [LNLPVPort02_03, LNLPPort20_21_22], 10, [5, 6], 4>;433defm : X86WriteRes<WriteFHAddY, [LNLPVPort02_03], 4, [5], 3>;434defm : X86WriteRes<WriteFHAddYLd, [LNLPVPort02_03, LNLPPort20_21_22], 11, [5, 7], 4>;435def : WriteRes<WriteFLD0, [LNLPVPort02_03]>;436defm : X86WriteRes<WriteFLD1, [LNLPVPort02_03], 1, [2], 2>;437defm : X86WriteRes<WriteFLDC, [LNLPVPort02_03], 1, [2], 2>;438 439def : WriteRes<WriteFLoad, [LNLPPort20_21_22]> {440 let Latency = 7;441}442def : WriteRes<WriteFLoadX, [LNLPPort20_21_22]> {443 let ReleaseAtCycles = [6];444 let Latency = 7;445}446def : WriteRes<WriteFLoadY, [LNLPPort20_21_22]> {447 let ReleaseAtCycles = [7];448 let Latency = 8;449}450def : WriteRes<WriteFLogic, [LNLPVPort00_01_02_03]>;451def : WriteRes<WriteFLogicLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {452 let ReleaseAtCycles = [1, 6];453 let Latency = 7;454}455def : WriteRes<WriteFLogicY, [LNLPVPort00_01_02_03]>;456def : WriteRes<WriteFLogicYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {457 let ReleaseAtCycles = [1, 7];458 let Latency = 8;459}460defm : X86WriteResPairUnsupported<WriteFLogicZ>;461def : WriteRes<WriteFMA, [LNLPVPort00_01]> {462 let ReleaseAtCycles = [4];463 let Latency = 4;464}465def : WriteRes<WriteFMALd, [LNLPVPort00_01, LNLPPort20_21_22]> {466 let ReleaseAtCycles = [4, 6];467 let Latency = 10;468}469def : WriteRes<WriteFMAX, [LNLPVPort00_01]> {470 let ReleaseAtCycles = [4];471 let Latency = 4;472}473def : WriteRes<WriteFMAXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {474 let ReleaseAtCycles = [4, 6];475 let Latency = 10;476}477def : WriteRes<WriteFMAY, [LNLPVPort00_01]> {478 let ReleaseAtCycles = [4];479 let Latency = 4;480}481def : WriteRes<WriteFMAYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {482 let ReleaseAtCycles = [4, 7];483 let Latency = 11;484}485defm : X86WriteResPairUnsupported<WriteFMAZ>;486def : WriteRes<WriteFMOVMSK, [LNLPVPort00_01]> {487 let ReleaseAtCycles = [3];488 let Latency = 3;489}490 491defm : X86WriteRes<WriteFMaskedLoad, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 1], 2>;492defm : X86WriteRes<WriteFMaskedLoadY, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 9, [1, 1], 2>;493defm : X86WriteRes<WriteFMaskedStore32, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;494defm : X86WriteRes<WriteFMaskedStore32Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;495defm : X86WriteRes<WriteFMaskedStore64, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;496defm : X86WriteRes<WriteFMaskedStore64Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;497defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;498defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;499defm : X86WriteResUnsupported<WriteFMoveZ>;500def : WriteRes<WriteFMul, [LNLPVPort00_01]> {501 let ReleaseAtCycles = [3];502 let Latency = 3;503}504def : WriteRes<WriteFMulLd, [LNLPVPort00_01, LNLPPort20_21_22]> {505 let ReleaseAtCycles = [3, 6];506 let Latency = 9;507}508def : WriteRes<WriteFMul64, [LNLPVPort00_01]> {509 let ReleaseAtCycles = [3];510 let Latency = 3;511}512def : WriteRes<WriteFMul64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {513 let ReleaseAtCycles = [3, 6];514 let Latency = 9;515}516def : WriteRes<WriteFMul64X, [LNLPVPort00_01]> {517 let ReleaseAtCycles = [3];518 let Latency = 3;519}520def : WriteRes<WriteFMul64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {521 let ReleaseAtCycles = [3, 6];522 let Latency = 9;523}524def : WriteRes<WriteFMul64Y, [LNLPVPort00_01]> {525 let ReleaseAtCycles = [3];526 let Latency = 3;527}528def : WriteRes<WriteFMul64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {529 let ReleaseAtCycles = [3, 7];530 let Latency = 10;531}532defm : X86WriteResPairUnsupported<WriteFMul64Z>;533def : WriteRes<WriteFMulX, [LNLPVPort00_01]> {534 let ReleaseAtCycles = [3];535 let Latency = 3;536}537def : WriteRes<WriteFMulXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {538 let ReleaseAtCycles = [3, 6];539 let Latency = 9;540}541def : WriteRes<WriteFMulY, [LNLPVPort00_01]> {542 let ReleaseAtCycles = [3];543 let Latency = 3;544}545def : WriteRes<WriteFMulYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {546 let ReleaseAtCycles = [3, 7];547 let Latency = 10;548}549defm : X86WriteResPairUnsupported<WriteFMulZ>;550def : WriteRes<WriteFRcp, [LNLPVPort00_01]> {551 let ReleaseAtCycles = [4];552 let Latency = 4;553}554def : WriteRes<WriteFRcpLd, [LNLPVPort00_01, LNLPPort20_21_22]> {555 let ReleaseAtCycles = [4, 6];556 let Latency = 10;557}558def : WriteRes<WriteFRcpX, [LNLPVPort00_01]> {559 let ReleaseAtCycles = [4];560 let Latency = 4;561}562def : WriteRes<WriteFRcpXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {563 let ReleaseAtCycles = [4, 6];564 let Latency = 10;565}566def : WriteRes<WriteFRcpY, [LNLPVPort00_01]> {567 let ReleaseAtCycles = [4];568 let Latency = 4;569}570def : WriteRes<WriteFRcpYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {571 let ReleaseAtCycles = [4, 7];572 let Latency = 11;573}574defm : X86WriteResPairUnsupported<WriteFRcpZ>;575defm : X86WriteRes<WriteFRnd, [LNLPVPort00_01], 8, [8], 2>;576defm : X86WriteRes<WriteFRndLd, [LNLPVPort00_01, LNLPPort20_21_22], 14, [8, 6], 3>;577defm : X86WriteRes<WriteFRndY, [LNLPVPort00_01], 8, [8], 2>;578defm : X86WriteRes<WriteFRndYLd, [LNLPVPort00_01, LNLPPort20_21_22], 15, [8, 7], 3>;579defm : X86WriteResPairUnsupported<WriteFRndZ>;580def : WriteRes<WriteFRsqrt, [LNLPVPort00_01]> {581 let ReleaseAtCycles = [4];582 let Latency = 4;583}584def : WriteRes<WriteFRsqrtLd, [LNLPVPort00_01, LNLPPort20_21_22]> {585 let ReleaseAtCycles = [4, 6];586 let Latency = 10;587}588def : WriteRes<WriteFRsqrtX, [LNLPVPort00_01]> {589 let ReleaseAtCycles = [4];590 let Latency = 4;591}592def : WriteRes<WriteFRsqrtXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {593 let ReleaseAtCycles = [4, 6];594 let Latency = 10;595}596def : WriteRes<WriteFRsqrtY, [LNLPVPort00_01]> {597 let ReleaseAtCycles = [4];598 let Latency = 4;599}600def : WriteRes<WriteFRsqrtYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {601 let ReleaseAtCycles = [4, 7];602 let Latency = 11;603}604defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;605 606defm : LNLPWriteResPair<WriteFShuffle, [LNLPVPort02_03], 1, [1], 1, 7>;607defm : LNLPWriteResPair<WriteFShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;608defm : LNLPWriteResPair<WriteFShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;609defm : X86WriteResPairUnsupported<WriteFShuffleZ>;610def : WriteRes<WriteFSign, [LNLPVPort00_01]>;611def : WriteRes<WriteFSqrt, [LNLPVPort00_01]> {612 let ReleaseAtCycles = [10];613 let Latency = 10;614}615def : WriteRes<WriteFSqrtLd, [LNLPVPort00_01, LNLPPort20_21_22]> {616 let ReleaseAtCycles = [10, 6];617 let Latency = 16;618}619def : WriteRes<WriteFSqrt64, [LNLPVPort00_01]> {620 let ReleaseAtCycles = [15];621 let Latency = 15;622}623def : WriteRes<WriteFSqrt64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {624 let ReleaseAtCycles = [15, 6];625 let Latency = 21;626}627def : WriteRes<WriteFSqrt64X, [LNLPVPort00_01]> {628 let ReleaseAtCycles = [15];629 let Latency = 15;630}631def : WriteRes<WriteFSqrt64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {632 let ReleaseAtCycles = [15, 6];633 let Latency = 21;634}635def : WriteRes<WriteFSqrt64Y, [LNLPVPort00_01]> {636 let ReleaseAtCycles = [15];637 let Latency = 15;638}639def : WriteRes<WriteFSqrt64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {640 let ReleaseAtCycles = [15, 7];641 let Latency = 22;642}643defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;644def : WriteRes<WriteFSqrt80, [LNLPPortInvalid, LNLPVPort00_01]> {645 let ReleaseAtCycles = [7, 1];646 let Latency = 21;647}648def : WriteRes<WriteFSqrtX, [LNLPVPort00_01]> {649 let ReleaseAtCycles = [10];650 let Latency = 10;651}652def : WriteRes<WriteFSqrtXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {653 let ReleaseAtCycles = [10, 6];654 let Latency = 16;655}656def : WriteRes<WriteFSqrtY, [LNLPVPort00_01]> {657 let ReleaseAtCycles = [10];658 let Latency = 10;659}660def : WriteRes<WriteFSqrtYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {661 let ReleaseAtCycles = [10, 7];662 let Latency = 17;663}664defm : X86WriteResPairUnsupported<WriteFSqrtZ>;665defm : X86WriteRes<WriteFStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;666defm : X86WriteResUnsupported<WriteFStoreNT>;667defm : X86WriteRes<WriteFStoreNTX, [LNLPPort10_11, LNLPPort25_26_27], 518, [1, 1], 2>;668defm : X86WriteRes<WriteFStoreNTY, [LNLPPort10_11, LNLPPort25_26_27], 542, [1, 1], 2>;669defm : X86WriteRes<WriteFStoreX, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;670defm : X86WriteRes<WriteFStoreY, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;671defm : LNLPWriteResPair<WriteFTest, [LNLPVPort00_01], 3, [1]>;672defm : LNLPWriteResPair<WriteFTestY, [LNLPVPort00_01], 5, [1], 1, 6>;673defm : LNLPWriteResPair<WriteFVarBlend, [LNLPVPort00_01_02_03], 1, [1], 1, 7>;674defm : LNLPWriteResPair<WriteFVarBlendY, [LNLPVPort00_01_02_03], 3, [3], 3, 7>;675defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;676defm : LNLPWriteResPair<WriteFVarShuffle, [LNLPVPort02_03], 1, [1], 1, 7>;677defm : LNLPWriteResPair<WriteFVarShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;678defm : LNLPWriteResPair<WriteFVarShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;679defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;680defm : X86WriteRes<WriteFence, [LNLPPort10_11, LNLPPort25_26_27], 2, [1, 1], 2>;681defm : LNLPWriteResPair<WriteIDiv16, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 16, [1, 3], 4, 4>;682defm : LNLPWriteResPair<WriteIDiv32, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 15, [1, 3], 4, 4>;683defm : LNLPWriteResPair<WriteIDiv64, [LNLPPort01_03_05], 18, [3], 3>;684defm : X86WriteRes<WriteIDiv8, [LNLPPort01_03_05], 17, [3], 3>;685defm : X86WriteRes<WriteIDiv8Ld, [LNLPPort01_03_05], 22, [3], 3>;686defm : LNLPWriteResPair<WriteIMul16, [LNLPPort01_03_05, LNLPPort00_02_04], 5, [2, 1], 4>;687defm : LNLPWriteResPair<WriteIMul16Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 4, [1, 1], 2>;688defm : LNLPWriteResPair<WriteIMul16Reg, [LNLPPort01_03_05], 3, [1]>;689defm : LNLPWriteResPair<WriteIMul32, [LNLPPort01_03_05, LNLPPort00_02_04], 4, [1, 1], 3>;690defm : LNLPWriteResPair<WriteIMul32Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 2, [1, 1]>;691defm : LNLPWriteResPair<WriteIMul32Reg, [LNLPPort01_03_05], 3, [1]>;692defm : LNLPWriteResPair<WriteIMul64, [LNLPPort01_03_05, LNLPPort00_02_04], 4, [1, 1], 2>;693defm : LNLPWriteResPair<WriteIMul64Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 2, [1, 1]>;694defm : LNLPWriteResPair<WriteIMul64Reg, [LNLPPort01_03_05], 3, [1]>;695defm : LNLPWriteResPair<WriteIMul8, [LNLPPort01_03_05], 3, [1]>;696def : WriteRes<WriteIMulH, []> {697 let Latency = 3; // 4698}699def : WriteRes<WriteIMulHLd, []> {700 let Latency = 3;701}702def : WriteRes<WriteJump, [LNLPPort00_02_04]>;703defm : X86WriteRes<WriteJumpLd, [LNLPPort00_02_04, LNLPPort20_21_22], 6, [1, 1], 2>;704defm : X86WriteResUnsupported<WriteLAHFSAHF>;705defm : X86WriteRes<WriteLDMXCSR, [LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort25_26_27], 7, [1, 1, 1, 1], 4>;706def : WriteRes<WriteLEA, [LNLPPort01]>;707defm : LNLPWriteResPair<WriteLZCNT, [LNLPPort01], 3, [1]>;708def : WriteRes<WriteLoad, [LNLPPort20_21_22]> {709 let Latency = 4;710}711def : WriteRes<WriteMMXMOVMSK, [LNLPVPort00_01]> {712 let Latency = 3 ;713}714defm : LNLPWriteResPair<WriteMPSAD, [LNLPVPort02_03, LNLPVPort02_03], 4, [1, 1], 2, 7>;715defm : LNLPWriteResPair<WriteMPSADY, [LNLPVPort02_03, LNLPVPort02_03], 4, [1, 1], 2, 8>;716defm : LNLPWriteResPair<WriteMULX32, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 4, [1, 1, 1], 2>;717defm : LNLPWriteResPair<WriteMULX64, [LNLPPort01_03_05, LNLPPort01_03_05], 4, [1, 1]>;718// FIXME: Incompleted schedwrite.719def : WriteRes<WriteMicrocoded, [LNLPPort00_01_02_03_04_05]> {720 let Latency = LunarlakePModel.MaxLatency;721}722def : WriteRes<WriteMove, [LNLPPort00_01_02_03_04_05]>;723defm : X86WriteRes<WriteNop, [], 1, [], 0>;724defm : X86WriteRes<WritePCmpEStrI, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05], 16, [3, 2, 1, 1, 1], 8>;725defm : X86WriteRes<WritePCmpEStrILd, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort01_03_05], 31, [3, 1, 1, 1, 1, 1], 8>;726defm : X86WriteRes<WritePCmpEStrM, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort01_03_05], 16, [3, 3, 1, 1, 1], 9>;727defm : X86WriteRes<WritePCmpEStrMLd, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort01_03_05], 17, [3, 2, 1, 1, 1, 1], 9>;728defm : LNLPWriteResPair<WritePCmpIStrI, [LNLPPort00], 11, [3], 3, 20>;729defm : LNLPWriteResPair<WritePCmpIStrM, [LNLPPort00], 11, [3], 3>;730defm : LNLPWriteResPair<WritePHAdd, [LNLPVPort00_01_02_03, LNLPVPort02_03], 3, [1, 2], 3, 8>;731defm : LNLPWriteResPair<WritePHAddX, [LNLPVPort00_01_02_03, LNLPVPort02_03], 2, [1, 2], 3, 7>;732defm : LNLPWriteResPair<WritePHAddY, [LNLPVPort00_01_02_03, LNLPVPort02_03], 2, [1, 2], 3, 8>;733def : WriteRes<WritePHMINPOS, [LNLPVPort00_01]> {734 let Latency = 5;735}736def : WriteRes<WritePHMINPOSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {737 let Latency = 11;738}739 740// FIXME : uops info is incorrect 741defm : LNLPWriteResPair<WritePMULLD, [LNLPVPort00_01_02_03], 10, [2], 2, 8>;742defm : LNLPWriteResPair<WritePMULLDY, [LNLPVPort00_01_02_03], 10, [2], 2, 8>; 743defm : X86WriteResPairUnsupported<WritePMULLDZ>;744defm : LNLPWriteResPair<WritePOPCNT, [LNLPPort01_03_05], 3, [1]>;745defm : LNLPWriteResPair<WritePSADBW, [LNLPVPort02_03], 3, [1], 1, 8>;746defm : LNLPWriteResPair<WritePSADBWX, [LNLPVPort02_03], 3, [1], 1, 7>;747defm : LNLPWriteResPair<WritePSADBWY, [LNLPVPort02_03], 3, [1], 1, 8>;748defm : X86WriteResPairUnsupported<WritePSADBWZ>;749defm : X86WriteRes<WriteRMW, [LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 1, [1, 1, 1], 3>;750defm : X86WriteRes<WriteRotate, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 2, [1, 2], 3>;751defm : X86WriteRes<WriteRotateLd, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 12, [1, 2], 3>;752defm : X86WriteRes<WriteRotateCL, [LNLPPort01_03_05], 2, [2], 2>;753defm : X86WriteRes<WriteRotateCLLd, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 19, [2, 3, 2], 7>;754defm : X86WriteRes<WriteSETCC, [LNLPPort01_03_05], 2, [2], 2>;755defm : X86WriteRes<WriteSETCCStore, [LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27], 13, [2, 1, 1], 4>;756defm : X86WriteRes<WriteSHDmrcl, [LNLPPort00_01_02_03_04_05,LNLPPort01_03_05 , LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1, 1, 1, 1, 1], 6>;757defm : X86WriteRes<WriteSHDmri, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1, 1, 1, 1], 5>;758defm : X86WriteRes<WriteSHDrrcl, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 5, [1, 1, 1], 3>;759def : WriteRes<WriteSHDrri, [LNLPPort01_03_05]> {760 let Latency = 3;761}762defm : X86WriteRes<WriteSTMXCSR, [LNLPPort00_02_04, LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], LunarlakePModel.MaxLatency, [1, 6, 1, 1], 4>;763def : WriteRes<WriteShift, [LNLPPort01_03_05]>;764defm : X86WriteRes<WriteShiftLd, [LNLPPort01_03_05, LNLPPort20_21_22], 5, [1, 4], 2>;765defm : X86WriteRes<WriteShiftCL, [LNLPPort00_02_04], 2, [2], 2>;766defm : X86WriteRes<WriteShiftCLLd, [LNLPPort00_02_04], 12, [2], 2>;767defm : LNLPWriteResPair<WriteShuffle, [LNLPVPort02_03], 1, [1], 1, 8>;768defm : LNLPWriteResPair<WriteShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;769defm : LNLPWriteResPair<WriteShuffleX, [LNLPVPort02_03], 1, [1], 1, 7>;770defm : LNLPWriteResPair<WriteShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;771defm : X86WriteResPairUnsupported<WriteShuffleZ>;772defm : X86WriteRes<WriteStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;773defm : X86WriteRes<WriteStoreNT, [LNLPPort10_11, LNLPPort25_26_27], 512, [1, 1], 2>;774def : WriteRes<WriteSystem, [LNLPPort00_01_02_03_04_05]> {775 let Latency = LunarlakePModel.MaxLatency;776}777def : WriteRes<WriteTZCNT, [LNLPPort01_03_05]> {778 let Latency = 3;779}780def : WriteRes<WriteTZCNTLd, [LNLPPort01_03_05, LNLPPort20_21_22]> {781 let ReleaseAtCycles = [3, 4];782 let Latency = 7;783}784def : WriteRes<WriteVPMOV256, [LNLPVPort02_03]> {785 let Latency = 3;786}787defm : X86WriteRes<WriteVPMOV256Ld, [LNLPVPort02_03, LNLPPort20_21_22], 10, [3, 7], 2>;788defm : X86WriteRes<WriteVarBlend, [LNLPVPort00_01_02_03], 3, [3], 3>;789defm : X86WriteRes<WriteVarBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [3, 6], 4>;790defm : X86WriteRes<WriteVarBlendY, [LNLPVPort00_01_02_03], 3, [3], 3>;791defm : X86WriteRes<WriteVarBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 9, [3, 7], 4>;792defm : X86WriteResPairUnsupported<WriteVarBlendZ>;793defm : LNLPWriteResPair<WriteVarShuffle, [LNLPVPort02_03, LNLPVPort00_01], 3, [1, 1], 2, 8>;794def : WriteRes<WriteVarShuffle256, [LNLPVPort02_03]> {795 let Latency = 3; 796}797def : WriteRes<WriteVarShuffle256Ld, [LNLPVPort02_03, LNLPPort20_21_22]> {798 let ReleaseAtCycles = [3, 7];799 let Latency = 10;800}801def : WriteRes<WriteVarShuffleX, [LNLPVPort02_03]>;802defm : X86WriteRes<WriteVarShuffleXLd, [LNLPVPort02_03, LNLPPort20_21_22], 7, [1, 6], 2>;803def : WriteRes<WriteVarShuffleY, [LNLPVPort02_03]>;804defm : X86WriteRes<WriteVarShuffleYLd, [LNLPVPort02_03, LNLPPort20_21_22], 8, [1, 7], 2>;805defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;806 807def : WriteRes<WriteVarVecShift, [LNLPVPort00_01]>;808def : WriteRes<WriteVarVecShiftLd, [LNLPVPort00_01, LNLPPort20_21_22]> {809 let ReleaseAtCycles = [1, 6];810 let Latency = 7;811}812def : WriteRes<WriteVarVecShiftY, [LNLPVPort00_01]>;813def : WriteRes<WriteVarVecShiftYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {814 let ReleaseAtCycles = [1, 7];815 let Latency = 8;816}817defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;818defm : LNLPWriteResPair<WriteVecALU, [LNLPVPort00], 1, [1], 1, 8>; // 4 ports ?819def : WriteRes<WriteVecALUX, [LNLPVPort00_01]>;820def : WriteRes<WriteVecALUXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {821 let ReleaseAtCycles = [1, 6];822 let Latency = 7;823}824def : WriteRes<WriteVecALUY, [LNLPVPort00_01]>;825def : WriteRes<WriteVecALUYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {826 let ReleaseAtCycles = [1, 7];827 let Latency = 8;828}829defm : X86WriteResPairUnsupported<WriteVecALUZ>;830defm : X86WriteRes<WriteVecExtract, [LNLPVPort00_01, LNLPVPort02_03], 4, [3, 1], 2>;831defm : X86WriteRes<WriteVecExtractSt, [LNLPVPort02_03, LNLPPort10_11, LNLPPort25_26_27], 2, [1, 1, 1], 2>;832defm : LNLPWriteResPair<WriteVecIMul, [LNLPVPort00_01], 5, [1], 1, 8>;833def : WriteRes<WriteVecIMulX, [LNLPVPort00_01]> {834 let ReleaseAtCycles = [4];835 let Latency = 4;836}837def : WriteRes<WriteVecIMulXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {838 let ReleaseAtCycles = [4, 6];839 let Latency = 10;840}841def : WriteRes<WriteVecIMulY, [LNLPVPort00_01]> {842 let ReleaseAtCycles = [4];843 let Latency = 4;844}845def : WriteRes<WriteVecIMulYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {846 let ReleaseAtCycles = [4, 7];847 let Latency = 11;848}849defm : X86WriteResPairUnsupported<WriteVecIMulZ>;850defm : X86WriteRes<WriteVecInsert, [LNLPPort01_03_05, LNLPVPort02_03], 5, [4, 1], 2>;851defm : X86WriteRes<WriteVecInsertLd, [LNLPVPort02_03, LNLPPort20_21_22], 7, [1, 6], 2>;852def : WriteRes<WriteVecLoad, [LNLPPort20_21_22]> {853 let Latency = 6;854}855// FIXME: Incompleted schedwrite.856def : WriteRes<WriteVecLoadNT, [LNLPPort20_21_22]> {857 let Latency = 7;858}859// FIXME: Incompleted schedwrite.860def : WriteRes<WriteVecLoadNTY, [LNLPPort20_21_22]> {861 let Latency = 8;862}863 864def : WriteRes<WriteVecLoadX, [LNLPPort20_21_22]> {865 let Latency = 6;866}867def : WriteRes<WriteVecLoadY, [LNLPPort20_21_22]> {868 let Latency = 7;869}870defm : LNLPWriteResPair<WriteVecLogic, [LNLPVPort00_01_02_03], 1, [1], 1, 8>;871def : WriteRes<WriteVecLogicX, [LNLPVPort00_01_02_03]>;872def : WriteRes<WriteVecLogicXLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {873 let ReleaseAtCycles = [1, 6];874 let Latency = 7;875}876def : WriteRes<WriteVecLogicY, [LNLPVPort00_01_02_03]>;877def : WriteRes<WriteVecLogicYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {878 let ReleaseAtCycles = [1, 7];879 let Latency = 8;880}881defm : X86WriteResPairUnsupported<WriteVecLogicZ>;882def : WriteRes<WriteVecMOVMSK, [LNLPVPort00_01]> {883 let ReleaseAtCycles = [3];884 let Latency = 3;885}886def : WriteRes<WriteVecMOVMSKY, [LNLPVPort00_01]> {887 let ReleaseAtCycles = [3];888 let Latency = 3; // Tool added Max889}890defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;891defm : X86WriteRes<WriteVecMaskedLoad, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;892defm : X86WriteRes<WriteVecMaskedLoadY, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;893defm : X86WriteRes<WriteVecMaskedStore32, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>; // updated lat from 3 to 14894defm : X86WriteRes<WriteVecMaskedStore32Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;895defm : X86WriteRes<WriteVecMaskedStore64, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;896defm : X86WriteRes<WriteVecMaskedStore64Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;897def : WriteRes<WriteVecMove, [LNLPVPort00_01_02_03]>;898def : WriteRes<WriteVecMoveFromGpr, [LNLPPort01_03_05]> {899 let Latency = 3; // Originally 4900}901def : WriteRes<WriteVecMoveToGpr, [LNLPVPort00_01]> {902 let Latency = 3;903}904defm : X86WriteRes<WriteVecMoveX, [LNLPVPort00_01_02_03], 1, [2], 2>;905defm : X86WriteRes<WriteVecMoveY, [], 1, [], 0>;906defm : X86WriteResUnsupported<WriteVecMoveZ>;907defm : LNLPWriteResPair<WriteVecShift, [LNLPVPort00_01], 1, [1], 1, 8>;908def : WriteRes<WriteVecShiftImm, [LNLPVPort00_01]>;909def : WriteRes<WriteVecShiftImmX, [LNLPVPort00_01]>;910defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;911def : WriteRes<WriteVecShiftImmY, [LNLPVPort00_01]>;912defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;913defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;914defm : X86WriteRes<WriteVecShiftX, [LNLPVPort00_01, LNLPVPort02_03], 2, [1, 1], 2>;915defm : X86WriteRes<WriteVecShiftXLd, [LNLPVPort00_01, LNLPPort20_21_22], 8, [1, 1], 2>; // 7916defm : X86WriteRes<WriteVecShiftY, [LNLPVPort00_01, LNLPVPort02_03], 4, [1, 1], 2>;917defm : X86WriteRes<WriteVecShiftYLd, [LNLPVPort00_01, LNLPPort20_21_22], 9, [1, 7], 2>; // 8918defm : X86WriteResPairUnsupported<WriteVecShiftZ>;919defm : X86WriteRes<WriteVecStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>; 920defm : X86WriteRes<WriteVecStoreNT, [LNLPPort10_11, LNLPPort25_26_27], 511, [1, 1], 2>; // historic value921defm : X86WriteRes<WriteVecStoreNTY, [LNLPPort10_11, LNLPPort25_26_27], 507, [1, 1], 2>;922defm : X86WriteRes<WriteVecStoreX, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;923defm : X86WriteRes<WriteVecStoreY, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;924defm : X86WriteRes<WriteVecTest, [LNLPVPort00_01, LNLPVPort02_03], 4, [1, 1], 2>;925defm : X86WriteRes<WriteVecTestLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 10, [3, 1, 6], 3>;926defm : X86WriteRes<WriteVecTestY, [LNLPVPort00_01, LNLPVPort02_03], LunarlakePModel.MaxLatency, [3, 1], 2>;927defm : X86WriteRes<WriteVecTestYLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 11, [3, 1, 6], 3>;928defm : X86WriteRes<WriteXCHG, [LNLPPort00_01_02_03_04_05], 2, [3], 3>;929def : WriteRes<WriteZero, []>;930 931// Manual Regressive SchedWriteRes and InstRW Definition. Suffix with "_X"932// All _X(N) prefix sequence are defs used from prev. generation to bypass incomplete data.933def LNLPWriteResGroupX0 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11]> {934 let Latency = 7;935 let NumMicroOps = 3;936}937def : InstRW<[LNLPWriteResGroupX0], (instregex "^AA(D|N)D64mr$",938 "^A(X?)OR64mr$")>;939def LNLPWriteResGroupX1 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {940 let ReleaseAtCycles = [2, 1, 1, 1, 1];941 let Latency = 12;942 let NumMicroOps = 6;943}944def : InstRW<[LNLPWriteResGroupX1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;945def LNLPWriteResGroupX2 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {946 let Latency = 6;947 let NumMicroOps = 2;948}949def : InstRW<[LNLPWriteResGroupX2], (instregex "^JMP(16|32|64)m((_NT)?)$",950 "^RET(16|32)$",951 "^RORX(32|64)mi$")>;952def : InstRW<[LNLPWriteResGroupX2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",953 "^AD(C|O)X(32|64)rm$")>;954def LNLPWriteResGroupX5 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {955 let Latency = 6;956 let NumMicroOps = 2;957}958def : InstRW<[LNLPWriteResGroupX5], (instregex "^CMP(8|16|32)mi$",959 "^CMP(8|16|32|64)mi8$",960 "^MOV(8|16)rm$",961 "^POP(16|32)r((mr)?)$")>;962def : InstRW<[LNLPWriteResGroupX5], (instrs CMP64mi32,963 MOV8rm_NOREX,964 MOVZX16rm8)>;965def : InstRW<[LNLPWriteResGroupX5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",966 "^AND(8|16|32)rm$",967 "^(X?)OR(8|16|32)rm$")>;968def : InstRW<[LNLPWriteResGroupX5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;969def LNLPWriteResGroupX6 : SchedWriteRes<[]> {970 let NumMicroOps = 0;971}972def : InstRW<[LNLPWriteResGroupX6], (instregex "^(ADD|SUB)64ri8$",973 "^(DE|IN)C64r$",974 "^MOV64rr((_REV)?)$")>;975def : InstRW<[LNLPWriteResGroupX6], (instrs CLC,976 JMP_2)>;977def LNLPWriteResGroupX7 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {978 let Latency = 13;979 let NumMicroOps = 4;980}981def : InstRW<[LNLPWriteResGroupX7], (instregex "^A(D|N)D8mi(8?)$",982 "^(DE|IN)C8m$",983 "^N(EG|OT)8m$",984 "^(X?)OR8mi(8?)$",985 "^SUB8mi(8?)$")>;986def : InstRW<[LNLPWriteResGroupX7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",987 "^(X?)OR8mr$")>;988def : InstRW<[LNLPWriteResGroupX7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;989def LNLPWriteResGroupX8 : SchedWriteRes<[LNLPPort01_03_05]> {990 let Latency = 3;991}992def : InstRW<[LNLPWriteResGroupX8], (instregex "^(V?)(ADD|SUB)SSrr((_Int)?)$")>;993def LNLPWriteResGroupX9 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {994 let Latency = 10;995 let NumMicroOps = 2;996}997def : InstRW<[LNLPWriteResGroupX9], (instregex "^ADD_F(32|64)m$",998 "^ILD_F(16|32|64)m$",999 "^SUB(R?)_F(32|64)m$")>;1000def LNLPWriteResGroupX10 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {1001 let ReleaseAtCycles = [1, 2];1002 let Latency = 13;1003 let NumMicroOps = 3;1004}1005def : InstRW<[LNLPWriteResGroupX10], (instregex "^ADD_FI(16|32)m$",1006 "^SUB(R?)_FI(16|32)m$")>;1007 1008def LNLPWriteResGroupX11 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {1009 let Latency = 2;1010}1011def : InstRW<[LNLPWriteResGroupX11], (instregex "^AND(8|16|32|64)r(r|i8)$",1012 "^AND(8|16|32|64)rr_REV$",1013 "^(AND|TEST)(32|64)i32$",1014 "^(AND|TEST)(8|32)ri$",1015 "^(AND|TEST)64ri32$",1016 "^(AND|TEST)8i8$",1017 "^(X?)OR(8|16|32|64)r(r|i8)$",1018 "^(X?)OR(8|16|32|64)rr_REV$",1019 "^(X?)OR(32|64)i32$",1020 "^(X?)OR(8|32)ri$",1021 "^(X?)OR64ri32$",1022 "^(X?)OR8i8$",1023 "^TEST(8|16|32|64)rr$")>;1024def : InstRW<[LNLPWriteResGroupX11], (instrs XOR8rr_NOREX)>;1025def LNLPWriteResGroupX12 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {1026 let Latency = 7;1027 let NumMicroOps = 2;1028}1029def : InstRW<[LNLPWriteResGroupX12], (instregex "^TEST(8|16|32)mi$")>;1030def : InstRW<[LNLPWriteResGroupX12], (instrs TEST64mi32)>;1031def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd], (instregex "^(X?)OR64rm$")>;1032def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd], (instrs AND64rm)>;1033def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;1034def LNLPWriteResGroupX13 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {1035 let Latency = 7;1036 let NumMicroOps = 2;1037}1038def : InstRW<[LNLPWriteResGroupX13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;1039def LNLPWriteResGroupX14 : SchedWriteRes<[LNLPPort01_03_05]> {1040 let Latency = 2;1041}1042def : InstRW<[LNLPWriteResGroupX14], (instregex "^ANDN(32|64)rr$")>;1043def LNLPWriteResGroupX15 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22]> {1044 let ReleaseAtCycles = [5, 2, 1, 1];1045 let Latency = 10;1046 let NumMicroOps = 9;1047}1048def : InstRW<[LNLPWriteResGroupX15], (instrs BT64mr)>;1049def LNLPWriteResGroupX16 : SchedWriteRes<[LNLPPort01]> {1050 let Latency = 3;1051}1052def : InstRW<[LNLPWriteResGroupX16], (instregex "^BT((C|R|S)?)64rr$")>;1053def LNLPWriteResGroupX17 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1054 let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];1055 let Latency = 17;1056 let NumMicroOps = 10;1057}1058def : InstRW<[LNLPWriteResGroupX17], (instregex "^BT(C|R|S)64mr$")>;1059def LNLPWriteResGroupX18 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1060 let Latency = 7;1061 let NumMicroOps = 5;1062}1063def : InstRW<[LNLPWriteResGroupX18], (instregex "^CALL(16|32|64)m((_NT)?)$")>;1064 1065def LNLPWriteResGroupX19 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {1066 let Latency = 3;1067 let NumMicroOps = 3;1068}1069def : InstRW<[LNLPWriteResGroupX19], (instregex "^CALL(16|32|64)r((_NT)?)$")>;1070 1071def LNLPWriteResGroupX20 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1072 let Latency = 3;1073 let NumMicroOps = 2;1074}1075def : InstRW<[LNLPWriteResGroupX20], (instrs CALL64pcrel32,1076 MFENCE)>;1077def LNLPWriteResGroupX21 : SchedWriteRes<[LNLPVPort02_03]>;1078def : InstRW<[LNLPWriteResGroupX21], (instregex "^C(DQ|WD)E$",1079 "^(V?)MOVS(H|L)DUPrr$",1080 "^(V?)SHUFP(D|S)rri$",1081 "^VMOVS(H|L)DUPYrr$",1082 "^VSHUFP(D|S)Yrri$")>;1083def : InstRW<[LNLPWriteResGroupX21], (instrs CBW)>;1084 1085def LNLPWriteResGroupX22 : SchedWriteRes<[LNLPPort00_02_04]>;1086def : InstRW<[LNLPWriteResGroupX22], (instregex "^C(DQ|QO)$",1087 "^(CL|ST)AC$")>;1088def LNLPWriteResGroupX23 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1089 let Latency = 3;1090 let NumMicroOps = 2;1091}1092def : InstRW<[LNLPWriteResGroupX23], (instrs CLD)>;1093 1094def LNLPWriteResGroupX24 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1095 let Latency = 3;1096 let NumMicroOps = 3;1097}1098def : InstRW<[LNLPWriteResGroupX24], (instrs CLDEMOTE)>;1099 1100def LNLPWriteResGroupX25 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {1101 let Latency = 2;1102 let NumMicroOps = 4;1103}1104def : InstRW<[LNLPWriteResGroupX25], (instrs CLFLUSH)>;1105 1106def LNLPWriteResGroupX26 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1107 let Latency = 2;1108 let NumMicroOps = 3;1109}1110def : InstRW<[LNLPWriteResGroupX26], (instrs CLFLUSHOPT)>;1111 1112def LNLPWriteResGroupX27 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01]> {1113 let ReleaseAtCycles = [2, 1];1114 let Latency = LunarlakePModel.MaxLatency;1115 let NumMicroOps = 3;1116}1117def : InstRW<[LNLPWriteResGroupX27], (instrs CLI)>;1118 1119def LNLPWriteResGroupX28 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01, LNLPPort01_03_05]> {1120 let ReleaseAtCycles = [6, 1, 3];1121 let Latency = LunarlakePModel.MaxLatency;1122 let NumMicroOps = 10;1123}1124def : InstRW<[LNLPWriteResGroupX28], (instrs CLTS)>;1125 1126def LNLPWriteResGroupX29 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1127 let Latency = 5;1128 let NumMicroOps = 3;1129}1130def : InstRW<[LNLPWriteResGroupX29], (instregex "^MOV16o(16|32|64)a$")>;1131def : InstRW<[LNLPWriteResGroupX29], (instrs CLWB)>;1132 1133def LNLPWriteResGroupX30 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {1134 let ReleaseAtCycles = [5, 2];1135 let Latency = 6;1136 let NumMicroOps = 7;1137}1138def : InstRW<[LNLPWriteResGroupX30], (instregex "^CMPS(B|L|Q|W)$")>;1139 1140def LNLPWriteResGroupX31 : SchedWriteRes<[LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1141 let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];1142 let Latency = 32;1143 let NumMicroOps = 22;1144}1145def : InstRW<[LNLPWriteResGroupX31], (instrs CMPXCHG16B)>;1146 1147def LNLPWriteResGroupX32 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1148 let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];1149 let Latency = 25;1150 let NumMicroOps = 16;1151}1152def : InstRW<[LNLPWriteResGroupX32], (instrs CMPXCHG8B)>;1153 1154def LNLPWriteResGroupX33 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1155 let ReleaseAtCycles = [1, 2, 1, 1, 1];1156 let Latency = 13;1157 let NumMicroOps = 6;1158}1159def : InstRW<[LNLPWriteResGroupX33], (instrs CMPXCHG8rm)>;1160 1161def LNLPWriteResGroupX34 : SchedWriteRes<[LNLPPort00, LNLPVPort00_01, LNLPPort00_02_04, LNLPPort01, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1162 let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];1163 let Latency = 18;1164 let NumMicroOps = 26;1165}1166def : InstRW<[LNLPWriteResGroupX34], (instrs CPUID)>;1167 1168def LNLPWriteResGroupX35 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01, LNLPPort20_21_22]> {1169 let Latency = 26;1170 let NumMicroOps = 3;1171}1172def LNLPWriteResGroupX36 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22, LNLPPort01_03_05]> {1173 let Latency = 12;1174 let NumMicroOps = 3;1175}1176def : InstRW<[LNLPWriteResGroupX36], (instrs CVTSI642SSrm)>;1177def : InstRW<[LNLPWriteResGroupX36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;1178def LNLPWriteResGroupX37 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05]> {1179 let ReleaseAtCycles = [1, 2];1180 let Latency = 8;1181 let NumMicroOps = 3;1182}1183def : InstRW<[LNLPWriteResGroupX37, ReadInt2Fpu], (instrs CVTSI642SSrr)>;1184def : InstRW<[LNLPWriteResGroupX37, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;1185def LNLPWriteResGroupX38 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01, LNLPPort01_03_05]> {1186 let Latency = 8;1187 let NumMicroOps = 3;1188}1189def : InstRW<[LNLPWriteResGroupX38, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;1190def LNLPWriteResGroupX39 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1191 let Latency = 2;1192 let NumMicroOps = 2;1193}1194def : InstRW<[LNLPWriteResGroupX39], (instregex "^J(E|R)CXZ$")>;1195def : InstRW<[LNLPWriteResGroupX39], (instrs CWD)>;1196 1197def LNLPWriteResGroupX40 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]>;1198def : InstRW<[LNLPWriteResGroupX40], (instregex "^(LD|ST)_Frr$",1199 "^MOV16s(m|r)$",1200 "^MOV(32|64)sr$")>;1201def : InstRW<[LNLPWriteResGroupX40], (instrs DEC16r_alt,1202 SALC,1203 ST_FPrr,1204 SYSCALL)>;1205 1206def LNLPWriteResGroupX41 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1207 let Latency = 7;1208}1209def : InstRW<[LNLPWriteResGroupX41], (instrs DEC32r_alt)>;1210def LNLPWriteResGroupX42 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22]> {1211 let Latency = 27;1212 let NumMicroOps = 2;1213}1214def : InstRW<[LNLPWriteResGroupX42], (instregex "^DIVR_F(32|64)m$")>;1215def LNLPWriteResGroupX43 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22, LNLPPort01_03_05]> {1216 let Latency = 30;1217 let NumMicroOps = 3;1218}1219def : InstRW<[LNLPWriteResGroupX43], (instregex "^DIVR_FI(16|32)m$")>;1220 1221def LNLPWriteResGroupX44 : SchedWriteRes<[LNLPPort00]> {1222 let Latency = 15;1223}1224def : InstRW<[LNLPWriteResGroupX44], (instregex "^DIVR_F(P?)rST0$")>;1225def : InstRW<[LNLPWriteResGroupX44], (instrs DIVR_FST0r)>;1226def LNLPWriteResGroupX45 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {1227 let Latency = 20;1228 let NumMicroOps = 2;1229}1230def : InstRW<[LNLPWriteResGroupX45, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;1231def LNLPWriteResGroupX46 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22]> {1232 let Latency = 22;1233 let NumMicroOps = 2;1234}1235def : InstRW<[LNLPWriteResGroupX46], (instregex "^DIV_F(32|64)m$")>;1236def LNLPWriteResGroupX47 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22, LNLPPort01_03_05]> {1237 let Latency = 25;1238 let NumMicroOps = 3;1239}1240def : InstRW<[LNLPWriteResGroupX47], (instregex "^DIV_FI(16|32)m$")>;1241 1242def LNLPWriteResGroupX48 : SchedWriteRes<[LNLPPort00]> {1243 let Latency = 20;1244}1245def : InstRW<[LNLPWriteResGroupX48], (instregex "^DIV_F(P?)rST0$")>;1246def : InstRW<[LNLPWriteResGroupX48], (instrs DIV_FST0r)>;1247 1248def LNLPWriteResGroupX49 : SchedWriteRes<[LNLPPort00, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1249 let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];1250 let Latency = 126;1251 let NumMicroOps = 57;1252}1253def : InstRW<[LNLPWriteResGroupX49], (instrs ENTER)>;1254 1255def LNLPWriteResGroupX50 : SchedWriteRes<[LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1256 let Latency = 12;1257 let NumMicroOps = 3;1258}1259def : InstRW<[LNLPWriteResGroupX50], (instregex "^(V?)EXTRACTPSmri$")>;1260def : InstRW<[LNLPWriteResGroupX50], (instrs SMSW16m)>;1261 1262def LNLPWriteResGroupX51 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05]> {1263 let Latency = 4;1264 let NumMicroOps = 2;1265}1266def : InstRW<[LNLPWriteResGroupX51], (instregex "^(V?)EXTRACTPSrri$")>;1267def : InstRW<[LNLPWriteResGroupX51], (instrs MMX_PEXTRWrri)>;1268 1269def LNLPWriteResGroupX52 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11, LNLPVPort02_03]> {1270 let Latency = 7;1271 let NumMicroOps = 5;1272}1273def : InstRW<[LNLPWriteResGroupX52], (instrs FARCALL64m)>;1274 1275def LNLPWriteResGroupX53 : SchedWriteRes<[LNLPPort20_21_22, LNLPVPort02_03]> {1276 let Latency = 6;1277 let NumMicroOps = 2;1278}1279def : InstRW<[LNLPWriteResGroupX53], (instrs FARJMP64m,1280 JMP64m_REX)>;1281 1282def LNLPWriteResGroupX54 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11]> {1283 let NumMicroOps = 2;1284}1285def : InstRW<[LNLPWriteResGroupX54], (instregex "^(V?)MASKMOVDQU((64)?)$",1286 "^ST_FP(32|64|80)m$")>;1287def : InstRW<[LNLPWriteResGroupX54], (instrs FBSTPm,1288 VMPTRSTm)>;1289 1290def LNLPWriteResGroupX55 : SchedWriteRes<[LNLPPort01_03_05]> {1291 let ReleaseAtCycles = [2];1292 let Latency = 2;1293 let NumMicroOps = 2;1294}1295def : InstRW<[LNLPWriteResGroupX55], (instrs FDECSTP)>;1296 1297def LNLPWriteResGroupX56 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {1298 let ReleaseAtCycles = [1, 2];1299 let Latency = 11;1300 let NumMicroOps = 3;1301}1302def : InstRW<[LNLPWriteResGroupX56], (instregex "^FICOM(P?)(16|32)m$")>;1303 1304def LNLPWriteResGroupX57 : SchedWriteRes<[LNLPPort01_03_05]>;1305def : InstRW<[LNLPWriteResGroupX57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;1306def : InstRW<[LNLPWriteResGroupX57], (instrs FINCSTP,1307 FNOP)>;1308 1309def LNLPWriteResGroupX58 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05, LNLPPort20_21_22]> {1310 let Latency = 7;1311 let NumMicroOps = 3;1312}1313def : InstRW<[LNLPWriteResGroupX58], (instrs FLDCW16m)>;1314 1315def LNLPWriteResGroupX59 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPPort20_21_22]> {1316 let ReleaseAtCycles = [2, 39, 5, 10, 8];1317 let Latency = 62;1318 let NumMicroOps = 64;1319}1320def : InstRW<[LNLPWriteResGroupX59], (instrs FLDENVm)>;1321 1322def LNLPWriteResGroupX60 : SchedWriteRes<[LNLPVPort00_01_02_03]> {1323 let ReleaseAtCycles = [4];1324 let Latency = 4;1325 let NumMicroOps = 4;1326}1327def : InstRW<[LNLPWriteResGroupX60], (instrs FNCLEX)>;1328 1329def LNLPWriteResGroupX61 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort01_03_05]> {1330 let ReleaseAtCycles = [6, 3, 6];1331 let Latency = 75;1332 let NumMicroOps = 15;1333}1334def : InstRW<[LNLPWriteResGroupX61], (instrs FNINIT)>;1335 1336def LNLPWriteResGroupX62 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPVPort02_03]> {1337 let Latency = 2;1338 let NumMicroOps = 3;1339}1340def : InstRW<[LNLPWriteResGroupX62], (instrs FNSTCW16m)>;1341 1342def LNLPWriteResGroupX63 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03]> {1343 let Latency = 3;1344 let NumMicroOps = 2;1345}1346def : InstRW<[LNLPWriteResGroupX63], (instrs FNSTSW16r)>;1347 1348def LNLPWriteResGroupX64 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11]> {1349 let Latency = 3;1350 let NumMicroOps = 3;1351}1352def : InstRW<[LNLPWriteResGroupX64], (instrs FNSTSWm)>;1353 1354def LNLPWriteResGroupX65 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPVPort02_03]> {1355 let ReleaseAtCycles = [9, 30, 21, 1, 11, 11, 16, 1];1356 let Latency = 106;1357 let NumMicroOps = 100;1358}1359def : InstRW<[LNLPWriteResGroupX65], (instrs FSTENVm)>;1360 1361def LNLPWriteResGroupX66 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPVPort02_03]> {1362 let ReleaseAtCycles = [4, 47, 1, 2, 1, 33, 2];1363 let Latency = 63;1364 let NumMicroOps = 90;1365}1366def : InstRW<[LNLPWriteResGroupX66], (instrs FXRSTOR)>;1367 1368def LNLPWriteResGroupX67 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPVPort02_03]> {1369 let ReleaseAtCycles = [4, 45, 1, 2, 1, 31, 4];1370 let Latency = 63;1371 let NumMicroOps = 88;1372}1373def : InstRW<[LNLPWriteResGroupX67], (instrs FXRSTOR64)>;1374 1375def LNLPWriteResGroupX68 : SchedWriteRes<[LNLPVPort02_03, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1376 let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];1377 let Latency = LunarlakePModel.MaxLatency;1378 let NumMicroOps = 110;1379}1380def : InstRW<[LNLPWriteResGroupX68], (instregex "^FXSAVE((64)?)$")>;1381 1382def LNLPWriteResGroupX69 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {1383 let Latency = 12;1384 let NumMicroOps = 2;1385}1386 1387def LNLPWriteResGroupX77 : SchedWriteRes<[LNLPPort00_02_04]> {1388 let NumMicroOps = 4;1389}1390def : InstRW<[LNLPWriteResGroupX77], (instrs INC16r_alt)>;1391 1392def LNLPWriteResGroupX78 : SchedWriteRes<[LNLPPort20_21_22]> {1393 let Latency = 7;1394}1395def : InstRW<[LNLPWriteResGroupX78], (instrs INC32r_alt)>;1396 1397def LNLPWriteResGroupX85 : SchedWriteRes<[LNLPPort00_02_04]>;1398def : InstRW<[LNLPWriteResGroupX85], (instrs JMP64r_REX)>;1399def LNLPWriteResGroupX86 : SchedWriteRes<[]> {1400 let Latency = 0;1401 let NumMicroOps = 0;1402}1403def : InstRW<[LNLPWriteResGroupX86], (instregex "^JMP_(1|4)$")>;1404def : InstRW<[LNLPWriteResGroupX86], (instrs VZEROUPPER)>;1405 1406def LNLPWriteResGroupX93 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1407 let Latency = 2;1408 let NumMicroOps = 2;1409}1410def : InstRW<[LNLPWriteResGroupX93], (instrs LEA16r)>;1411 1412def LNLPWriteResGroupX104 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1413 let ReleaseAtCycles = [4, 6, 1];1414 let Latency = 3;1415 let NumMicroOps = 11;1416}1417def : InstRW<[LNLPWriteResGroupX104], (instrs LOOPE)>;1418 1419def LNLPWriteResGroupX105 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1420 let ReleaseAtCycles = [4, 6, 1];1421 let Latency = 2;1422 let NumMicroOps = 11;1423}1424def : InstRW<[LNLPWriteResGroupX105], (instrs LOOPNE)>;1425 1426def LNLPWriteResGroupX115 : SchedWriteRes<[LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27]> {1427 let ReleaseAtCycles = [2, 1, 1];1428 let Latency = 12;1429 let NumMicroOps = 4;1430}1431def : InstRW<[LNLPWriteResGroupX115], (instregex "^MMX_MASKMOVQ((64)?)$")>;1432def LNLPWriteResGroupX118 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort00_01]> {1433 let Latency = 3;1434 let NumMicroOps = 2;1435}1436def : InstRW<[LNLPWriteResGroupX118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;1437def LNLPWriteResGroupX122 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {1438 let Latency = 9;1439 let NumMicroOps = 2;1440}1441def : InstRW<[LNLPWriteResGroupX122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;1442def LNLPWriteResGroupX123 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22, LNLPPort01_03_05]> {1443 let ReleaseAtCycles = [1, 1, 2];1444 let Latency = 11;1445 let NumMicroOps = 4;1446}1447def : InstRW<[LNLPWriteResGroupX123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;1448def LNLPWriteResGroupX124 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05]> {1449 let ReleaseAtCycles = [1, 2];1450 let Latency = 3;1451 let NumMicroOps = 3;1452}1453def : InstRW<[LNLPWriteResGroupX124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;1454def LNLPWriteResGroupX116 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1455 let Latency = 18;1456 let NumMicroOps = 2;1457}1458def : InstRW<[LNLPWriteResGroupX116], (instrs MMX_MOVD64mr)>;1459def LNLPWriteResGroupX117 : SchedWriteRes<[LNLPPort20_21_22]> {1460 let Latency = 8;1461}1462def : InstRW<[LNLPWriteResGroupX117], (instregex "^MMX_MOV(D|Q)64rm$",1463 "^VBROADCASTI128rm$")>;1464def : InstRW<[LNLPWriteResGroupX117], (instrs MMX_MOVD64to64rm)>;1465def LNLPWriteResGroupX120 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {1466 let ReleaseAtCycles = [1, 2];1467 let Latency = 12;1468 let NumMicroOps = 3;1469}1470def : InstRW<[LNLPWriteResGroupX120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;1471def : InstRW<[LNLPWriteResGroupX120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;1472def LNLPWriteResGroupX121 : SchedWriteRes<[LNLPPort01_03_05]> {1473 let ReleaseAtCycles = [2];1474 let Latency = 4;1475 let NumMicroOps = 2;1476}1477def : InstRW<[LNLPWriteResGroupX121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;1478def : InstRW<[LNLPWriteResGroupX121], (instrs MMX_PACKUSWBrr)>;1479def : InstRW<[LNLPWriteResGroupX121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrri)>;1480def LNLPWriteResGroupX125 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {1481 let Latency = 9;1482 let NumMicroOps = 2;1483}1484def : InstRW<[LNLPWriteResGroupX125, ReadAfterLd], (instrs MMX_PINSRWrmi)>;1485def LNLPWriteResGroupX126 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {1486 let Latency = 5;1487 let NumMicroOps = 2;1488}1489def : InstRW<[LNLPWriteResGroupX126], (instregex "^MOV16ao(16|32|64)$")>;1490def LNLPWriteResGroupX127 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1491 let Latency = 12;1492 let NumMicroOps = 3;1493}1494def : InstRW<[LNLPWriteResGroupX127], (instregex "^PUSH(F|G)S(16|32)$")>;1495def : InstRW<[LNLPWriteResGroupX127], (instrs MOV16ms,1496 MOVBE32mr)>;1497def LNLPWriteResGroupX128 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1498 let NumMicroOps = 2;1499}1500def : InstRW<[LNLPWriteResGroupX128], (instregex "^MOV(16|32|64)rs$",1501 "^S(TR|LDT)16r$")>;1502def LNLPWriteResGroupX129 : SchedWriteRes<[LNLPPort20_21_22]>;1503def : InstRW<[LNLPWriteResGroupX129], (instregex "^MOV32ao(16|32|64)$")>;1504def : InstRW<[LNLPWriteResGroupX129], (instrs MOV64ao64)>;1505def LNLPWriteResGroupX130 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1506 let NumMicroOps = 3;1507}1508def : InstRW<[LNLPWriteResGroupX130], (instregex "^MOV(8|32)o(16|32)a$",1509 "^MOV(8|32|64)o64a$")>;1510def LNLPWriteResGroupX131 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {1511 let Latency = 0;1512}1513def : InstRW<[LNLPWriteResGroupX131], (instregex "^MOV32rr((_REV)?)$",1514 "^MOVZX(32|64)rr8$")>;1515def : InstRW<[LNLPWriteResGroupX131], (instrs MOVZX32rr8_NOREX)>;1516 1517def LNLPWriteResGroupX132 : SchedWriteRes<[LNLPPort20_21_22]> {1518 let Latency = 5;1519}1520def : InstRW<[LNLPWriteResGroupX132], (instrs MOV64ao32)>;1521def LNLPWriteResGroupX134 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1522 let Latency = 12;1523 let NumMicroOps = 2;1524}1525def : InstRW<[LNLPWriteResGroupX134], (instrs MOV64o32a)>;1526def LNLPWriteResGroupX135 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1527 let Latency = LunarlakePModel.MaxLatency;1528 let NumMicroOps = 3;1529}1530def : InstRW<[LNLPWriteResGroupX135], (instrs MOV64rc)>;1531def LNLPWriteResGroupX137 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {1532 let NumMicroOps = 2;1533}1534def : InstRW<[LNLPWriteResGroupX137], (instregex "^MOV8ao(16|32|64)$")>;1535def LNLPWriteResGroupX138 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1536 let Latency = 13;1537 let NumMicroOps = 2;1538}1539def : InstRW<[LNLPWriteResGroupX138], (instregex "^MOV8m(i|r)$")>;1540def : InstRW<[LNLPWriteResGroupX138], (instrs MOV8mr_NOREX)>;1541def LNLPWriteResGroupX139 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {1542 let Latency = 12;1543 let NumMicroOps = 3;1544}1545def : InstRW<[LNLPWriteResGroupX139], (instrs MOVBE16mr)>;1546def LNLPWriteResGroupX142 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1547 let Latency = 12;1548 let NumMicroOps = 4;1549}1550def : InstRW<[LNLPWriteResGroupX142], (instrs MOVBE64mr,1551 PUSHF16,1552 SLDT16m,1553 STRm)>;1554 1555def LNLPWriteResGroupX144 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1556 let NumMicroOps = 4;1557}1558def : InstRW<[LNLPWriteResGroupX144], (instregex "^MOVDIR64B(16|32|64)$")>;1559def LNLPWriteResGroupX147 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {1560 let Latency = 8;1561 let NumMicroOps = 2;1562}1563def : InstRW<[LNLPWriteResGroupX147, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$")>;1564def LNLPWriteResGroupX148 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1565 let Latency = 512;1566 let NumMicroOps = 2;1567}1568def : InstRW<[LNLPWriteResGroupX148], (instrs MOVNTDQmr)>;1569def LNLPWriteResGroupX149 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1570 let Latency = 518;1571 let NumMicroOps = 2;1572}1573def : InstRW<[LNLPWriteResGroupX149], (instrs MOVNTImr)>;1574def LNLPWriteResGroupX150 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1575 let ReleaseAtCycles = [4, 1, 1, 1];1576 let Latency = 8;1577 let NumMicroOps = 7;1578}1579def : InstRW<[LNLPWriteResGroupX150], (instrs MOVSB)>;1580def LNLPWriteResGroupX151 : SchedWriteRes<[LNLPVPort00_01_02_03]>;1581def : InstRW<[LNLPWriteResGroupX151], (instrs VPBLENDDrri)>;1582def LNLPWriteResGroupX152 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1583 let ReleaseAtCycles = [4, 1, 1, 1];1584 let Latency = 7;1585 let NumMicroOps = 7;1586}1587def : InstRW<[LNLPWriteResGroupX152], (instregex "^MOVS(L|Q|W)$")>;1588def LNLPWriteResGroupX153 : SchedWriteRes<[LNLPPort20_21_22]> {1589 let Latency = 6;1590}1591def : InstRW<[LNLPWriteResGroupX153], (instregex "^MOVSX(16|32|64)rm(16|32)$",1592 "^MOVSX(32|64)rm8$")>;1593def : InstRW<[LNLPWriteResGroupX153], (instrs MOVSX32rm8_NOREX)>;1594def LNLPWriteResGroupX154 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {1595 let Latency = 6;1596 let NumMicroOps = 2;1597}1598def : InstRW<[LNLPWriteResGroupX154], (instrs MOVSX16rm8)>;1599def LNLPWriteResGroupX156 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03]> {1600 let Latency = 11;1601 let NumMicroOps = 2;1602}1603def : InstRW<[LNLPWriteResGroupX156], (instregex "^MUL_F(32|64)m$")>;1604def LNLPWriteResGroupX157 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort01_03_05]> {1605 let Latency = 14;1606 let NumMicroOps = 3;1607}1608def : InstRW<[LNLPWriteResGroupX157], (instregex "^MUL_FI(16|32)m$")>;1609def LNLPWriteResGroupX158 : SchedWriteRes<[LNLPVPort00_01_02_03]> {1610 let Latency = 4;1611}1612def : InstRW<[LNLPWriteResGroupX158], (instregex "^MUL_F(P?)rST0$")>;1613def : InstRW<[LNLPWriteResGroupX158], (instrs MUL_FST0r)>;1614def LNLPWriteResGroupX155 : SchedWriteRes<[LNLPPort01_03_05]>;1615def : InstRW<[LNLPWriteResGroupX155], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;1616def : InstRW<[LNLPWriteResGroupX155], (instrs MOVSX32rr8_NOREX)>;1617def LNLPWriteResGroupX173 : SchedWriteRes<[LNLPPort01_03_05]>;1618def : InstRW<[LNLPWriteResGroupX173], (instregex "^(V?)PALIGNRrri$",1619 "^VPBROADCAST(B|D|Q|W)rr$")>;1620def : InstRW<[LNLPWriteResGroupX173], (instrs VPALIGNRYrri)>;1621def LNLPWriteResGroupX176 : SchedWriteRes<[LNLPVPort02_03, LNLPPort10_11, LNLPPort25_26_27]> {1622 let Latency = 12;1623 let NumMicroOps = 3;1624}1625def : InstRW<[LNLPWriteResGroupX176], (instregex "^(V?)PEXTR(D|Q)mri$")>;1626def LNLPWriteResGroupX179 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1627 let Latency = 12;1628 let NumMicroOps = 3;1629}1630def : InstRW<[LNLPWriteResGroupX179], (instregex "^POP(16|32|64)rmm$",1631 "^PUSH(16|32)rmm$")>;1632def LNLPWriteResGroupX180 : SchedWriteRes<[LNLPPort20_21_22]> {1633 let Latency = 5;1634}1635def : InstRW<[LNLPWriteResGroupX180], (instregex "^POPA(16|32)$",1636 "^PREFETCHIT(0|1)$")>;1637def : InstRW<[LNLPWriteResGroupX180], (instrs POPF32)>;1638def LNLPWriteResGroupX181 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22]> {1639 let ReleaseAtCycles = [6, 2, 1, 1];1640 let Latency = 5;1641 let NumMicroOps = 10;1642}1643def : InstRW<[LNLPWriteResGroupX181], (instrs POPF16)>;1644def LNLPWriteResGroupX182 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22]> {1645 let ReleaseAtCycles = [2, 1, 1];1646 let Latency = 5;1647 let NumMicroOps = 7;1648}1649def : InstRW<[LNLPWriteResGroupX182], (instrs POPF64)>;1650def LNLPWriteResGroupX183 : SchedWriteRes<[LNLPPort20_21_22]> {1651 let Latency = 0;1652}1653def : InstRW<[LNLPWriteResGroupX183], (instregex "^PREFETCHT(0|1|2)$")>;1654def : InstRW<[LNLPWriteResGroupX183], (instrs PREFETCHNTA)>;1655def LNLPWriteResGroupX187 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1656 let NumMicroOps = 2;1657}1658def : InstRW<[LNLPWriteResGroupX187], (instregex "^PUSH64r((mr)?)$")>;1659def LNLPWriteResGroupX188 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1660 let NumMicroOps = 3;1661}1662def : InstRW<[LNLPWriteResGroupX188], (instrs PUSH64rmm)>;1663def LNLPWriteResGroupX189 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11]>;1664def : InstRW<[LNLPWriteResGroupX189], (instregex "^PUSHA(16|32)$",1665 "^ST_F(32|64)m$")>;1666def : InstRW<[LNLPWriteResGroupX189], (instrs PUSHF32)>;1667def LNLPWriteResGroupX190 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1668 let Latency = 4;1669 let NumMicroOps = 4;1670}1671def : InstRW<[LNLPWriteResGroupX190], (instrs PUSHF64)>;1672def LNLPWriteResGroupX191 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1673 let NumMicroOps = 3;1674}1675def : InstRW<[LNLPWriteResGroupX191], (instregex "^PUSH(F|G)S64$")>;1676def LNLPWriteResGroupX192 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1677 let ReleaseAtCycles = [2, 3, 2];1678 let Latency = 8;1679 let NumMicroOps = 7;1680}1681def : InstRW<[LNLPWriteResGroupX192], (instregex "^RC(L|R)(16|32|64)rCL$")>;1682def LNLPWriteResGroupX193 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1683 let ReleaseAtCycles = [1, 2];1684 let Latency = 13;1685 let NumMicroOps = 3;1686}1687def : InstRW<[LNLPWriteResGroupX193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;1688def LNLPWriteResGroupX194 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1689 let ReleaseAtCycles = [1, 5, 2];1690 let Latency = 20;1691 let NumMicroOps = 8;1692}1693def : InstRW<[LNLPWriteResGroupX194, WriteRMW], (instrs RCL8mCL)>;1694def LNLPWriteResGroupX195 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1695 let ReleaseAtCycles = [2, 5, 2];1696 let Latency = 7;1697 let NumMicroOps = 9;1698}1699def : InstRW<[LNLPWriteResGroupX195], (instrs RCL8rCL)>;1700def LNLPWriteResGroupX196 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1701 let ReleaseAtCycles = [2, 4, 3];1702 let Latency = 20;1703 let NumMicroOps = 9;1704}1705def : InstRW<[LNLPWriteResGroupX196, WriteRMW], (instrs RCR8mCL)>;1706def LNLPWriteResGroupX197 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1707 let ReleaseAtCycles = [3, 4, 3];1708 let Latency = 9;1709 let NumMicroOps = 10;1710}1711def : InstRW<[LNLPWriteResGroupX197], (instrs RCR8rCL)>;1712def LNLPWriteResGroupX206 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {1713 let ReleaseAtCycles = [5, 6, 3, 1];1714 let Latency = 18;1715 let NumMicroOps = 15;1716}1717def : InstRW<[LNLPWriteResGroupX206], (instrs RDTSC)>;1718def LNLPWriteResGroupX208 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {1719 let Latency = 7;1720 let NumMicroOps = 2;1721}1722def : InstRW<[LNLPWriteResGroupX208], (instrs RET64)>;1723def LNLPWriteResGroupX209 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {1724 let ReleaseAtCycles = [2, 1];1725 let Latency = 6;1726 let NumMicroOps = 3;1727}1728def : InstRW<[LNLPWriteResGroupX209], (instregex "^RETI(16|32|64)$")>;1729def LNLPWriteResGroupX210 : SchedWriteRes<[]>;1730def : InstRW<[LNLPWriteResGroupX210], (instrs REX64_PREFIX)>;1731def LNLPWriteResGroupX211 : SchedWriteRes<[LNLPPort00_02_04]> {1732 let ReleaseAtCycles = [2];1733 let Latency = 12;1734 let NumMicroOps = 2;1735}1736def : InstRW<[LNLPWriteResGroupX211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;1737def LNLPWriteResGroupX212 : SchedWriteRes<[LNLPPort00_02_04]> {1738 let ReleaseAtCycles = [2];1739 let NumMicroOps = 2;1740}1741def : InstRW<[LNLPWriteResGroupX212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;1742def LNLPWriteResGroupX213 : SchedWriteRes<[LNLPPort00_02_04]> {1743 let ReleaseAtCycles = [2];1744 let Latency = 13;1745 let NumMicroOps = 2;1746}1747def : InstRW<[LNLPWriteResGroupX213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",1748 "^(RO|SH)L8mCL$",1749 "^(RO|SA|SH)R8mCL$")>;1750def LNLPWriteResGroupX214 : SchedWriteRes<[LNLPPort00_02_04]> {1751 let ReleaseAtCycles = [2];1752 let Latency = 4;1753 let NumMicroOps = 2;1754}1755def : InstRW<[LNLPWriteResGroupX214], (instrs SAHF)>;1756def LNLPWriteResGroupX215 : SchedWriteRes<[LNLPPort00_02_04]> {1757 let Latency = 13;1758}1759def : InstRW<[LNLPWriteResGroupX215, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",1760 "^SHL8m(1|i)$")>;1761def LNLPWriteResGroupX216 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {1762 let Latency = 8;1763 let NumMicroOps = 2;1764}1765def : InstRW<[LNLPWriteResGroupX216, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",1766 "^SHLX(32|64)rm$")>;1767def LNLPWriteResGroupX217 : SchedWriteRes<[LNLPPort00_02_04]> {1768 let Latency = 3;1769}1770def : InstRW<[LNLPWriteResGroupX217], (instregex "^S(A|H)RX(32|64)rr$",1771 "^SHLX(32|64)rr$")>;1772def LNLPWriteResGroupX218 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1773 let ReleaseAtCycles = [2, 2, 1, 1, 1];1774 let Latency = LunarlakePModel.MaxLatency;1775 let NumMicroOps = 7;1776}1777def : InstRW<[LNLPWriteResGroupX218], (instrs SERIALIZE)>;1778def LNLPWriteResGroupX219 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1779 let Latency = 2;1780 let NumMicroOps = 2;1781}1782def : InstRW<[LNLPWriteResGroupX219], (instrs SFENCE)>;1783def LNLPWriteResGroupX220 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {1784 let ReleaseAtCycles = [1, 2, 2, 2];1785 let Latency = 21;1786 let NumMicroOps = 7;1787}1788def : InstRW<[LNLPWriteResGroupX220], (instregex "^S(G|I)DT64m$")>;1789def LNLPWriteResGroupX223 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22]> {1790 let ReleaseAtCycles = [2, 2, 1, 2, 1];1791 let Latency = 13;1792 let NumMicroOps = 8;1793}1794def : InstRW<[LNLPWriteResGroupX223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;1795def LNLPWriteResGroupX224 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03]> {1796 let ReleaseAtCycles = [2, 2, 1, 2];1797 let Latency = 6;1798 let NumMicroOps = 7;1799}1800def : InstRW<[LNLPWriteResGroupX224], (instrs SHA1MSG2rr)>;1801def LNLPWriteResGroupX233 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {1802 let Latency = 13;1803 let NumMicroOps = 5;1804}1805def : InstRW<[LNLPWriteResGroupX233], (instrs SHRD16mri8)>;1806def LNLPWriteResGroupX234 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1807 let Latency = 6;1808 let NumMicroOps = 2;1809}1810def : InstRW<[LNLPWriteResGroupX234], (instregex "^SLDT(32|64)r$")>;1811def LNLPWriteResGroupX235 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1812 let NumMicroOps = 2;1813}1814def : InstRW<[LNLPWriteResGroupX235], (instrs SMSW16r)>;1815def LNLPWriteResGroupX236 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1816 let Latency = LunarlakePModel.MaxLatency;1817 let NumMicroOps = 2;1818}1819def : InstRW<[LNLPWriteResGroupX236], (instregex "^SMSW(32|64)r$")>;1820def LNLPWriteResGroupX237 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22]> {1821 let Latency = 24;1822 let NumMicroOps = 2;1823}1824def : InstRW<[LNLPWriteResGroupX237, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;1825def LNLPWriteResGroupX238 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1826 let Latency = 6;1827 let NumMicroOps = 2;1828}1829def : InstRW<[LNLPWriteResGroupX238], (instrs STD)>;1830def LNLPWriteResGroupX239 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {1831 let ReleaseAtCycles = [1, 4, 1];1832 let Latency = LunarlakePModel.MaxLatency;1833 let NumMicroOps = 6;1834}1835def : InstRW<[LNLPWriteResGroupX239], (instrs STI)>;1836def LNLPWriteResGroupX240 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1837 let ReleaseAtCycles = [2, 1, 1];1838 let Latency = 8;1839 let NumMicroOps = 4;1840}1841def : InstRW<[LNLPWriteResGroupX240], (instrs STOSB)>;1842def LNLPWriteResGroupX241 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {1843 let ReleaseAtCycles = [2, 1, 1];1844 let Latency = 7;1845 let NumMicroOps = 4;1846}1847def : InstRW<[LNLPWriteResGroupX241], (instregex "^STOS(L|Q|W)$")>;1848def LNLPWriteResGroupX242 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {1849 let Latency = 5;1850 let NumMicroOps = 2;1851}1852def : InstRW<[LNLPWriteResGroupX242], (instregex "^STR(32|64)r$")>;1853def LNLPWriteResGroupX243 : SchedWriteRes<[LNLPPort01_03_05]> {1854 let Latency = 2;1855}1856def : InstRW<[LNLPWriteResGroupX243], (instregex "^(TST|XAM)_F$")>;1857def : InstRW<[LNLPWriteResGroupX243], (instrs UCOM_FPPr)>;1858def LNLPWriteResGroupX244 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {1859 let ReleaseAtCycles = [3, 1];1860 let Latency = 9;1861 let NumMicroOps = 4;1862}1863def : InstRW<[LNLPWriteResGroupX244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;1864def : InstRW<[LNLPWriteResGroupX244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;1865def LNLPWriteResGroupX245 : SchedWriteRes<[LNLPPort01_03_05]> {1866 let ReleaseAtCycles = [3];1867 let Latency = 3;1868 let NumMicroOps = 3;1869}1870def : InstRW<[LNLPWriteResGroupX245], (instregex "^VBLENDVP(D|S)rrr$")>;1871def : InstRW<[LNLPWriteResGroupX245], (instrs VPBLENDVBrrr)>;1872def LNLPWriteResGroupX250 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {1873 let ReleaseAtCycles = [1, 1, 2, 4];1874 let Latency = 29;1875 let NumMicroOps = 8;1876}1877def : InstRW<[LNLPWriteResGroupX250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",1878 "^VPGATHER(D|Q)QYrm$")>;1879def : InstRW<[LNLPWriteResGroupX250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,1880 VPGATHERQDYrm)>;1881def LNLPWriteResGroupX251 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {1882 let ReleaseAtCycles = [1, 1, 1, 2];1883 let Latency = 20;1884 let NumMicroOps = 5;1885}1886def : InstRW<[LNLPWriteResGroupX251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",1887 "^VPGATHER(D|Q)Qrm$")>;1888def : InstRW<[LNLPWriteResGroupX251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,1889 VPGATHERQDrm)>;1890def LNLPWriteResGroupX252 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {1891 let ReleaseAtCycles = [1, 1, 2, 8];1892 let Latency = 30;1893 let NumMicroOps = 12;1894}1895def : InstRW<[LNLPWriteResGroupX252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,1896 VPGATHERDDYrm)>;1897def LNLPWriteResGroupX253 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {1898 let ReleaseAtCycles = [1, 1, 2, 4];1899 let Latency = 28;1900 let NumMicroOps = 8;1901}1902def : InstRW<[LNLPWriteResGroupX253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,1903 VPGATHERDDrm)>;1904def LNLPWriteResGroupX254 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05]> {1905 let ReleaseAtCycles = [1, 2];1906 let Latency = 5;1907 let NumMicroOps = 3;1908}1909def : InstRW<[LNLPWriteResGroupX254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;1910def LNLPWriteResGroupX256 : SchedWriteRes<[LNLPVPort00_01, LNLPPort00_02_04, LNLPPort20_21_22]> {1911 let Latency = 7;1912 let NumMicroOps = 3;1913}1914def : InstRW<[LNLPWriteResGroupX256], (instrs VLDMXCSR)>;1915def LNLPWriteResGroupX257 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort00_02_04]> {1916 let ReleaseAtCycles = [8, 1, 1, 1, 1, 1, 2, 3];1917 let Latency = 40;1918 let NumMicroOps = 18;1919}1920def : InstRW<[LNLPWriteResGroupX257], (instrs VMCLEARm)>;1921def LNLPWriteResGroupX259 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1922 let Latency = 521;1923 let NumMicroOps = 2;1924}1925def : InstRW<[LNLPWriteResGroupX259], (instrs VMOVNTDQmr)>;1926def LNLPWriteResGroupX260 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1927 let Latency = 473;1928 let NumMicroOps = 2;1929}1930def : InstRW<[LNLPWriteResGroupX260], (instrs VMOVNTPDmr)>;1931def LNLPWriteResGroupX261 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1932 let Latency = 494;1933 let NumMicroOps = 2;1934}1935def : InstRW<[LNLPWriteResGroupX261], (instrs VMOVNTPSYmr)>;1936def LNLPWriteResGroupX262 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {1937 let Latency = 470;1938 let NumMicroOps = 2;1939}1940def : InstRW<[LNLPWriteResGroupX262], (instrs VMOVNTPSmr)>;1941def LNLPWriteResGroupX264 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {1942 let Latency = 9;1943 let NumMicroOps = 2;1944}1945def : InstRW<[LNLPWriteResGroupX264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;1946def LNLPWriteResGroupX267 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {1947 let ReleaseAtCycles = [1, 2, 3, 3, 1];1948 let Latency = 16;1949 let NumMicroOps = 10;1950}1951def : InstRW<[LNLPWriteResGroupX267], (instrs VZEROALL)>;1952def LNLPWriteResGroupX268 : SchedWriteRes<[LNLPVPort00_01_02_03]> {1953 let ReleaseAtCycles = [2];1954 let Latency = 2;1955 let NumMicroOps = 2;1956}1957def : InstRW<[LNLPWriteResGroupX268], (instrs WAIT)>;1958def LNLPWriteResGroupX269 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {1959 let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];1960 let Latency = LunarlakePModel.MaxLatency;1961 let NumMicroOps = 144;1962}1963def : InstRW<[LNLPWriteResGroupX269], (instrs WRMSR)>;1964def LNLPWriteResGroupX270 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {1965 let ReleaseAtCycles = [2, 1, 4, 1];1966 let Latency = LunarlakePModel.MaxLatency;1967 let NumMicroOps = 8;1968}1969def : InstRW<[LNLPWriteResGroupX270], (instrs WRPKRUr)>;1970def LNLPWriteResGroupX271 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {1971 let ReleaseAtCycles = [2];1972 let Latency = 12;1973 let NumMicroOps = 2;1974}1975def : InstRW<[LNLPWriteResGroupX271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;1976def LNLPWriteResGroupX272 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {1977 let ReleaseAtCycles = [2];1978 let Latency = 13;1979 let NumMicroOps = 2;1980}1981def : InstRW<[LNLPWriteResGroupX272, WriteRMW], (instrs XADD8rm)>;1982def LNLPWriteResGroupX273 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1983 let ReleaseAtCycles = [4, 1];1984 let Latency = 39;1985 let NumMicroOps = 5;1986}1987def : InstRW<[LNLPWriteResGroupX273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;1988def LNLPWriteResGroupX274 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1989 let ReleaseAtCycles = [5, 1];1990 let Latency = 39;1991 let NumMicroOps = 6;1992}1993def : InstRW<[LNLPWriteResGroupX274, WriteRMW], (instrs XCHG64rm)>;1994def LNLPWriteResGroupX275 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {1995 let ReleaseAtCycles = [4, 1];1996 let Latency = 40;1997 let NumMicroOps = 5;1998}1999def : InstRW<[LNLPWriteResGroupX275, WriteRMW], (instrs XCHG8rm)>;2000def LNLPWriteResGroupX276 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort00_02_04]> {2001 let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];2002 let Latency = 17;2003 let NumMicroOps = 15;2004}2005def : InstRW<[LNLPWriteResGroupX276], (instrs XCH_F)>;2006def LNLPWriteResGroupX277 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05]> {2007 let ReleaseAtCycles = [7, 3, 8, 5];2008 let Latency = 4;2009 let NumMicroOps = 23;2010}2011def : InstRW<[LNLPWriteResGroupX277], (instrs XGETBV)>;2012def LNLPWriteResGroupX278 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {2013 let ReleaseAtCycles = [2, 1];2014 let Latency = 7;2015 let NumMicroOps = 3;2016}2017def : InstRW<[LNLPWriteResGroupX278], (instrs XLAT)>;2018def LNLPWriteResGroupX279 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort00_02_04]> {2019 let ReleaseAtCycles = [21, 1, 1, 8];2020 let Latency = 37;2021 let NumMicroOps = 31;2022}2023def : InstRW<[LNLPWriteResGroupX279], (instregex "^XRSTOR((S|64)?)$")>;2024def : InstRW<[LNLPWriteResGroupX279], (instrs XRSTORS64)>;2025def LNLPWriteResGroupX280 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2026 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];2027 let Latency = 42;2028 let NumMicroOps = 140;2029}2030def : InstRW<[LNLPWriteResGroupX280], (instrs XSAVE)>;2031def LNLPWriteResGroupX281 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2032 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];2033 let Latency = 41;2034 let NumMicroOps = 140;2035}2036def : InstRW<[LNLPWriteResGroupX281], (instrs XSAVE64)>;2037def LNLPWriteResGroupX282 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2038 let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];2039 let Latency = 42;2040 let NumMicroOps = 151;2041}2042def : InstRW<[LNLPWriteResGroupX282], (instrs XSAVEC)>;2043def LNLPWriteResGroupX283 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2044 let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];2045 let Latency = 42;2046 let NumMicroOps = 152;2047}2048def : InstRW<[LNLPWriteResGroupX283], (instrs XSAVEC64)>;2049def LNLPWriteResGroupX284 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2050 let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];2051 let Latency = 46;2052 let NumMicroOps = 155;2053}2054def : InstRW<[LNLPWriteResGroupX284], (instrs XSAVEOPT)>;2055def LNLPWriteResGroupX285 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2056 let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];2057 let Latency = 46;2058 let NumMicroOps = 156;2059}2060def : InstRW<[LNLPWriteResGroupX285], (instrs XSAVEOPT64)>;2061def LNLPWriteResGroupX286 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2062 let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];2063 let Latency = 42;2064 let NumMicroOps = 184;2065}2066def : InstRW<[LNLPWriteResGroupX286], (instrs XSAVES)>;2067def LNLPWriteResGroupX287 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {2068 let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];2069 let Latency = 42;2070 let NumMicroOps = 186;2071}2072def : InstRW<[LNLPWriteResGroupX287], (instrs XSAVES64)>;2073def LNLPWriteResGroupX288 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort00_01_02_03_04_05, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort01_03_05]> {2074 let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];2075 let Latency = 5;2076 let NumMicroOps = 54;2077}2078def : InstRW<[LNLPWriteResGroupX288], (instrs XSETBV)>;2079 2080// SchedWriteRes and InstRW definition2081// Following defs are based on data shared by arch team2082def LNLPWriteResGroup0 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2083 let ReleaseAtCycles = [4, 6];2084 let Latency = 10;2085 let NumMicroOps = 2;2086}2087def : InstRW<[LNLPWriteResGroup0, ReadAfterVecXLd], (instregex "^(V?)CMPP(D|S)rmi$",2088 "^GF2P8AFFINE((INV)?)QBrmi$")>;2089def : InstRW<[LNLPWriteResGroup0, ReadAfterVecXLd], (instrs GF2P8MULBrm)>;2090def : InstRW<[LNLPWriteResGroup0, ReadAfterVecLd], (instregex "^(V?)CMPS(D|S)rmi((_Int)?)$")>;2091def LNLPWriteResGroup1 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {2092 let ReleaseAtCycles = [4, 1, 6];2093 let Latency = 11;2094 let NumMicroOps = 2;2095}2096def LNLPWriteResGroup2 : SchedWriteRes<[LNLPPort01_03_05, LNLPVPort00_01, LNLPVPort02_03]> {2097 let ReleaseAtCycles = [4, 4, 1];2098 let Latency = 9;2099 let NumMicroOps = 3;2100}2101def : InstRW<[LNLPWriteResGroup2, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;2102def LNLPWriteResGroup3 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2103 let ReleaseAtCycles = [7, 4];2104 let Latency = 11;2105 let NumMicroOps = 3;2106}2107def : InstRW<[LNLPWriteResGroup3], (instregex "^CVT(T?)SS2SI((64)?)rm_Int$",2108 "^CVT(T?)SS2SIrm$",2109 "^VCVTTSD2SI((64)?)rm_Int$")>;2110def LNLPWriteResGroup4 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {2111 let ReleaseAtCycles = [7, 1];2112 let Latency = 8;2113 let NumMicroOps = 3;2114}2115def : InstRW<[LNLPWriteResGroup4], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;2116def LNLPWriteResGroup5 : SchedWriteRes<[LNLPVPort00_01]> {2117 let ReleaseAtCycles = [4];2118 let Latency = 3;2119}2120def : InstRW<[LNLPWriteResGroup5], (instregex "^GF2P8AFFINE((INV)?)QBrri$")>;2121def : InstRW<[LNLPWriteResGroup5], (instrs GF2P8MULBrr)>;2122def LNLPWriteResGroup6 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {2123 let ReleaseAtCycles = [4, 1, 8];2124 let Latency = 13;2125 let NumMicroOps = 3;2126}2127def : InstRW<[LNLPWriteResGroup6], (instregex "^MMX_CVT(T?)PD2PIrm$")>;2128def LNLPWriteResGroup7 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {2129 let ReleaseAtCycles = [4, 1];2130 let Latency = LunarlakePModel.MaxLatency;2131 let NumMicroOps = 2;2132}2133def : InstRW<[LNLPWriteResGroup7], (instregex "^MMX_CVT(T?)PD2PIrr$")>;2134def : InstRW<[LNLPWriteResGroup7], (instrs MMX_CVTPI2PDrr)>;2135def LNLPWriteResGroup8 : SchedWriteRes<[LNLPVPort00_01]> {2136 let ReleaseAtCycles = [5];2137 let Latency = LunarlakePModel.MaxLatency;2138 let NumMicroOps = 2;2139}2140def : InstRW<[LNLPWriteResGroup8], (instrs MMX_CVTPI2PSrr)>;2141def LNLPWriteResGroup9 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2142 let ReleaseAtCycles = [4, 8];2143 let Latency = 13;2144 let NumMicroOps = 2;2145}2146def : InstRW<[LNLPWriteResGroup9], (instregex "^MMX_CVT(T?)PS2PIrm$")>;2147def LNLPWriteResGroup10 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {2148 let ReleaseAtCycles = [4, 1];2149 let Latency = LunarlakePModel.MaxLatency;2150 let NumMicroOps = 2;2151}2152def : InstRW<[LNLPWriteResGroup10], (instrs MMX_CVTPS2PIrr)>;2153def LNLPWriteResGroup11 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {2154 let ReleaseAtCycles = [4, 1];2155 let Latency = 5;2156 let NumMicroOps = 2;2157}2158def : InstRW<[LNLPWriteResGroup11], (instrs MMX_CVTTPS2PIrr)>;2159def LNLPWriteResGroup12 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {2160 let Latency = 3;2161 let NumMicroOps = 2;2162}2163def : InstRW<[LNLPWriteResGroup12], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;2164def LNLPWriteResGroup13 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {2165 let ReleaseAtCycles = [2, 4];2166 let Latency = LunarlakePModel.MaxLatency;2167 let NumMicroOps = 3;2168}2169def : InstRW<[LNLPWriteResGroup13], (instregex "^MOVBE(16|32|64)rm$")>;2170def LNLPWriteResGroup14 : SchedWriteRes<[LNLPPort20_21_22]> {2171 let ReleaseAtCycles = [6];2172 let Latency = 6;2173}2174def : InstRW<[LNLPWriteResGroup14], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",2175 "^VPBROADCAST(D|Q|W)rm$")>;2176def : InstRW<[LNLPWriteResGroup14], (instrs VBROADCASTSSrm)>;2177def LNLPWriteResGroup15 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {2178 let Latency = LunarlakePModel.MaxLatency;2179 let NumMicroOps = 2;2180}2181def : InstRW<[LNLPWriteResGroup15], (instregex "^MOVDIRI(32|64)$")>;2182def LNLPWriteResGroup16 : SchedWriteRes<[LNLPVPort00_01_02_03]>;2183def : InstRW<[LNLPWriteResGroup16], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",2184 "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",2185 "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;2186def LNLPWriteResGroup17 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2187 let ReleaseAtCycles = [3, 6];2188 let Latency = 9; // originally 102189}2190def : InstRW<[LNLPWriteResGroup17, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",2191 "^(V?)PCMPGTQrm$")>;2192def LNLPWriteResGroup18 : SchedWriteRes<[LNLPVPort02_03]> {2193 let ReleaseAtCycles = [3];2194 let Latency = 3;2195}2196def : InstRW<[LNLPWriteResGroup18], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",2197 "^(V?)PACKUSWBrr$",2198 "^(V?)PCMPGTQrr$",2199 "^VPACK(S|U)S(DW|WB)Yrr$",2200 "^VSHA512MSG(1|2)rr$")>;2201def : InstRW<[LNLPWriteResGroup18], (instrs VPCMPGTQYrr)>;2202def LNLPWriteResGroup19 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {2203 let ReleaseAtCycles = [1, 6];2204 let Latency = 7;2205}2206def : InstRW<[LNLPWriteResGroup19, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;2207def : InstRW<[LNLPWriteResGroup19, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;2208def LNLPWriteResGroup20 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2209 let ReleaseAtCycles = [1, 6];2210 let Latency = 7;2211 let NumMicroOps = 2;2212}2213def : InstRW<[LNLPWriteResGroup20], (instregex "^(V?)PSHUF(D|HW|LW)mi$",2214 "^VPERMILP(D|S)mi$")>;2215def : InstRW<[LNLPWriteResGroup20, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$",2216 "^(V?)SHUFP(D|S)rmi$")>;2217def : InstRW<[LNLPWriteResGroup20, ReadAfterVecXLd], (instrs VINSERTPSrmi,2218 VPBLENDWrmi)>;2219def LNLPWriteResGroup21 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {2220 let ReleaseAtCycles = [3, 4];2221 let Latency = 7;2222}2223def : InstRW<[LNLPWriteResGroup21, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;2224def LNLPWriteResGroup22 : SchedWriteRes<[LNLPPort01_03_05]> {2225 let ReleaseAtCycles = [3];2226 let Latency = 3;2227}2228def : InstRW<[LNLPWriteResGroup22], (instregex "^P(DEP|EXT)(32|64)rr$")>;2229def LNLPWriteResGroup23 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {2230 let ReleaseAtCycles = [1, 2, 1];2231 let Latency = 9; // originally LunarlakePModel.MaxLatency;2232 let NumMicroOps = 4;2233}2234def : InstRW<[LNLPWriteResGroup23, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;2235def LNLPWriteResGroup24 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {2236 let ReleaseAtCycles = [1, 2];2237 let Latency = 2;2238 let NumMicroOps = 3;2239}2240def : InstRW<[LNLPWriteResGroup24], (instregex "^(V?)PH(ADD|SUB)SWrr$",2241 "^VPH(ADD|SUB)SWYrr$")>;2242def LNLPWriteResGroup25 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2243 let ReleaseAtCycles = [3, 6];2244 let Latency = 9;2245}2246def : InstRW<[LNLPWriteResGroup25, ReadAfterVecXLd], (instregex "^(V?)PMULUDQrm$")>;2247def : InstRW<[LNLPWriteResGroup25, ReadAfterVecXLd], (instrs VPMULDQrm)>;2248def LNLPWriteResGroup26 : SchedWriteRes<[LNLPVPort00_01]> {2249 let ReleaseAtCycles = [3];2250 let Latency = 3;2251}2252def : InstRW<[LNLPWriteResGroup26], (instregex "^(V?)PMULUDQrr$",2253 "^VPMUL(U?)DQYrr$")>;2254def : InstRW<[LNLPWriteResGroup26], (instrs VMOVSDto64Zrr,2255 VPMULDQrr)>;2256 2257def LNLPWriteResGroup27 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort20_21_22]> {2258 let ReleaseAtCycles = [1, 1, 6];2259 let Latency = 8;2260 let NumMicroOps = 3;2261}2262def : InstRW<[LNLPWriteResGroup27, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;2263def LNLPWriteResGroup28 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03]> {2264 let Latency = 2;2265 let NumMicroOps = 2;2266}2267def : InstRW<[LNLPWriteResGroup28], (instrs SHA1MSG1rr)>;2268def LNLPWriteResGroup29 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort20_21_22]> {2269 let ReleaseAtCycles = [1, 1, 1, 6];2270 let Latency = 7; // Originally 82271 let NumMicroOps = 4;2272}2273def : InstRW<[LNLPWriteResGroup29, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;2274def LNLPWriteResGroup30 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03]> {2275 let Latency = 3; // originally LunarlakePModel.MaxLatency;2276 let NumMicroOps = 3;2277}2278def : InstRW<[LNLPWriteResGroup30], (instrs SHA1NEXTErr)>;2279def LNLPWriteResGroup31 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2280 let ReleaseAtCycles = [3, 6];2281 let Latency = LunarlakePModel.MaxLatency;2282 let NumMicroOps = 2;2283}2284def : InstRW<[LNLPWriteResGroup31, ReadAfterVecXLd], (instrs SHA1RNDS4rmi)>;2285def LNLPWriteResGroup32 : SchedWriteRes<[LNLPVPort02_03]> {2286 let ReleaseAtCycles = [3];2287 let Latency = 2;2288}2289def : InstRW<[LNLPWriteResGroup32], (instrs SHA1RNDS4rri,2290 SHA256RNDS2rr)>;2291def LNLPWriteResGroup33 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2292 let ReleaseAtCycles = [3, 6];2293 let Latency = 12 ; // orignally 99; diff lat for 1 & 2 version2294}2295def : InstRW<[LNLPWriteResGroup33, ReadAfterVecXLd], (instregex "^SHA256MSG(1|2)rm$")>;2296 2297def LNLPWriteResGroup34 : SchedWriteRes<[LNLPVPort00_01]> {2298 let ReleaseAtCycles = [3];2299 let Latency = 5; // orignally 99; Diff lat for 1 & 2 version2300}2301def : InstRW<[LNLPWriteResGroup34], (instregex "^SHA256MSG(1|2)rr$")>;2302def LNLPWriteResGroup35 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2303 let ReleaseAtCycles = [3, 6];2304 let Latency = 9;2305 let NumMicroOps = 2;2306}2307def : InstRW<[LNLPWriteResGroup35, ReadAfterVecXLd], (instrs SHA256RNDS2rm)>;2308def LNLPWriteResGroup36 : SchedWriteRes<[LNLPPort20_21_22]> {2309 let ReleaseAtCycles = [7];2310 let Latency = 7;2311}2312def : InstRW<[LNLPWriteResGroup36], (instregex "^VBROADCASTS(D|S)Yrm$",2313 "^VMOV(D|SH|SL)DUPYrm$",2314 "^VPBROADCAST(D|Q|W)Yrm$")>;2315def : InstRW<[LNLPWriteResGroup36], (instrs VBROADCASTF128rm)>;2316def LNLPWriteResGroup37 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2317 let ReleaseAtCycles = [4, 7];2318 let Latency = 11;2319 let NumMicroOps = 2;2320}2321def : InstRW<[LNLPWriteResGroup37, ReadAfterVecYLd], (instregex "^VCMPP(D|S)Yrmi$")>;2322def LNLPWriteResGroup38 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2323 let ReleaseAtCycles = [4, 6];2324 let Latency = 10;2325}2326def : InstRW<[LNLPWriteResGroup38], (instregex "^VCVT(T?)PS2DQrm$")>;2327def LNLPWriteResGroup39 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {2328 let ReleaseAtCycles = [4, 1, 6];2329 let Latency = 11;2330 let NumMicroOps = 3;2331}2332def : InstRW<[LNLPWriteResGroup39, ReadAfterVecLd], (instrs VCVTSI642SSrm_Int)>;2333def LNLPWriteResGroup40 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {2334 let NumMicroOps = 2;2335}2336def : InstRW<[LNLPWriteResGroup40], (instregex "^VEXTRACT(F|I)128mri$")>;2337def LNLPWriteResGroup41 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {2338 let ReleaseAtCycles = [1, 7];2339 let Latency = 8;2340 let NumMicroOps = 2;2341}2342def : InstRW<[LNLPWriteResGroup41, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$")>;2343def LNLPWriteResGroup42 : SchedWriteRes<[LNLPVPort00_01]> {2344 let ReleaseAtCycles = [3];2345 let Latency = 4;2346}2347def : InstRW<[LNLPWriteResGroup42], (instregex "^VMOVMSKP(D|S)Yrr$")>;2348def LNLPWriteResGroup43 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2349 let ReleaseAtCycles = [3, 7];2350 let Latency = 10;2351}2352def : InstRW<[LNLPWriteResGroup43, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;2353def : InstRW<[LNLPWriteResGroup43, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;2354def LNLPWriteResGroup44 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {2355 let ReleaseAtCycles = [1, 7];2356 let Latency = 8;2357}2358def : InstRW<[LNLPWriteResGroup44, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;2359def LNLPWriteResGroup45 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2360 let ReleaseAtCycles = [1, 7];2361 let Latency = 8;2362 let NumMicroOps = 2;2363}2364def : InstRW<[LNLPWriteResGroup45], (instregex "^VPSHUF(D|HW|LW)Ymi$")>;2365def : InstRW<[LNLPWriteResGroup45, ReadAfterVecYLd], (instrs VPALIGNRYrmi,2366 VPBLENDWYrmi)>;2367def LNLPWriteResGroup46 : SchedWriteRes<[LNLPVPort02_03]>;2368def : InstRW<[LNLPWriteResGroup46], (instregex "^VPBLENDW(Y?)rri$")>;2369def LNLPWriteResGroup47 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2370 let ReleaseAtCycles = [1, 7];2371 let Latency = 8;2372}2373def : InstRW<[LNLPWriteResGroup47], (instrs VPBROADCASTBYrm)>;2374def : InstRW<[LNLPWriteResGroup47, ReadAfterVecYLd], (instregex "^VUNPCK(H|L)P(D|S)Yrm$")>;2375def LNLPWriteResGroup48 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {2376 let ReleaseAtCycles = [3, 7];2377 let Latency = 10;2378 let NumMicroOps = 2;2379}2380def : InstRW<[LNLPWriteResGroup48, ReadAfterVecXLd], (instrs VPCLMULQDQYrmi)>;2381def LNLPWriteResGroup49 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {2382 let ReleaseAtCycles = [1, 2, 7];2383 let Latency = 9;2384 let NumMicroOps = 4;2385}2386def : InstRW<[LNLPWriteResGroup49, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;2387def LNLPWriteResGroup50 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2388 let ReleaseAtCycles = [3, 7];2389 let Latency = 10;2390}2391def : InstRW<[LNLPWriteResGroup50, ReadAfterVecYLd], (instregex "^VPMUL(U?)DQYrm$")>;2392def LNLPWriteResGroup51 : SchedWriteRes<[LNLPVPort02_03]> {2393 let ReleaseAtCycles = [3];2394 let Latency = LunarlakePModel.MaxLatency;2395}2396def : InstRW<[LNLPWriteResGroup51], (instrs VSHA512RNDS2rr)>;2397def LNLPWriteResGroup52 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {2398 let ReleaseAtCycles = [3, 6];2399 let Latency = LunarlakePModel.MaxLatency;2400 let NumMicroOps = 2;2401}2402def : InstRW<[LNLPWriteResGroup52], (instregex "^VSM3MSG(1|2)rm$")>;2403def LNLPWriteResGroup53 : SchedWriteRes<[LNLPVPort00_01]> {2404 let ReleaseAtCycles = [3];2405 let Latency = LunarlakePModel.MaxLatency;2406}2407def : InstRW<[LNLPWriteResGroup53], (instregex "^VSM3MSG(1|2)rr$")>;2408def : InstRW<[LNLPWriteResGroup53], (instrs VTESTPSYrr)>;2409}2410