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1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Skylake Client to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14def SkylakeClientModel : SchedMachineModel {15 // All x86 instructions are modeled as a single micro-op, and SKylake can16 // decode 6 instructions per cycle.17 let IssueWidth = 6;18 let MicroOpBufferSize = 224; // Based on the reorder buffer.19 let LoadLatency = 5;20 let MispredictPenalty = 14;21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.23 let LoopMicroOpBufferSize = 50;24 25 // This flag is set to allow the scheduler to assign a default model to26 // unrecognized opcodes.27 let CompleteModel = 0;28}29 30let SchedModel = SkylakeClientModel in {31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle.33 34// Ports 0, 1, 5, and 6 handle all computation.35// Port 4 gets the data half of stores. Store data can be available later than36// the store address, but since we don't model the latency of stores, we can37// ignore that.38// Ports 2 and 3 are identical. They handle loads and the address half of39// stores. Port 7 can handle address calculations.40def SKLPort0 : ProcResource<1>;41def SKLPort1 : ProcResource<1>;42def SKLPort2 : ProcResource<1>;43def SKLPort3 : ProcResource<1>;44def SKLPort4 : ProcResource<1>;45def SKLPort5 : ProcResource<1>;46def SKLPort6 : ProcResource<1>;47def SKLPort7 : ProcResource<1>;48 49// Many micro-ops are capable of issuing on multiple ports.50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>;51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>;52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>;54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>;55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>;56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>;57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>;58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>;59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0.64// FP division and sqrt on port 0.65def SKLFPDivider : ProcResource<1>;66 67// 60 Entry Unified Scheduler68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,69 SKLPort5, SKLPort6, SKLPort7]> {70 let BufferSize=60;71}72 73// Skylake can retire up to four (potentially fused) uops per cycle. Set the74// limit to twice that given we do not model fused uops as only taking up one75// retirement slot. I could not find any documented sources on how many76// in-flight micro-ops can be tracked.77def SKRCU : RetireControlUnit<0, 8>;78 79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 580// cycles after the memory operand.81def : ReadAdvance<ReadAfterLd, 5>;82 83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available84// until 5/6/7 cycles after the memory operand.85def : ReadAdvance<ReadAfterVecLd, 5>;86def : ReadAdvance<ReadAfterVecXLd, 6>;87def : ReadAdvance<ReadAfterVecYLd, 7>;88 89def : ReadAdvance<ReadInt2Fpu, 0>;90 91// Many SchedWrites are defined in pairs with and without a folded load.92// Instructions with folded loads are usually micro-fused, so they only appear93// as two micro-ops when queued in the reservation station.94// This multiclass defines the resource usage for variants with and without95// folded loads.96multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,97 list<ProcResourceKind> ExePorts,98 int Lat, list<int> Res = [1], int UOps = 1,99 int LoadLat = 5, int LoadUOps = 1> {100 // Register variant is using a single cycle on ExePort.101 def : WriteRes<SchedRW, ExePorts> {102 let Latency = Lat;103 let ReleaseAtCycles = Res;104 let NumMicroOps = UOps;105 }106 107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to108 // the latency (default = 5).109 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {110 let Latency = !add(Lat, LoadLat);111 let ReleaseAtCycles = !listconcat([1], Res);112 let NumMicroOps = !add(UOps, LoadUOps);113 }114}115 116// A folded store needs a cycle on port 4 for the store data, and an extra port117// 2/3/7 cycle to recompute the address.118def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;119 120// Arithmetic.121defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.122defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op.123 124// Integer multiplication.125defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>;126defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;127defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>;128defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;129defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>;130defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;131defm : SKLWriteResPair<WriteMULX32, [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>;132defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>;133defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>;134defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>;135defm : SKLWriteResPair<WriteMULX64, [SKLPort1,SKLPort5], 3, [1,1], 2>;136defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>;137defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>;138def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }139def : WriteRes<WriteIMulHLd, []> {140 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);141}142 143defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>;144defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>;145defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;146defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;147defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;148 149// TODO: Why isn't the SKLDivider used?150defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;151defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;152defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;153defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;154defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;155defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;156defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;157 158defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>;159defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;160defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;161defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;162defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;163defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;164defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;165defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;166 167defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;168 169def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.170 171defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move.172defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.173def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.174def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {175 let Latency = 2;176 let NumMicroOps = 3;177}178 179defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>;180defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>;181defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>;182defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>;183defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>;184defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;185defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;186 187// Bit counts.188defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;189defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;190defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>;191defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>;192defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;193 194// Integer shifts and rotates.195defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;196defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>;197defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>;198defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>;199 200// SHLD/SHRD.201defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;202defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;203defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;204defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;205 206// BMI1 BEXTR/BLS, BMI2 BZHI207defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;208defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>;209defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>;210 211// Loads, stores, and moves, not folded with other operations.212defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>;213defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>;214defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;215defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>;216 217// Model the effect of clobbering the read-write mask operand of the GATHER operation.218// Does not cost anything by itself, only has latency, matching that of the WriteLoad,219defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;220 221// Idioms that clear a register, like xorps %xmm0, %xmm0.222// These can often bypass execution ports completely.223def : WriteRes<WriteZero, []>;224 225// Branches don't produce values, so they have no latency, but they still226// consume resources. Indirect branches can fold loads.227defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>;228 229// Floating point. This covers both scalar and vector operations.230defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>;231defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>;232defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>;233defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>;234defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>;235defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>;236defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>;237defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>;238defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>;239defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>;240defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>;241defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;242defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>;243defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;244 245defm : X86WriteRes<WriteFMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;246defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;247defm : X86WriteRes<WriteFMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;248defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;249 250defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>;251defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>;252defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>;253defm : X86WriteResUnsupported<WriteFMoveZ>;254defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>;255 256defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub.257defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>;258defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>;259defm : X86WriteResPairUnsupported<WriteFAddZ>;260defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub.261defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>;262defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>;263defm : X86WriteResPairUnsupported<WriteFAdd64Z>;264 265defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare.266defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>;267defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>;268defm : X86WriteResPairUnsupported<WriteFCmpZ>;269defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare.270defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>;271defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>;272defm : X86WriteResPairUnsupported<WriteFCmp64Z>;273 274defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87).275defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE).276 277defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication.278defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>;279defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>;280defm : X86WriteResPairUnsupported<WriteFMulZ>;281defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication.282defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>;283defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>;284defm : X86WriteResPairUnsupported<WriteFMul64Z>;285 286defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.287defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;288defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;289defm : X86WriteResPairUnsupported<WriteFDivZ>;290defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 5>; // Floating point double division.291defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 6>;292defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,8], 1, 7>;293defm : X86WriteResPairUnsupported<WriteFDiv64Z>;294 295defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.296defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;297defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;298defm : X86WriteResPairUnsupported<WriteFSqrtZ>;299defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.300defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;301defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;302defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;303defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.304 305defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.306defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>;307defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>;308defm : X86WriteResPairUnsupported<WriteFRcpZ>;309 310defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.311defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;312defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;313defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;314 315defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.316defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>;317defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>;318defm : X86WriteResPairUnsupported<WriteFMAZ>;319defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product.320defm : X86WriteRes<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4>;321defm : X86WriteRes<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4>;322defm : X86WriteRes<WriteDPPSLd, [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 19, [1,3,1,1], 6>;323defm : X86WriteRes<WriteDPPSYLd, [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 20, [1,3,1,1], 6>;324defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs.325defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.326defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>;327defm : X86WriteResPairUnsupported<WriteFRndZ>;328defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.329defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;330defm : X86WriteResPairUnsupported<WriteFLogicZ>;331defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.332defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>;333defm : X86WriteResPairUnsupported<WriteFTestZ>;334defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.335defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;336defm : X86WriteResPairUnsupported<WriteFShuffleZ>;337defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.338defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;339defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;340defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.341defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;342defm : X86WriteResPairUnsupported<WriteFBlendZ>;343defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.344defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;345defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;346 347// FMA Scheduling helper class.348// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }349 350// Vector integer operations.351defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>;352defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>;353defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>;354defm : X86WriteRes<WriteVecLoadNT, [SKLPort23,SKLPort015], 7, [1,1], 2>;355defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23,SKLPort015], 8, [1,1], 2>;356defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>;357defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>;358defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>;359defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>;360defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>;361defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;362defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;363defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;364defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;365defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;366defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 3>;367defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>;368defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>;369defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>;370defm : X86WriteResUnsupported<WriteVecMoveZ>;371defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>;372defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>;373 374defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.375defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>;376defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>;377defm : X86WriteResPairUnsupported<WriteVecALUZ>;378defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.379defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;380defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;381defm : X86WriteResPairUnsupported<WriteVecLogicZ>;382defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.383defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;384defm : X86WriteResPairUnsupported<WriteVecTestZ>;385defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply.386defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>;387defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>;388defm : X86WriteResPairUnsupported<WriteVecIMulZ>;389defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.390defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>;391defm : X86WriteResPairUnsupported<WritePMULLDZ>;392defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.393defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;394defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;395defm : X86WriteResPairUnsupported<WriteShuffleZ>;396defm : SKLWriteResPair<WriteVarShuffle, [SKLPort0,SKLPort5], 1, [1,1], 2, 5>; // Vector shuffles.397defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;398defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;399defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;400defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends.401defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;402defm : X86WriteResPairUnsupported<WriteBlendZ>;403defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.404defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;405defm : X86WriteResPairUnsupported<WriteVarBlendZ>;406defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.407defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;408defm : X86WriteResPairUnsupported<WriteMPSADZ>;409defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.410defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;411defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;412defm : X86WriteResPairUnsupported<WritePSADBWZ>;413defm : SKLWriteResPair<WritePHMINPOS, [SKLPort0], 4, [1], 1, 6>; // Vector PHMINPOS.414 415// Vector integer shifts.416defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>;417defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>;418defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>;419defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>;420defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>;421defm : X86WriteResPairUnsupported<WriteVecShiftZ>;422 423defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts.424defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;425defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;426defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;427defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.428defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;429defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;430 431// Vector insert/extract operations.432def : WriteRes<WriteVecInsert, [SKLPort5]> {433 let Latency = 2;434 let NumMicroOps = 2;435 let ReleaseAtCycles = [2];436}437def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {438 let Latency = 6;439 let NumMicroOps = 2;440}441def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;442 443def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {444 let Latency = 3;445 let NumMicroOps = 2;446}447def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {448 let Latency = 2;449 let NumMicroOps = 3;450}451 452// Conversion between integer and float.453defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;454defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort01], 4, [1], 1, 6>;455defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort01], 4, [1], 1, 7>;456defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;457defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;458defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;459defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;460defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;461 462defm : X86WriteRes<WriteCvtI2SS, [SKLPort5,SKLPort01], 5, [1,1], 2>;463defm : X86WriteRes<WriteCvtI2SSLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;464defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort01], 4, [1], 1, 6>;465defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort01], 4, [1], 1, 7>;466defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;467defm : X86WriteRes<WriteCvtI2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>;468defm : X86WriteRes<WriteCvtI2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;469defm : X86WriteRes<WriteCvtI2PD, [SKLPort5,SKLPort01], 5, [1,1], 2>;470defm : X86WriteRes<WriteCvtI2PDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;471defm : X86WriteRes<WriteCvtI2PDY, [SKLPort5,SKLPort01], 7, [1,1], 2>;472defm : X86WriteRes<WriteCvtI2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>;473defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;474 475defm : X86WriteRes<WriteCvtSS2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>;476defm : X86WriteRes<WriteCvtSS2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;477defm : X86WriteRes<WriteCvtPS2PD, [SKLPort5,SKLPort01], 5, [1,1], 2>;478defm : X86WriteRes<WriteCvtPS2PDLd, [SKLPort23,SKLPort01], 9, [1,1], 2>;479defm : X86WriteRes<WriteCvtPS2PDY, [SKLPort5,SKLPort01], 7, [1,1], 2>;480defm : X86WriteRes<WriteCvtPS2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>;481defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;482defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort5,SKLPort01], 5, [1,1], 2, 5>;483defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;484defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;485defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;486 487defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort01], 5, [1,1], 2>;488defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>;489defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;490defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>;491defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;492defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;493 494defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort01], 5, [1,1], 2>;495defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>;496defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;497defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;498defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;499defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;500 501// Strings instructions.502 503// Packed Compare Implicit Length Strings, Return Mask504def : WriteRes<WritePCmpIStrM, [SKLPort0]> {505 let Latency = 10;506 let NumMicroOps = 3;507 let ReleaseAtCycles = [3];508}509def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {510 let Latency = 16;511 let NumMicroOps = 4;512 let ReleaseAtCycles = [3,1];513}514 515// Packed Compare Explicit Length Strings, Return Mask516def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {517 let Latency = 19;518 let NumMicroOps = 9;519 let ReleaseAtCycles = [4,3,1,1];520}521def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {522 let Latency = 25;523 let NumMicroOps = 10;524 let ReleaseAtCycles = [4,3,1,1,1];525}526 527// Packed Compare Implicit Length Strings, Return Index528def : WriteRes<WritePCmpIStrI, [SKLPort0]> {529 let Latency = 10;530 let NumMicroOps = 3;531 let ReleaseAtCycles = [3];532}533def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {534 let Latency = 16;535 let NumMicroOps = 4;536 let ReleaseAtCycles = [3,1];537}538 539// Packed Compare Explicit Length Strings, Return Index540def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {541 let Latency = 18;542 let NumMicroOps = 8;543 let ReleaseAtCycles = [4,3,1];544}545def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {546 let Latency = 24;547 let NumMicroOps = 9;548 let ReleaseAtCycles = [4,3,1,1];549}550 551// MOVMSK Instructions.552def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; }553def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; }554def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }555def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; }556 557// AES instructions.558def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.559 let Latency = 4;560 let NumMicroOps = 1;561 let ReleaseAtCycles = [1];562}563def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {564 let Latency = 10;565 let NumMicroOps = 2;566 let ReleaseAtCycles = [1,1];567}568 569def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.570 let Latency = 8;571 let NumMicroOps = 2;572 let ReleaseAtCycles = [2];573}574def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {575 let Latency = 14;576 let NumMicroOps = 3;577 let ReleaseAtCycles = [2,1];578}579 580def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.581 let Latency = 20;582 let NumMicroOps = 11;583 let ReleaseAtCycles = [3,6,2];584}585def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {586 let Latency = 25;587 let NumMicroOps = 11;588 let ReleaseAtCycles = [3,6,1,1];589}590 591// Carry-less multiplication instructions.592def : WriteRes<WriteCLMul, [SKLPort5]> {593 let Latency = 6;594 let NumMicroOps = 1;595 let ReleaseAtCycles = [1];596}597def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {598 let Latency = 12;599 let NumMicroOps = 2;600 let ReleaseAtCycles = [1,1];601}602 603// Catch-all for expensive system instructions.604def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;605 606// AVX2.607defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.608defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.609defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.610defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move.611defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.612 613// Old microcoded instructions that nobody use.614def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;615 616// Fence instructions.617def : WriteRes<WriteFence, [SKLPort23, SKLPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }618 619// Load/store MXCSR.620def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }621def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }622 623// Nop, not very useful expect it provides a model for nops!624def : WriteRes<WriteNop, []>;625 626////////////////////////////////////////////////////////////////////////////////627// Horizontal add/sub instructions.628////////////////////////////////////////////////////////////////////////////////629 630defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;631defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;632defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>;633defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;634defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;635 636// Remaining instrs.637 638def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {639 let Latency = 1;640 let NumMicroOps = 1;641 let ReleaseAtCycles = [1];642}643def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",644 "MMX_PADDUS(B|W)rr",645 "MMX_PAVG(B|W)rr",646 "MMX_PCMPEQ(B|D|W)rr",647 "MMX_PCMPGT(B|D|W)rr",648 "MMX_P(MAX|MIN)SWrr",649 "MMX_P(MAX|MIN)UBrr",650 "MMX_PSUBS(B|W)rr",651 "MMX_PSUBUS(B|W)rr")>;652 653def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {654 let Latency = 1;655 let NumMicroOps = 1;656 let ReleaseAtCycles = [1];657}658def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",659 "UCOM_F(P?)r")>;660 661def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {662 let Latency = 1;663 let NumMicroOps = 1;664 let ReleaseAtCycles = [1];665}666def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;667 668def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {669 let Latency = 1;670 let NumMicroOps = 1;671 let ReleaseAtCycles = [1];672}673def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;674 675def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {676 let Latency = 1;677 let NumMicroOps = 1;678 let ReleaseAtCycles = [1];679}680def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;681 682def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {683 let Latency = 1;684 let NumMicroOps = 1;685 let ReleaseAtCycles = [1];686}687def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;688 689def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {690 let Latency = 1;691 let NumMicroOps = 1;692 let ReleaseAtCycles = [1];693}694def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",695 "VPBLENDD(Y?)rri")>;696 697def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {698 let Latency = 1;699 let NumMicroOps = 1;700 let ReleaseAtCycles = [1];701}702def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,703 SIDT64m,704 SMSW16m,705 STRm,706 SYSCALL)>;707 708def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {709 let Latency = 1;710 let NumMicroOps = 2;711 let ReleaseAtCycles = [1,1];712}713def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;714def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;715 716def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {717 let Latency = 2;718 let NumMicroOps = 2;719 let ReleaseAtCycles = [2];720}721def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;722 723def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {724 let Latency = 2;725 let NumMicroOps = 2;726 let ReleaseAtCycles = [2];727}728def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,729 MMX_MOVDQ2Qrr)>;730 731def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {732 let Latency = 2;733 let NumMicroOps = 2;734 let ReleaseAtCycles = [2];735}736def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,737 WAIT,738 XGETBV)>;739 740def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {741 let Latency = 2;742 let NumMicroOps = 2;743 let ReleaseAtCycles = [1,1];744}745def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;746 747def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {748 let Latency = 2;749 let NumMicroOps = 2;750 let ReleaseAtCycles = [1,1];751}752def: InstRW<[SKLWriteResGroup23], (instrs CWD,753 JCXZ, JECXZ, JRCXZ,754 ADC8i8, SBB8i8,755 ADC16i16, SBB16i16,756 ADC32i32, SBB32i32,757 ADC64i32, SBB64i32)>;758 759def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {760 let Latency = 2;761 let NumMicroOps = 3;762 let ReleaseAtCycles = [1,1,1];763}764def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;765 766def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {767 let Latency = 2;768 let NumMicroOps = 3;769 let ReleaseAtCycles = [1,1,1];770}771def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;772 773def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {774 let Latency = 2;775 let NumMicroOps = 3;776 let ReleaseAtCycles = [1,1,1];777}778def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,779 STOSB, STOSL, STOSQ, STOSW)>;780def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;781 782def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {783 let Latency = 3;784 let NumMicroOps = 1;785 let ReleaseAtCycles = [1];786}787def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",788 "PEXT(32|64)rr")>;789 790def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {791 let Latency = 3;792 let NumMicroOps = 1;793 let ReleaseAtCycles = [1];794}795def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",796 "VPBROADCAST(B|W)rr")>;797 798def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {799 let Latency = 3;800 let NumMicroOps = 2;801 let ReleaseAtCycles = [1,1];802}803def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;804 805def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {806 let Latency = 3;807 let NumMicroOps = 3;808 let ReleaseAtCycles = [1,2];809}810def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;811 812def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {813 let Latency = 3;814 let NumMicroOps = 3;815 let ReleaseAtCycles = [2,1];816}817def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",818 "(V?)PHSUBSW(Y?)rr")>;819 820def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5]> {821 let Latency = 2;822 let NumMicroOps = 2;823 let ReleaseAtCycles = [2];824}825def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,826 MMX_PACKSSWBrr,827 MMX_PACKUSWBrr)>;828 829def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {830 let Latency = 3;831 let NumMicroOps = 3;832 let ReleaseAtCycles = [1,2];833}834def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;835 836def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {837 let Latency = 2;838 let NumMicroOps = 3;839 let ReleaseAtCycles = [1,2];840}841def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,842 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;843 844def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {845 let Latency = 5;846 let NumMicroOps = 8;847 let ReleaseAtCycles = [2,4,2];848}849def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;850 851def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {852 let Latency = 6;853 let NumMicroOps = 8;854 let ReleaseAtCycles = [2,4,2];855}856def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;857 858def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {859 let Latency = 3;860 let NumMicroOps = 3;861 let ReleaseAtCycles = [1,1,1];862}863def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;864 865def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {866 let Latency = 3;867 let NumMicroOps = 4;868 let ReleaseAtCycles = [1,1,1,1];869}870def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;871 872def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {873 let Latency = 3;874 let NumMicroOps = 4;875 let ReleaseAtCycles = [1,1,1,1];876}877def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;878 879def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {880 let Latency = 4;881 let NumMicroOps = 1;882 let ReleaseAtCycles = [1];883}884def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;885 886def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {887 let Latency = 4;888 let NumMicroOps = 3;889 let ReleaseAtCycles = [1,1,1];890}891def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",892 "IST_F(16|32)m")>;893 894def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {895 let Latency = 4;896 let NumMicroOps = 4;897 let ReleaseAtCycles = [4];898}899def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;900 901def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {902 let Latency = 4;903 let NumMicroOps = 4;904 let ReleaseAtCycles = [1,3];905}906def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;907 908def SKLWriteResGroup56 : SchedWriteRes<[]> {909 let Latency = 0;910 let NumMicroOps = 4;911 let ReleaseAtCycles = [];912}913def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;914 915def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {916 let Latency = 4;917 let NumMicroOps = 4;918 let ReleaseAtCycles = [1,1,2];919}920def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;921 922def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort0]> {923 let Latency = 5;924 let NumMicroOps = 2;925 let ReleaseAtCycles = [1,1];926}927def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>;928 929def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {930 let Latency = 5;931 let NumMicroOps = 3;932 let ReleaseAtCycles = [1,1,1];933}934def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;935 936def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {937 let Latency = 5;938 let NumMicroOps = 5;939 let ReleaseAtCycles = [1,4];940}941def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;942 943def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {944 let Latency = 5;945 let NumMicroOps = 6;946 let ReleaseAtCycles = [1,1,4];947}948def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;949 950def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {951 let Latency = 6;952 let NumMicroOps = 1;953 let ReleaseAtCycles = [1];954}955def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,956 VPBROADCASTDrm,957 VPBROADCASTQrm)>;958def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",959 "(V?)MOVSLDUPrm",960 "(V?)MOVDDUPrm")>;961 962def SKLWriteResGroup68 : SchedWriteRes<[SKLPort01]> {963 let Latency = 6;964 let NumMicroOps = 2;965 let ReleaseAtCycles = [2];966}967def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;968 969def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {970 let Latency = 6;971 let NumMicroOps = 2;972 let ReleaseAtCycles = [1,1];973}974def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,975 MMX_PADDSWrm,976 MMX_PADDUSBrm,977 MMX_PADDUSWrm,978 MMX_PAVGBrm,979 MMX_PAVGWrm,980 MMX_PCMPEQBrm,981 MMX_PCMPEQDrm,982 MMX_PCMPEQWrm,983 MMX_PCMPGTBrm,984 MMX_PCMPGTDrm,985 MMX_PCMPGTWrm,986 MMX_PMAXSWrm,987 MMX_PMAXUBrm,988 MMX_PMINSWrm,989 MMX_PMINUBrm,990 MMX_PSUBSBrm,991 MMX_PSUBSWrm,992 MMX_PSUBUSBrm,993 MMX_PSUBUSWrm)>;994 995def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {996 let Latency = 6;997 let NumMicroOps = 2;998 let ReleaseAtCycles = [1,1];999}1000def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;1001def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;1002 1003def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {1004 let Latency = 6;1005 let NumMicroOps = 2;1006 let ReleaseAtCycles = [1,1];1007}1008def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",1009 "MOVBE(16|32|64)rm")>;1010 1011def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {1012 let Latency = 6;1013 let NumMicroOps = 2;1014 let ReleaseAtCycles = [1,1];1015}1016def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;1017def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;1018 1019def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {1020 let Latency = 6;1021 let NumMicroOps = 3;1022 let ReleaseAtCycles = [2,1];1023}1024def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;1025 1026def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {1027 let Latency = 6;1028 let NumMicroOps = 4;1029 let ReleaseAtCycles = [1,1,1,1];1030}1031def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;1032 1033def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {1034 let Latency = 6;1035 let NumMicroOps = 4;1036 let ReleaseAtCycles = [1,1,1,1];1037}1038def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",1039 "SHL(8|16|32|64)m(1|i)",1040 "SHR(8|16|32|64)m(1|i)")>;1041 1042def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {1043 let Latency = 6;1044 let NumMicroOps = 4;1045 let ReleaseAtCycles = [1,1,1,1];1046}1047def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",1048 "PUSH(16|32|64)rmm")>;1049 1050def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {1051 let Latency = 6;1052 let NumMicroOps = 6;1053 let ReleaseAtCycles = [1,5];1054}1055def: InstRW<[SKLWriteResGroup84], (instrs STD)>;1056 1057def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {1058 let Latency = 7;1059 let NumMicroOps = 1;1060 let ReleaseAtCycles = [1];1061}1062def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;1063def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,1064 VBROADCASTI128rm,1065 VBROADCASTSDYrm,1066 VBROADCASTSSYrm,1067 VMOVDDUPYrm,1068 VMOVSHDUPYrm,1069 VMOVSLDUPYrm,1070 VPBROADCASTDYrm,1071 VPBROADCASTQYrm)>;1072 1073def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {1074 let Latency = 6;1075 let NumMicroOps = 2;1076 let ReleaseAtCycles = [1,1];1077}1078def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",1079 "(V?)PMOV(SX|ZX)BQrm",1080 "(V?)PMOV(SX|ZX)BWrm",1081 "(V?)PMOV(SX|ZX)DQrm",1082 "(V?)PMOV(SX|ZX)WDrm",1083 "(V?)PMOV(SX|ZX)WQrm")>;1084 1085def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {1086 let Latency = 7;1087 let NumMicroOps = 2;1088 let ReleaseAtCycles = [1,1];1089}1090def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rmi,1091 VINSERTI128rmi,1092 VPBLENDDrmi)>;1093def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],1094 (instregex "(V?)PADD(B|D|Q|W)rm",1095 "(V?)PSUB(B|D|Q|W)rm")>;1096 1097def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {1098 let Latency = 7;1099 let NumMicroOps = 3;1100 let ReleaseAtCycles = [2,1];1101}1102def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,1103 MMX_PACKSSWBrm,1104 MMX_PACKUSWBrm)>;1105 1106def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {1107 let Latency = 7;1108 let NumMicroOps = 3;1109 let ReleaseAtCycles = [1,2];1110}1111def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,1112 SCASB, SCASL, SCASQ, SCASW)>;1113 1114def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {1115 let Latency = 7;1116 let NumMicroOps = 3;1117 let ReleaseAtCycles = [1,1,1];1118}1119def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;1120 1121def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {1122 let Latency = 7;1123 let NumMicroOps = 3;1124 let ReleaseAtCycles = [1,1,1];1125}1126def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;1127 1128def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {1129 let Latency = 7;1130 let NumMicroOps = 3;1131 let ReleaseAtCycles = [1,1,1];1132}1133def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;1134 1135def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {1136 let Latency = 7;1137 let NumMicroOps = 5;1138 let ReleaseAtCycles = [1,1,1,2];1139}1140def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",1141 "ROR(8|16|32|64)m(1|i)")>;1142 1143def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {1144 let Latency = 2;1145 let NumMicroOps = 2;1146 let ReleaseAtCycles = [2];1147}1148def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,1149 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;1150 1151def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {1152 let Latency = 7;1153 let NumMicroOps = 5;1154 let ReleaseAtCycles = [1,1,1,2];1155}1156def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;1157 1158def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {1159 let Latency = 7;1160 let NumMicroOps = 5;1161 let ReleaseAtCycles = [1,1,1,1,1];1162}1163def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;1164def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;1165 1166def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {1167 let Latency = 7;1168 let NumMicroOps = 7;1169 let ReleaseAtCycles = [1,3,1,2];1170}1171def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;1172 1173def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {1174 let Latency = 8;1175 let NumMicroOps = 2;1176 let ReleaseAtCycles = [1,1];1177}1178def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",1179 "PEXT(32|64)rm")>;1180 1181def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {1182 let Latency = 8;1183 let NumMicroOps = 2;1184 let ReleaseAtCycles = [1,1];1185}1186def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;1187def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,1188 VPBROADCASTWYrm,1189 VPMOVSXBDYrm,1190 VPMOVSXBQYrm,1191 VPMOVSXWQYrm)>;1192 1193def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {1194 let Latency = 8;1195 let NumMicroOps = 2;1196 let ReleaseAtCycles = [1,1];1197}1198def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;1199def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],1200 (instregex "VPADD(B|D|Q|W)Yrm",1201 "VPSUB(B|D|Q|W)Yrm")>;1202 1203def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {1204 let Latency = 8;1205 let NumMicroOps = 4;1206 let ReleaseAtCycles = [1,2,1];1207}1208def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;1209 1210def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1211 let Latency = 8;1212 let NumMicroOps = 5;1213 let ReleaseAtCycles = [1,1,1,2];1214}1215def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",1216 "RCR(8|16|32|64)m(1|i)")>;1217 1218def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {1219 let Latency = 8;1220 let NumMicroOps = 6;1221 let ReleaseAtCycles = [1,1,1,3];1222}1223def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",1224 "ROR(8|16|32|64)mCL",1225 "SAR(8|16|32|64)mCL",1226 "SHL(8|16|32|64)mCL",1227 "SHR(8|16|32|64)mCL")>;1228 1229def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1230 let Latency = 8;1231 let NumMicroOps = 6;1232 let ReleaseAtCycles = [1,1,1,2,1];1233}1234def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;1235 1236def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {1237 let Latency = 9;1238 let NumMicroOps = 2;1239 let ReleaseAtCycles = [1,1];1240}1241def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,1242 VPCMPGTQrm,1243 VPMOVSXBWYrm,1244 VPMOVSXDQYrm,1245 VPMOVSXWDYrm,1246 VPMOVZXWDYrm)>;1247 1248def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort0]> {1249 let Latency = 9;1250 let NumMicroOps = 2;1251 let ReleaseAtCycles = [1,1];1252}1253def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>;1254 1255def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {1256 let Latency = 9;1257 let NumMicroOps = 4;1258 let ReleaseAtCycles = [2,1,1];1259}1260def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",1261 "(V?)PHSUBSWrm")>;1262 1263def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {1264 let Latency = 9;1265 let NumMicroOps = 5;1266 let ReleaseAtCycles = [1,2,1,1];1267}1268def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",1269 "LSL(16|32|64)rm")>;1270 1271def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {1272 let Latency = 10;1273 let NumMicroOps = 2;1274 let ReleaseAtCycles = [1,1];1275}1276def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",1277 "ILD_F(16|32|64)m")>;1278def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;1279 1280def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {1281 let Latency = 10;1282 let NumMicroOps = 4;1283 let ReleaseAtCycles = [2,1,1];1284}1285def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,1286 VPHSUBSWYrm)>;1287 1288def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1289 let Latency = 10;1290 let NumMicroOps = 8;1291 let ReleaseAtCycles = [1,1,1,1,1,3];1292}1293def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;1294 1295def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {1296 let Latency = 11;1297 let NumMicroOps = 2;1298 let ReleaseAtCycles = [1,1];1299}1300def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;1301 1302def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {1303 let Latency = 11;1304 let NumMicroOps = 3;1305 let ReleaseAtCycles = [2,1];1306}1307def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;1308 1309def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {1310 let Latency = 11;1311 let NumMicroOps = 7;1312 let ReleaseAtCycles = [2,3,2];1313}1314def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",1315 "RCR(16|32|64)rCL")>;1316 1317def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {1318 let Latency = 11;1319 let NumMicroOps = 9;1320 let ReleaseAtCycles = [1,5,1,2];1321}1322def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;1323 1324def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {1325 let Latency = 11;1326 let NumMicroOps = 11;1327 let ReleaseAtCycles = [2,9];1328}1329def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;1330 1331def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {1332 let Latency = 13;1333 let NumMicroOps = 3;1334 let ReleaseAtCycles = [2,1];1335}1336def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;1337 1338def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {1339 let Latency = 14;1340 let NumMicroOps = 3;1341 let ReleaseAtCycles = [1,1,1];1342}1343def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;1344 1345def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {1346 let Latency = 14;1347 let NumMicroOps = 10;1348 let ReleaseAtCycles = [2,4,1,3];1349}1350def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;1351 1352def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {1353 let Latency = 15;1354 let NumMicroOps = 1;1355 let ReleaseAtCycles = [1];1356}1357def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;1358 1359def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {1360 let Latency = 15;1361 let NumMicroOps = 10;1362 let ReleaseAtCycles = [1,1,1,5,1,1];1363}1364def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;1365 1366def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {1367 let Latency = 16;1368 let NumMicroOps = 14;1369 let ReleaseAtCycles = [1,1,1,4,2,5];1370}1371def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;1372 1373def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {1374 let Latency = 16;1375 let NumMicroOps = 16;1376 let ReleaseAtCycles = [16];1377}1378def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;1379 1380def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {1381 let Latency = 17;1382 let NumMicroOps = 15;1383 let ReleaseAtCycles = [2,1,2,4,2,4];1384}1385def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;1386 1387def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {1388 let Latency = 18;1389 let NumMicroOps = 8;1390 let ReleaseAtCycles = [1,1,1,5];1391}1392def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;1393 1394def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {1395 let Latency = 18;1396 let NumMicroOps = 11;1397 let ReleaseAtCycles = [2,1,1,4,1,2];1398}1399def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;1400 1401def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {1402 let Latency = 20;1403 let NumMicroOps = 1;1404 let ReleaseAtCycles = [1];1405}1406def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;1407 1408def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1409 let Latency = 20;1410 let NumMicroOps = 8;1411 let ReleaseAtCycles = [1,1,1,1,1,1,2];1412}1413def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;1414 1415def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {1416 let Latency = 20;1417 let NumMicroOps = 10;1418 let ReleaseAtCycles = [1,2,7];1419}1420def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;1421 1422def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {1423 let Latency = 22;1424 let NumMicroOps = 2;1425 let ReleaseAtCycles = [1,1];1426}1427def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;1428 1429def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {1430 let Latency = 18;1431 let NumMicroOps = 5; // 2 uops perform multiple loads1432 let ReleaseAtCycles = [1,2,1,1];1433}1434def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,1435 VGATHERQPDrm, VPGATHERQQrm,1436 VGATHERQPSrm, VPGATHERQDrm)>;1437 1438def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {1439 let Latency = 20;1440 let NumMicroOps = 5; // 2 uops peform multiple loads1441 let ReleaseAtCycles = [1,4,1,1];1442}1443def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,1444 VGATHERDPSrm, VPGATHERDDrm,1445 VGATHERQPDYrm, VPGATHERQQYrm,1446 VGATHERQPSYrm, VPGATHERQDYrm)>;1447 1448def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {1449 let Latency = 22;1450 let NumMicroOps = 5; // 2 uops perform multiple loads1451 let ReleaseAtCycles = [1,8,1,1];1452}1453def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;1454 1455def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1456 let Latency = 23;1457 let NumMicroOps = 19;1458 let ReleaseAtCycles = [2,1,4,1,1,4,6];1459}1460def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;1461 1462def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {1463 let Latency = 25;1464 let NumMicroOps = 3;1465 let ReleaseAtCycles = [1,1,1];1466}1467def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;1468 1469def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {1470 let Latency = 27;1471 let NumMicroOps = 2;1472 let ReleaseAtCycles = [1,1];1473}1474def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;1475 1476def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {1477 let Latency = 30;1478 let NumMicroOps = 3;1479 let ReleaseAtCycles = [1,1,1];1480}1481def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;1482 1483def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {1484 let Latency = 35;1485 let NumMicroOps = 23;1486 let ReleaseAtCycles = [1,5,3,4,10];1487}1488def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",1489 "IN(8|16|32)rr")>;1490 1491def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {1492 let Latency = 35;1493 let NumMicroOps = 23;1494 let ReleaseAtCycles = [1,5,2,1,4,10];1495}1496def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",1497 "OUT(8|16|32)rr")>;1498 1499def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {1500 let Latency = 37;1501 let NumMicroOps = 31;1502 let ReleaseAtCycles = [1,8,1,21];1503}1504def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;1505 1506def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {1507 let Latency = 40;1508 let NumMicroOps = 18;1509 let ReleaseAtCycles = [1,1,2,3,1,1,1,8];1510}1511def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;1512 1513def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {1514 let Latency = 41;1515 let NumMicroOps = 39;1516 let ReleaseAtCycles = [1,10,1,1,26];1517}1518def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;1519 1520def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {1521 let Latency = 42;1522 let NumMicroOps = 22;1523 let ReleaseAtCycles = [2,20];1524}1525def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;1526 1527def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {1528 let Latency = 42;1529 let NumMicroOps = 40;1530 let ReleaseAtCycles = [1,11,1,1,26];1531}1532def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;1533def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;1534 1535def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {1536 let Latency = 46;1537 let NumMicroOps = 44;1538 let ReleaseAtCycles = [1,11,1,1,30];1539}1540def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;1541 1542def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {1543 let Latency = 62;1544 let NumMicroOps = 64;1545 let ReleaseAtCycles = [2,8,5,10,39];1546}1547def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;1548 1549def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {1550 let Latency = 63;1551 let NumMicroOps = 88;1552 let ReleaseAtCycles = [4,4,31,1,2,1,45];1553}1554def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;1555 1556def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {1557 let Latency = 63;1558 let NumMicroOps = 90;1559 let ReleaseAtCycles = [4,2,33,1,2,1,47];1560}1561def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;1562 1563def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {1564 let Latency = 75;1565 let NumMicroOps = 15;1566 let ReleaseAtCycles = [6,3,6];1567}1568def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;1569 1570def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {1571 let Latency = 106;1572 let NumMicroOps = 100;1573 let ReleaseAtCycles = [9,1,11,16,1,11,21,30];1574}1575def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;1576 1577def: InstRW<[WriteZero], (instrs CLC)>;1578 1579 1580// Instruction variants handled by the renamer. These might not need execution1581// ports in certain conditions.1582// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",1583// section "Skylake Pipeline" > "Register allocation and renaming".1584// These can be investigated with llvm-exegesis, e.g.1585// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-1586// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-1587 1588def SKLWriteZeroLatency : SchedWriteRes<[]> {1589 let Latency = 0;1590}1591 1592def SKLWriteZeroIdiom : SchedWriteVariant<[1593 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1594 SchedVar<NoSchedPred, [WriteALU]>1595]>;1596def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,1597 XOR32rr, XOR64rr)>;1598 1599def SKLWriteFZeroIdiom : SchedWriteVariant<[1600 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1601 SchedVar<NoSchedPred, [WriteFLogic]>1602]>;1603def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,1604 VXORPDrr)>;1605 1606def SKLWriteFZeroIdiomY : SchedWriteVariant<[1607 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1608 SchedVar<NoSchedPred, [WriteFLogicY]>1609]>;1610def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;1611 1612def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[1613 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1614 SchedVar<NoSchedPred, [WriteVecLogicX]>1615]>;1616def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;1617 1618def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[1619 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1620 SchedVar<NoSchedPred, [WriteVecLogicY]>1621]>;1622def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;1623 1624def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[1625 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1626 SchedVar<NoSchedPred, [WriteVecALUX]>1627]>;1628def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,1629 PCMPGTDrr, VPCMPGTDrr,1630 PCMPGTWrr, VPCMPGTWrr)>;1631 1632def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[1633 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1634 SchedVar<NoSchedPred, [WriteVecALUY]>1635]>;1636def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,1637 VPCMPGTDYrr,1638 VPCMPGTWYrr)>;1639 1640def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {1641 let Latency = 1;1642 let NumMicroOps = 1;1643 let ReleaseAtCycles = [1];1644}1645 1646def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[1647 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1648 SchedVar<NoSchedPred, [SKLWritePSUB]>1649]>;1650def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,1651 PSUBDrr, VPSUBDrr,1652 PSUBQrr, VPSUBQrr,1653 PSUBWrr, VPSUBWrr,1654 VPSUBBYrr,1655 VPSUBDYrr,1656 VPSUBQYrr,1657 VPSUBWYrr)>;1658 1659def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {1660 let Latency = 3;1661 let NumMicroOps = 1;1662 let ReleaseAtCycles = [1];1663}1664 1665def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[1666 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,1667 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]>1668]>;1669def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,1670 VPCMPGTQYrr)>;1671 1672 1673// CMOVs that use both Z and C flag require an extra uop.1674def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {1675 let Latency = 2;1676 let ReleaseAtCycles = [2];1677 let NumMicroOps = 2;1678}1679 1680def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {1681 let Latency = 7;1682 let ReleaseAtCycles = [1,2];1683 let NumMicroOps = 3;1684}1685 1686def SKLCMOVA_CMOVBErr : SchedWriteVariant<[1687 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,1688 SchedVar<NoSchedPred, [WriteCMOV]>1689]>;1690 1691def SKLCMOVA_CMOVBErm : SchedWriteVariant<[1692 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,1693 SchedVar<NoSchedPred, [WriteCMOV.Folded]>1694]>;1695 1696def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;1697def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;1698 1699// SETCCs that use both Z and C flag require an extra uop.1700def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {1701 let Latency = 2;1702 let ReleaseAtCycles = [2];1703 let NumMicroOps = 2;1704}1705 1706def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {1707 let Latency = 3;1708 let ReleaseAtCycles = [1,1,2];1709 let NumMicroOps = 4;1710}1711 1712def SKLSETA_SETBErr : SchedWriteVariant<[1713 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,1714 SchedVar<NoSchedPred, [WriteSETCC]>1715]>;1716 1717def SKLSETA_SETBErm : SchedWriteVariant<[1718 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,1719 SchedVar<NoSchedPred, [WriteSETCCStore]>1720]>;1721 1722def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;1723def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;1724 1725///////////////////////////////////////////////////////////////////////////////1726// Dependency breaking instructions.1727///////////////////////////////////////////////////////////////////////////////1728 1729def : IsZeroIdiomFunction<[1730 // GPR Zero-idioms.1731 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,1732 1733 // SSE Zero-idioms.1734 DepBreakingClass<[1735 // fp variants.1736 XORPSrr, XORPDrr,1737 1738 // int variants.1739 PXORrr,1740 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,1741 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr1742 ], ZeroIdiomPredicate>,1743 1744 // AVX Zero-idioms.1745 DepBreakingClass<[1746 // xmm fp variants.1747 VXORPSrr, VXORPDrr,1748 1749 // xmm int variants.1750 VPXORrr,1751 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,1752 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,1753 1754 // ymm variants.1755 VXORPSYrr, VXORPDYrr, VPXORYrr,1756 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,1757 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr1758 ], ZeroIdiomPredicate>,1759]>;1760 1761} // SchedModel1762