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1//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Skylake Server to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14def SkylakeServerModel : SchedMachineModel {15 // All x86 instructions are modeled as a single micro-op, and SKylake can16 // decode 6 instructions per cycle.17 let IssueWidth = 6;18 let MicroOpBufferSize = 224; // Based on the reorder buffer.19 let LoadLatency = 5;20 let MispredictPenalty = 14;21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.23 let LoopMicroOpBufferSize = 50;24 25 // This flag is set to allow the scheduler to assign a default model to26 // unrecognized opcodes.27 let CompleteModel = 0;28}29 30let SchedModel = SkylakeServerModel in {31 32// Skylake Server can issue micro-ops to 8 different ports in one cycle.33 34// Ports 0, 1, 5, and 6 handle all computation.35// Port 4 gets the data half of stores. Store data can be available later than36// the store address, but since we don't model the latency of stores, we can37// ignore that.38// Ports 2 and 3 are identical. They handle loads and the address half of39// stores. Port 7 can handle address calculations.40def SKXPort0 : ProcResource<1>;41def SKXPort1 : ProcResource<1>;42def SKXPort2 : ProcResource<1>;43def SKXPort3 : ProcResource<1>;44def SKXPort4 : ProcResource<1>;45def SKXPort5 : ProcResource<1>;46def SKXPort6 : ProcResource<1>;47def SKXPort7 : ProcResource<1>;48 49// Many micro-ops are capable of issuing on multiple ports.50def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;51def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;52def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;53def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;54def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;55def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;56def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;57def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;58def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;59def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;60def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;61def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;62 63def SKXDivider : ProcResource<1>; // Integer division issued on port 0.64// FP division and sqrt on port 0.65def SKXFPDivider : ProcResource<1>;66 67// 60 Entry Unified Scheduler68def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,69 SKXPort5, SKXPort6, SKXPort7]> {70 let BufferSize=60;71}72 73// Skylake can retire up to four (potentially fused) uops per cycle. Set the74// limit to twice that given we do not model fused uops as only taking up one75// retirement slot. I could not find any documented sources on how many76// in-flight micro-ops can be tracked.77def SKXRCU : RetireControlUnit<0, 8>;78 79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 580// cycles after the memory operand.81def : ReadAdvance<ReadAfterLd, 5>;82 83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available84// until 5/6/7 cycles after the memory operand.85def : ReadAdvance<ReadAfterVecLd, 5>;86def : ReadAdvance<ReadAfterVecXLd, 6>;87def : ReadAdvance<ReadAfterVecYLd, 7>;88 89def : ReadAdvance<ReadInt2Fpu, 0>;90 91// Many SchedWrites are defined in pairs with and without a folded load.92// Instructions with folded loads are usually micro-fused, so they only appear93// as two micro-ops when queued in the reservation station.94// This multiclass defines the resource usage for variants with and without95// folded loads.96multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,97 list<ProcResourceKind> ExePorts,98 int Lat, list<int> Res = [1], int UOps = 1,99 int LoadLat = 5, int LoadUOps = 1> {100 // Register variant is using a single cycle on ExePort.101 def : WriteRes<SchedRW, ExePorts> {102 let Latency = Lat;103 let ReleaseAtCycles = Res;104 let NumMicroOps = UOps;105 }106 107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to108 // the latency (default = 5).109 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {110 let Latency = !add(Lat, LoadLat);111 let ReleaseAtCycles = !listconcat([1], Res);112 let NumMicroOps = !add(UOps, LoadUOps);113 }114}115 116// A folded store needs a cycle on port 4 for the store data, and an extra port117// 2/3/7 cycle to recompute the address.118def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;119 120// Arithmetic.121defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.122defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.123 124// Integer multiplication.125defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>;126defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;127defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>;128defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;129defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;130defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;131defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;132defm : SKXWriteResPair<WriteMULX32, [SKXPort1,SKXPort06,SKXPort0156], 3, [1,1,1], 3>;133defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;134defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;135defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;136defm : SKXWriteResPair<WriteMULX64, [SKXPort1,SKXPort5], 3, [1,1], 2>;137defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;138defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;139def SKXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }140def : WriteRes<WriteIMulHLd, []> {141 let Latency = !add(SKXWriteIMulH.Latency, SkylakeServerModel.LoadLatency);142}143 144defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;145defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;146defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;147defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;148defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;149 150// TODO: Why isn't the SKXDivider used?151defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;152defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;153defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;154defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;155defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;156defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;157defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;158 159defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>;160defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;161defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;162defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;163defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;164defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;165defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;166defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;167 168defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;169 170def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.171 172defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.173defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.174def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.175def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {176 let Latency = 2;177 let NumMicroOps = 3;178}179defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;180defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;181defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;182defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;183defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;184defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;185defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;186 187// Integer shifts and rotates.188defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;189defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;190defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>;191defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;192 193// SHLD/SHRD.194defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;195defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;196defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;197defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;198 199// Bit counts.200defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;201defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;202defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;203defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;204defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;205 206// BMI1 BEXTR/BLS, BMI2 BZHI207defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;208defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;209defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;210 211// Loads, stores, and moves, not folded with other operations.212defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;213defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;214defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;215defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;216 217// Model the effect of clobbering the read-write mask operand of the GATHER operation.218// Does not cost anything by itself, only has latency, matching that of the WriteLoad,219defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;220 221// Idioms that clear a register, like xorps %xmm0, %xmm0.222// These can often bypass execution ports completely.223def : WriteRes<WriteZero, []>;224 225// Branches don't produce values, so they have no latency, but they still226// consume resources. Indirect branches can fold loads.227defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;228 229// Floating point. This covers both scalar and vector operations.230defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;231defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;232defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;233defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;234defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;235defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;236defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;237defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;238defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;239defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;240defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;241defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;242defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;243defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;244 245defm : X86WriteRes<WriteFMaskedStore32, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;246defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;247defm : X86WriteRes<WriteFMaskedStore64, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;248defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;249 250defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;251defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;252defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;253defm : X86WriteRes<WriteFMoveZ, [SKXPort05], 1, [1], 1>;254defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;255 256defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.257defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;258defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;259defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;260defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.261defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;262defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;263defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;264 265defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.266defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;267defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;268defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;269defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.270defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;271defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;272defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;273 274defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags (X87).275defm : SKXWriteResPair<WriteFComX, [SKXPort0], 2>; // Floating point compare to flags (SSE).276 277defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.278defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;279defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;280defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;281defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.282defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;283defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;284defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;285 286defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.287defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.288defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.289defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.290defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,4], 1, 5>; // 10-14 cycles. // Floating point division.291defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,4], 1, 6>; // 10-14 cycles.292defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,8], 1, 7>; // 10-14 cycles.293defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.294 295defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.296defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;297defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;298defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;299defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.300defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;301defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;302defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;303defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.304 305defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.306defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;307defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;308defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;309 310defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.311defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;312defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;313defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;314 315defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.316defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;317defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;318defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;319defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.320defm : X86WriteRes<WriteDPPS, [SKXPort5,SKXPort01], 13, [1,3], 4>;321defm : X86WriteRes<WriteDPPSY, [SKXPort5,SKXPort01], 13, [1,3], 4>;322defm : X86WriteRes<WriteDPPSLd, [SKXPort5,SKXPort01,SKXPort06,SKXPort23], 19, [1,3,1,1], 6>;323defm : X86WriteRes<WriteDPPSYLd, [SKXPort5,SKXPort01,SKXPort06,SKXPort23], 20, [1,3,1,1], 6>;324defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.325defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.326defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;327defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;328defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.329defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;330defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;331defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.332defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;333defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;334defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.335defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;336defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;337defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.338defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;339defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;340defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.341defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;342defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;343defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.344defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;345defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;346 347// FMA Scheduling helper class.348// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }349 350// Vector integer operations.351defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;352defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;353defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;354defm : X86WriteRes<WriteVecLoadNT, [SKXPort23,SKXPort015], 7, [1,1], 2>;355defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23,SKXPort015], 8, [1,1], 2>;356defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;357defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;358defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;359defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;360defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;361defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;362defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;363defm : X86WriteRes<WriteVecMaskedStore32, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;364defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;365defm : X86WriteRes<WriteVecMaskedStore64, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;366defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort23,SKXPort0,SKXPort4], 2, [1,1,1], 3>;367defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;368defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;369defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;370defm : X86WriteRes<WriteVecMoveZ, [SKXPort05], 1, [1], 1>;371defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;372defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;373 374defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.375defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;376defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;377defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;378defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.379defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;380defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;381defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;382defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.383defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;384defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;385defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5, [1], 1, 5>; // Vector integer multiply.386defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 5, [1], 1, 6>;387defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>;388defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>;389defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.390defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;391defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;392defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.393defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;394defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;395defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;396defm : SKXWriteResPair<WriteVarShuffle, [SKXPort0,SKXPort5], 1, [1,1], 2, 5>; // Vector variable shuffles.397defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;398defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;399defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;400defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.401defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;402defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;403defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.404defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;405defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;406defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.407defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;408defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;409defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.410defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;411defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;412defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; // TODO: 512-bit ops require ports 0/1 to be joined.413defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.414 415// Vector integer shifts.416defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;417defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;418defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;419defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;420defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;421defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;422defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;423 424defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;425defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.426defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;427defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;428defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.429defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;430defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;431 432// Vector insert/extract operations.433def : WriteRes<WriteVecInsert, [SKXPort5]> {434 let Latency = 2;435 let NumMicroOps = 2;436 let ReleaseAtCycles = [2];437}438def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {439 let Latency = 6;440 let NumMicroOps = 2;441}442def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;443 444def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {445 let Latency = 3;446 let NumMicroOps = 2;447}448def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {449 let Latency = 2;450 let NumMicroOps = 3;451}452 453// Conversion between integer and float.454defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.455defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;456defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;457defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;458defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;459defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;460defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;461defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;462 463defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;464defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;465defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;466defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.467defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;468defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;469defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;470defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;471 472defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;473defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;474defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;475defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;476defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort5,SKXPort01], 5, [1,1], 2, 5>;477defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort5,SKXPort01], 5, [1,1], 2, 4>;478defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2, 7>;479defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort5,SKXPort05], 7, [1,1], 2, 7>;480 481defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;482defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;483defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;484defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;485defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;486defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;487 488defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;489defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;490defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;491defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;492defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;493defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;494 495// Strings instructions.496 497// Packed Compare Implicit Length Strings, Return Mask498def : WriteRes<WritePCmpIStrM, [SKXPort0]> {499 let Latency = 10;500 let NumMicroOps = 3;501 let ReleaseAtCycles = [3];502}503def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {504 let Latency = 16;505 let NumMicroOps = 4;506 let ReleaseAtCycles = [3,1];507}508 509// Packed Compare Explicit Length Strings, Return Mask510def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {511 let Latency = 19;512 let NumMicroOps = 9;513 let ReleaseAtCycles = [4,3,1,1];514}515def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {516 let Latency = 25;517 let NumMicroOps = 10;518 let ReleaseAtCycles = [4,3,1,1,1];519}520 521// Packed Compare Implicit Length Strings, Return Index522def : WriteRes<WritePCmpIStrI, [SKXPort0]> {523 let Latency = 10;524 let NumMicroOps = 3;525 let ReleaseAtCycles = [3];526}527def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {528 let Latency = 16;529 let NumMicroOps = 4;530 let ReleaseAtCycles = [3,1];531}532 533// Packed Compare Explicit Length Strings, Return Index534def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {535 let Latency = 18;536 let NumMicroOps = 8;537 let ReleaseAtCycles = [4,3,1];538}539def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {540 let Latency = 24;541 let NumMicroOps = 9;542 let ReleaseAtCycles = [4,3,1,1];543}544 545// MOVMSK Instructions.546def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }547def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }548def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }549def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }550 551// AES instructions.552def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.553 let Latency = 4;554 let NumMicroOps = 1;555 let ReleaseAtCycles = [1];556}557def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {558 let Latency = 10;559 let NumMicroOps = 2;560 let ReleaseAtCycles = [1,1];561}562 563def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.564 let Latency = 8;565 let NumMicroOps = 2;566 let ReleaseAtCycles = [2];567}568def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {569 let Latency = 14;570 let NumMicroOps = 3;571 let ReleaseAtCycles = [2,1];572}573 574def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.575 let Latency = 20;576 let NumMicroOps = 11;577 let ReleaseAtCycles = [3,6,2];578}579def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {580 let Latency = 25;581 let NumMicroOps = 11;582 let ReleaseAtCycles = [3,6,1,1];583}584 585// Carry-less multiplication instructions.586def : WriteRes<WriteCLMul, [SKXPort5]> {587 let Latency = 6;588 let NumMicroOps = 1;589 let ReleaseAtCycles = [1];590}591def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {592 let Latency = 12;593 let NumMicroOps = 2;594 let ReleaseAtCycles = [1,1];595}596 597// Catch-all for expensive system instructions.598def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;599 600// AVX2.601defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.602defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.603defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.604defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move.605defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.606 607// Old microcoded instructions that nobody use.608def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;609 610// Fence instructions.611def : WriteRes<WriteFence, [SKXPort23, SKXPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; }612 613// Load/store MXCSR.614def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }615def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }616 617// Nop, not very useful expect it provides a model for nops!618def : WriteRes<WriteNop, []>;619 620////////////////////////////////////////////////////////////////////////////////621// Horizontal add/sub instructions.622////////////////////////////////////////////////////////////////////////////////623 624defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort01], 6, [2,1], 3, 6>;625defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort01], 6, [2,1], 3, 7>;626defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;627defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;628defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;629 630// Remaining instrs.631 632def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {633 let Latency = 1;634 let NumMicroOps = 1;635 let ReleaseAtCycles = [1];636}637def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)kk",638 "KANDN(B|D|Q|W)kk",639 "KMOV(B|D|Q|W)kk",640 "KNOT(B|D|Q|W)kk",641 "KOR(B|D|Q|W)kk",642 "KXNOR(B|D|Q|W)kk",643 "KXOR(B|D|Q|W)kk",644 "KSET0(B|D|Q|W)", // Same as KXOR645 "KSET1(B|D|Q|W)", // Same as KXNOR646 "MMX_PADDS(B|W)rr",647 "MMX_PADDUS(B|W)rr",648 "MMX_PAVG(B|W)rr",649 "MMX_PCMPEQ(B|D|W)rr",650 "MMX_PCMPGT(B|D|W)rr",651 "MMX_P(MAX|MIN)SWrr",652 "MMX_P(MAX|MIN)UBrr",653 "MMX_PSUBS(B|W)rr",654 "MMX_PSUBUS(B|W)rr",655 "VPMOVB2M(Z|Z128|Z256)kr",656 "VPMOVD2M(Z|Z128|Z256)kr",657 "VPMOVQ2M(Z|Z128|Z256)kr",658 "VPMOVW2M(Z|Z128|Z256)kr")>;659 660def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {661 let Latency = 1;662 let NumMicroOps = 1;663 let ReleaseAtCycles = [1];664}665def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",666 "KMOV(B|D|Q|W)kr",667 "UCOM_F(P?)r")>;668 669def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {670 let Latency = 1;671 let NumMicroOps = 1;672 let ReleaseAtCycles = [1];673}674def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;675 676def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {677 let Latency = 1;678 let NumMicroOps = 1;679 let ReleaseAtCycles = [1];680}681def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;682 683def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {684 let Latency = 1;685 let NumMicroOps = 1;686 let ReleaseAtCycles = [1];687}688def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;689 690def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {691 let Latency = 1;692 let NumMicroOps = 1;693 let ReleaseAtCycles = [1];694}695def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;696 697def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {698 let Latency = 1;699 let NumMicroOps = 1;700 let ReleaseAtCycles = [1];701}702def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",703 "VBLENDMPS(Z128|Z256)rr",704 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",705 "(V?)PADD(B|D|Q|W)rr",706 "VPBLENDD(Y?)rri",707 "VPBLENDMB(Z128|Z256)rr",708 "VPBLENDMD(Z128|Z256)rr",709 "VPBLENDMQ(Z128|Z256)rr",710 "VPBLENDMW(Z128|Z256)rr",711 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",712 "VPTERNLOGD(Z|Z128|Z256)rri",713 "VPTERNLOGQ(Z|Z128|Z256)rri")>;714 715def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {716 let Latency = 1;717 let NumMicroOps = 1;718 let ReleaseAtCycles = [1];719}720def: InstRW<[SKXWriteResGroup10], (instrs SGDT64m,721 SIDT64m,722 SMSW16m,723 STRm,724 SYSCALL)>;725 726def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {727 let Latency = 1;728 let NumMicroOps = 2;729 let ReleaseAtCycles = [1,1];730}731def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;732def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",733 "ST_FP(32|64|80)m")>;734 735def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {736 let Latency = 2;737 let NumMicroOps = 2;738 let ReleaseAtCycles = [2];739}740def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;741 742def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {743 let Latency = 2;744 let NumMicroOps = 2;745 let ReleaseAtCycles = [2];746}747def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,748 MMX_MOVDQ2Qrr)>;749 750def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {751 let Latency = 2;752 let NumMicroOps = 2;753 let ReleaseAtCycles = [2];754}755def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,756 WAIT,757 XGETBV)>;758 759def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {760 let Latency = 2;761 let NumMicroOps = 2;762 let ReleaseAtCycles = [1,1];763}764def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;765 766def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {767 let Latency = 2;768 let NumMicroOps = 2;769 let ReleaseAtCycles = [1,1];770}771def: InstRW<[SKXWriteResGroup23], (instrs CWD,772 JCXZ, JECXZ, JRCXZ,773 ADC8i8, SBB8i8,774 ADC16i16, SBB16i16,775 ADC32i32, SBB32i32,776 ADC64i32, SBB64i32)>;777 778def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {779 let Latency = 2;780 let NumMicroOps = 3;781 let ReleaseAtCycles = [1,1,1];782}783def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;784 785def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {786 let Latency = 2;787 let NumMicroOps = 3;788 let ReleaseAtCycles = [1,1,1];789}790def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;791 792def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {793 let Latency = 2;794 let NumMicroOps = 3;795 let ReleaseAtCycles = [1,1,1];796}797def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,798 STOSB, STOSL, STOSQ, STOSW)>;799def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;800 801def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {802 let Latency = 2;803 let NumMicroOps = 5;804 let ReleaseAtCycles = [2,2,1];805}806def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;807 808def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {809 let Latency = 3;810 let NumMicroOps = 1;811 let ReleaseAtCycles = [1];812}813def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",814 "KORTEST(B|D|Q|W)kk",815 "KTEST(B|D|Q|W)kk")>;816 817def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {818 let Latency = 3;819 let NumMicroOps = 1;820 let ReleaseAtCycles = [1];821}822def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",823 "PEXT(32|64)rr")>;824 825def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {826 let Latency = 3;827 let NumMicroOps = 1;828 let ReleaseAtCycles = [1];829}830def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",831 "VALIGND(Z|Z128|Z256)rri",832 "VALIGNQ(Z|Z128|Z256)rri",833 "VPBROADCAST(B|W)rr",834 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;835 836def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {837 let Latency = 4;838 let NumMicroOps = 1;839 let ReleaseAtCycles = [1];840}841def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)kk",842 "KSHIFTL(B|D|Q|W)ki",843 "KSHIFTR(B|D|Q|W)ki",844 "KUNPCK(BW|DQ|WD)kk",845 "VCMPPD(Z|Z128|Z256)rri",846 "VCMPPS(Z|Z128|Z256)rri",847 "VCMP(SD|SS)Zrr",848 "VFPCLASS(PD|PS)(Z|Z128|Z256)ri",849 "VFPCLASS(SD|SS)Zri",850 "VPCMPB(Z|Z128|Z256)rri",851 "VPCMPD(Z|Z128|Z256)rri",852 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",853 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",854 "VPCMPQ(Z|Z128|Z256)rri",855 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",856 "VPCMPW(Z|Z128|Z256)rri",857 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;858 859def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {860 let Latency = 3;861 let NumMicroOps = 2;862 let ReleaseAtCycles = [1,1];863}864def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;865 866def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {867 let Latency = 3;868 let NumMicroOps = 3;869 let ReleaseAtCycles = [1,2];870}871def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;872 873def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {874 let Latency = 3;875 let NumMicroOps = 3;876 let ReleaseAtCycles = [2,1];877}878def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;879 880def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5]> {881 let Latency = 2;882 let NumMicroOps = 2;883 let ReleaseAtCycles = [2];884}885def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,886 MMX_PACKSSWBrr,887 MMX_PACKUSWBrr)>;888 889def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {890 let Latency = 3;891 let NumMicroOps = 3;892 let ReleaseAtCycles = [1,2];893}894def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;895 896def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {897 let Latency = 2;898 let NumMicroOps = 3;899 let ReleaseAtCycles = [1,2];900}901def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,902 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;903 904def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {905 let Latency = 5;906 let NumMicroOps = 8;907 let ReleaseAtCycles = [2,4,2];908}909def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;910 911def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {912 let Latency = 6;913 let NumMicroOps = 8;914 let ReleaseAtCycles = [2,4,2];915}916def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;917 918def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {919 let Latency = 3;920 let NumMicroOps = 3;921 let ReleaseAtCycles = [1,1,1];922}923def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;924 925def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {926 let Latency = 3;927 let NumMicroOps = 4;928 let ReleaseAtCycles = [1,1,1,1];929}930def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;931 932def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {933 let Latency = 3;934 let NumMicroOps = 4;935 let ReleaseAtCycles = [1,1,1,1];936}937def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;938 939def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {940 let Latency = 4;941 let NumMicroOps = 1;942 let ReleaseAtCycles = [1];943}944def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;945 946def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {947 let Latency = 4;948 let NumMicroOps = 1;949 let ReleaseAtCycles = [1];950}951def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",952 "VCVTPD2UQQ(Z128|Z256)rr",953 "VCVTPS2DQ(Y|Z128|Z256)rr",954 "(V?)CVTPS2DQrr",955 "VCVTPS2UDQ(Z128|Z256)rr",956 "VCVTTPD2QQ(Z128|Z256)rr",957 "VCVTTPD2UQQ(Z128|Z256)rr",958 "VCVTTPS2DQ(Z128|Z256)rr",959 "(V?)CVTTPS2DQrr",960 "VCVTTPS2UDQ(Z128|Z256)rr")>;961 962def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {963 let Latency = 4;964 let NumMicroOps = 1;965 let ReleaseAtCycles = [1];966}967def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,968 VCVTPD2UQQZrr,969 VCVTPS2DQZrr,970 VCVTPS2UDQZrr,971 VCVTTPD2QQZrr,972 VCVTTPD2UQQZrr,973 VCVTTPS2DQZrr,974 VCVTTPS2UDQZrr)>;975 976def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {977 let Latency = 4;978 let NumMicroOps = 2;979 let ReleaseAtCycles = [2];980}981def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",982 "VEXPANDPS(Z|Z128|Z256)rr",983 "VPEXPANDD(Z|Z128|Z256)rr",984 "VPEXPANDQ(Z|Z128|Z256)rr",985 "VPMOVDB(Z|Z128|Z256)rr",986 "VPMOVDW(Z|Z128|Z256)rr",987 "VPMOVQB(Z|Z128|Z256)rr",988 "VPMOVQW(Z|Z128|Z256)rr",989 "VPMOVSDB(Z|Z128|Z256)rr",990 "VPMOVSDW(Z|Z128|Z256)rr",991 "VPMOVSQB(Z|Z128|Z256)rr",992 "VPMOVSQD(Z|Z128|Z256)rr",993 "VPMOVSQW(Z|Z128|Z256)rr",994 "VPMOVSWB(Z|Z128|Z256)rr",995 "VPMOVUSDB(Z|Z128|Z256)rr",996 "VPMOVUSDW(Z|Z128|Z256)rr",997 "VPMOVUSQB(Z|Z128|Z256)rr",998 "VPMOVUSQD(Z|Z128|Z256)rr",999 "VPMOVUSWB(Z|Z128|Z256)rr",1000 "VPMOVWB(Z|Z128|Z256)rr")>;1001 1002def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {1003 let Latency = 4;1004 let NumMicroOps = 3;1005 let ReleaseAtCycles = [1,1,1];1006}1007def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",1008 "IST_F(16|32)m",1009 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;1010 1011def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {1012 let Latency = 4;1013 let NumMicroOps = 4;1014 let ReleaseAtCycles = [4];1015}1016def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;1017 1018def SKXWriteResGroup56 : SchedWriteRes<[]> {1019 let Latency = 0;1020 let NumMicroOps = 4;1021 let ReleaseAtCycles = [];1022}1023def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;1024 1025def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {1026 let Latency = 4;1027 let NumMicroOps = 4;1028 let ReleaseAtCycles = [1,1,2];1029}1030def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;1031 1032def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort01]> {1033 let Latency = 5;1034 let NumMicroOps = 2;1035 let ReleaseAtCycles = [1,1];1036}1037def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",1038 "MMX_CVT(T?)PS2PIrr",1039 "VCVTDQ2PDZ128rr",1040 "VCVTPD2DQZ128rr",1041 "(V?)CVT(T?)PD2DQrr",1042 "VCVTPD2UDQZ128rr",1043 "VCVTPS2PDZ128rr",1044 "(V?)CVTPS2PDrr",1045 "VCVTPS2QQZ128rr",1046 "VCVTPS2UQQZ128rr",1047 "VCVTQQ2PSZ128rr",1048 "(V?)CVTSI(64)?2SDrr",1049 "VCVTSI2SSZrr",1050 "(V?)CVTSI2SSrr",1051 "VCVTSI(64)?2SDZrr",1052 "VCVTSS2SDZrr",1053 "(V?)CVTSS2SDrr",1054 "VCVTTPD2DQZ128rr",1055 "VCVTTPD2UDQZ128rr",1056 "VCVTTPS2QQZ128rr",1057 "VCVTTPS2UQQZ128rr",1058 "VCVTUDQ2PDZ128rr",1059 "VCVTUQQ2PSZ128rr",1060 "VCVTUSI2SSZrr",1061 "VCVTUSI(64)?2SDZrr")>;1062 1063def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {1064 let Latency = 5;1065 let NumMicroOps = 3;1066 let ReleaseAtCycles = [2,1];1067}1068def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;1069 1070def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {1071 let Latency = 5;1072 let NumMicroOps = 3;1073 let ReleaseAtCycles = [1,1,1];1074}1075def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;1076 1077def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort01]> {1078 let Latency = 5;1079 let NumMicroOps = 3;1080 let ReleaseAtCycles = [1,1,1];1081}1082def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",1083 "VCVTPS2PHZ256mr(b?)",1084 "VCVTPS2PHZmr(b?)")>;1085 1086def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {1087 let Latency = 5;1088 let NumMicroOps = 4;1089 let ReleaseAtCycles = [1,2,1];1090}1091def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",1092 "VPMOVDW(Z|Z128|Z256)mr(b?)",1093 "VPMOVQB(Z|Z128|Z256)mr(b?)",1094 "VPMOVQW(Z|Z128|Z256)mr(b?)",1095 "VPMOVSDB(Z|Z128|Z256)mr(b?)",1096 "VPMOVSDW(Z|Z128|Z256)mr(b?)",1097 "VPMOVSQB(Z|Z128|Z256)mr(b?)",1098 "VPMOVSQD(Z|Z128|Z256)mr(b?)",1099 "VPMOVSQW(Z|Z128|Z256)mr(b?)",1100 "VPMOVSWB(Z|Z128|Z256)mr(b?)",1101 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",1102 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",1103 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",1104 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",1105 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",1106 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",1107 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;1108 1109def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {1110 let Latency = 5;1111 let NumMicroOps = 5;1112 let ReleaseAtCycles = [1,4];1113}1114def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;1115 1116def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {1117 let Latency = 5;1118 let NumMicroOps = 6;1119 let ReleaseAtCycles = [1,1,4];1120}1121def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;1122 1123def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {1124 let Latency = 6;1125 let NumMicroOps = 1;1126 let ReleaseAtCycles = [1];1127}1128def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,1129 VPBROADCASTDrm,1130 VPBROADCASTQrm)>;1131def: InstRW<[SKXWriteResGroup71], (instregex "(V?)MOVSHDUPrm",1132 "(V?)MOVSLDUPrm",1133 "(V?)MOVDDUPrm")>;1134 1135def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {1136 let Latency = 6;1137 let NumMicroOps = 2;1138 let ReleaseAtCycles = [2];1139}1140def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;1141def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",1142 "VCOMPRESSPS(Z|Z128|Z256)rr",1143 "VPCOMPRESSD(Z|Z128|Z256)rr",1144 "VPCOMPRESSQ(Z|Z128|Z256)rr",1145 "VPERMW(Z|Z128|Z256)rr")>;1146 1147def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {1148 let Latency = 6;1149 let NumMicroOps = 2;1150 let ReleaseAtCycles = [1,1];1151}1152def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,1153 MMX_PADDSWrm,1154 MMX_PADDUSBrm,1155 MMX_PADDUSWrm,1156 MMX_PAVGBrm,1157 MMX_PAVGWrm,1158 MMX_PCMPEQBrm,1159 MMX_PCMPEQDrm,1160 MMX_PCMPEQWrm,1161 MMX_PCMPGTBrm,1162 MMX_PCMPGTDrm,1163 MMX_PCMPGTWrm,1164 MMX_PMAXSWrm,1165 MMX_PMAXUBrm,1166 MMX_PMINSWrm,1167 MMX_PMINUBrm,1168 MMX_PSUBSBrm,1169 MMX_PSUBSWrm,1170 MMX_PSUBUSBrm,1171 MMX_PSUBUSWrm)>;1172 1173def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {1174 let Latency = 6;1175 let NumMicroOps = 2;1176 let ReleaseAtCycles = [1,1];1177}1178def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;1179def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;1180 1181def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {1182 let Latency = 6;1183 let NumMicroOps = 2;1184 let ReleaseAtCycles = [1,1];1185}1186def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",1187 "MOVBE(16|32|64)rm")>;1188 1189def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {1190 let Latency = 6;1191 let NumMicroOps = 2;1192 let ReleaseAtCycles = [1,1];1193}1194def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;1195def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;1196 1197def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {1198 let Latency = 6;1199 let NumMicroOps = 2;1200 let ReleaseAtCycles = [1,1];1201}1202def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;1203def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;1204 1205def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort01]> {1206 let Latency = 6;1207 let NumMicroOps = 3;1208 let ReleaseAtCycles = [2,1];1209}1210def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",1211 "VCVTSI642SSZrr",1212 "VCVTUSI642SSZrr")>;1213 1214def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {1215 let Latency = 6;1216 let NumMicroOps = 4;1217 let ReleaseAtCycles = [1,1,1,1];1218}1219def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;1220 1221def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {1222 let Latency = 6;1223 let NumMicroOps = 4;1224 let ReleaseAtCycles = [1,1,1,1];1225}1226def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",1227 "SHL(8|16|32|64)m(1|i)",1228 "SHR(8|16|32|64)m(1|i)")>;1229 1230def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {1231 let Latency = 6;1232 let NumMicroOps = 4;1233 let ReleaseAtCycles = [1,1,1,1];1234}1235def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",1236 "PUSH(16|32|64)rmm")>;1237 1238def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {1239 let Latency = 6;1240 let NumMicroOps = 6;1241 let ReleaseAtCycles = [1,5];1242}1243def: InstRW<[SKXWriteResGroup88], (instrs STD)>;1244 1245def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {1246 let Latency = 7;1247 let NumMicroOps = 1;1248 let ReleaseAtCycles = [1];1249}1250def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;1251def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,1252 VBROADCASTI128rm,1253 VBROADCASTSDYrm,1254 VBROADCASTSSYrm,1255 VMOVDDUPYrm,1256 VMOVSHDUPYrm,1257 VMOVSLDUPYrm,1258 VPBROADCASTDYrm,1259 VPBROADCASTQYrm)>;1260 1261def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {1262 let Latency = 7;1263 let NumMicroOps = 2;1264 let ReleaseAtCycles = [1,1];1265}1266def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;1267 1268def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {1269 let Latency = 7;1270 let NumMicroOps = 2;1271 let ReleaseAtCycles = [1,1];1272}1273def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",1274 "VMOVSSZrm(b?)")>;1275 1276def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {1277 let Latency = 6;1278 let NumMicroOps = 2;1279 let ReleaseAtCycles = [1,1];1280}1281def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",1282 "(V?)PMOV(SX|ZX)BQrm",1283 "(V?)PMOV(SX|ZX)BWrm",1284 "(V?)PMOV(SX|ZX)DQrm",1285 "(V?)PMOV(SX|ZX)WDrm",1286 "(V?)PMOV(SX|ZX)WQrm")>;1287 1288def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort01]> {1289 let Latency = 7;1290 let NumMicroOps = 2;1291 let ReleaseAtCycles = [1,1];1292}1293def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",1294 "VCVTPD2DQ(Y|Z256)rr",1295 "VCVTPD2UDQZ256rr",1296 "VCVTPS2PD(Y|Z256)rr",1297 "VCVTPS2QQZ256rr",1298 "VCVTPS2UQQZ256rr",1299 "VCVTQQ2PSZ256rr",1300 "VCVTTPD2DQ(Y|Z256)rr",1301 "VCVTTPD2UDQZ256rr",1302 "VCVTTPS2QQZ256rr",1303 "VCVTTPS2UQQZ256rr",1304 "VCVTUDQ2PDZ256rr",1305 "VCVTUQQ2PSZ256rr")>;1306 1307def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {1308 let Latency = 7;1309 let NumMicroOps = 2;1310 let ReleaseAtCycles = [1,1];1311}1312def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,1313 VCVTPD2DQZrr,1314 VCVTPD2UDQZrr,1315 VCVTPS2PDZrr,1316 VCVTPS2QQZrr,1317 VCVTPS2UQQZrr,1318 VCVTQQ2PSZrr,1319 VCVTTPD2DQZrr,1320 VCVTTPD2UDQZrr,1321 VCVTTPS2QQZrr,1322 VCVTTPS2UQQZrr,1323 VCVTUDQ2PDZrr,1324 VCVTUQQ2PSZrr)>;1325 1326def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {1327 let Latency = 7;1328 let NumMicroOps = 2;1329 let ReleaseAtCycles = [1,1];1330}1331def: InstRW<[SKXWriteResGroup95], (instrs VPBLENDDrmi)>;1332def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],1333 (instregex "VBLENDMPDZ128rm(b?)",1334 "VBLENDMPSZ128rm(b?)",1335 "VBROADCASTI32X2Z128rm(b?)",1336 "VBROADCASTSSZ128rm(b?)",1337 "VINSERT(F|I)128rmi",1338 "VMOVAPDZ128rm(b?)",1339 "VMOVAPSZ128rm(b?)",1340 "VMOVDDUPZ128rm(b?)",1341 "VMOVDQA32Z128rm(b?)",1342 "VMOVDQA64Z128rm(b?)",1343 "VMOVDQU16Z128rm(b?)",1344 "VMOVDQU32Z128rm(b?)",1345 "VMOVDQU64Z128rm(b?)",1346 "VMOVDQU8Z128rm(b?)",1347 "VMOVSHDUPZ128rm(b?)",1348 "VMOVSLDUPZ128rm(b?)",1349 "VMOVUPDZ128rm(b?)",1350 "VMOVUPSZ128rm(b?)",1351 "VPADD(B|D|Q|W)Z128rm(b?)",1352 "(V?)PADD(B|D|Q|W)rm",1353 "VPBLENDM(B|D|Q|W)Z128rm(b?)",1354 "VPBROADCASTDZ128rm(b?)",1355 "VPBROADCASTQZ128rm(b?)",1356 "VPSUB(B|D|Q|W)Z128rm(b?)",1357 "(V?)PSUB(B|D|Q|W)rm",1358 "VPTERNLOGDZ128rm(b?)i",1359 "VPTERNLOGQZ128rm(b?)i")>;1360 1361def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {1362 let Latency = 7;1363 let NumMicroOps = 3;1364 let ReleaseAtCycles = [2,1];1365}1366def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,1367 MMX_PACKSSWBrm,1368 MMX_PACKUSWBrm)>;1369 1370def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {1371 let Latency = 7;1372 let NumMicroOps = 3;1373 let ReleaseAtCycles = [2,1];1374}1375def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2WZ128rr",1376 "VPERMI2WZ256rr",1377 "VPERMI2WZrr",1378 "VPERMT2WZ128rr",1379 "VPERMT2WZ256rr",1380 "VPERMT2WZrr")>;1381 1382def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {1383 let Latency = 7;1384 let NumMicroOps = 3;1385 let ReleaseAtCycles = [1,2];1386}1387def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,1388 SCASB, SCASL, SCASQ, SCASW)>;1389 1390def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort01]> {1391 let Latency = 7;1392 let NumMicroOps = 3;1393 let ReleaseAtCycles = [1,1,1];1394}1395def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",1396 "VCVT(T?)SS2USI64Zrr")>;1397 1398def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {1399 let Latency = 7;1400 let NumMicroOps = 3;1401 let ReleaseAtCycles = [1,1,1];1402}1403def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;1404 1405def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {1406 let Latency = 7;1407 let NumMicroOps = 3;1408 let ReleaseAtCycles = [1,1,1];1409}1410def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;1411 1412def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {1413 let Latency = 7;1414 let NumMicroOps = 3;1415 let ReleaseAtCycles = [1,1,1];1416}1417def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;1418 1419def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {1420 let Latency = 7;1421 let NumMicroOps = 4;1422 let ReleaseAtCycles = [1,2,1];1423}1424def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",1425 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",1426 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",1427 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;1428 1429def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {1430 let Latency = 7;1431 let NumMicroOps = 5;1432 let ReleaseAtCycles = [1,1,1,2];1433}1434def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",1435 "ROR(8|16|32|64)m(1|i)")>;1436 1437def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {1438 let Latency = 2;1439 let NumMicroOps = 2;1440 let ReleaseAtCycles = [2];1441}1442def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,1443 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;1444 1445def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {1446 let Latency = 7;1447 let NumMicroOps = 5;1448 let ReleaseAtCycles = [1,1,1,2];1449}1450def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;1451 1452def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {1453 let Latency = 7;1454 let NumMicroOps = 5;1455 let ReleaseAtCycles = [1,1,1,1,1];1456}1457def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;1458def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;1459 1460def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {1461 let Latency = 7;1462 let NumMicroOps = 7;1463 let ReleaseAtCycles = [1,2,2,2];1464}1465def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,1466 VPSCATTERQQZ128mr,1467 VSCATTERDPDZ128mr,1468 VSCATTERQPDZ128mr)>;1469 1470def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {1471 let Latency = 7;1472 let NumMicroOps = 7;1473 let ReleaseAtCycles = [1,3,1,2];1474}1475def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;1476 1477def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {1478 let Latency = 7;1479 let NumMicroOps = 11;1480 let ReleaseAtCycles = [1,4,4,2];1481}1482def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,1483 VPSCATTERQQZ256mr,1484 VSCATTERDPDZ256mr,1485 VSCATTERQPDZ256mr)>;1486 1487def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {1488 let Latency = 7;1489 let NumMicroOps = 19;1490 let ReleaseAtCycles = [1,8,8,2];1491}1492def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,1493 VPSCATTERQDZmr,1494 VPSCATTERQQZmr,1495 VSCATTERDPDZmr,1496 VSCATTERQPSZmr,1497 VSCATTERQPDZmr)>;1498 1499def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {1500 let Latency = 7;1501 let NumMicroOps = 36;1502 let ReleaseAtCycles = [1,16,1,16,2];1503}1504def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;1505 1506def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {1507 let Latency = 8;1508 let NumMicroOps = 2;1509 let ReleaseAtCycles = [1,1];1510}1511def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",1512 "PEXT(32|64)rm")>;1513 1514def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {1515 let Latency = 8;1516 let NumMicroOps = 2;1517 let ReleaseAtCycles = [1,1];1518}1519def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",1520 "VPBROADCASTB(Z|Z256)rm(b?)",1521 "VPBROADCASTW(Z|Z256)rm(b?)")>;1522def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,1523 VPBROADCASTWYrm,1524 VPMOVSXBDYrm,1525 VPMOVSXBQYrm,1526 VPMOVSXWQYrm)>;1527 1528def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {1529 let Latency = 8;1530 let NumMicroOps = 2;1531 let ReleaseAtCycles = [1,1];1532}1533def: InstRW<[SKXWriteResGroup121], (instrs VPBLENDDYrmi)>;1534def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],1535 (instregex "VBLENDMPD(Z|Z256)rm(b?)",1536 "VBLENDMPS(Z|Z256)rm(b?)",1537 "VBROADCASTF32X2Z256rm(b?)",1538 "VBROADCASTF32X2Zrm(b?)",1539 "VBROADCASTF32X4Z256rm(b?)",1540 "VBROADCASTF32X4Zrm(b?)",1541 "VBROADCASTF32X8Zrm(b?)",1542 "VBROADCASTF64X2Z256rm(b?)",1543 "VBROADCASTF64X2Zrm(b?)",1544 "VBROADCASTF64X4Zrm(b?)",1545 "VBROADCASTI32X2Z256rm(b?)",1546 "VBROADCASTI32X2Zrm(b?)",1547 "VBROADCASTI32X4Z256rm(b?)",1548 "VBROADCASTI32X4Zrm(b?)",1549 "VBROADCASTI32X8Zrm(b?)",1550 "VBROADCASTI64X2Z256rm(b?)",1551 "VBROADCASTI64X2Zrm(b?)",1552 "VBROADCASTI64X4Zrm(b?)",1553 "VBROADCASTSD(Z|Z256)rm(b?)",1554 "VBROADCASTSS(Z|Z256)rm(b?)",1555 "VINSERTF32X4(Z|Z256)rm(b?)",1556 "VINSERTF32X8Zrm(b?)",1557 "VINSERTF64X2(Z|Z256)rm(b?)",1558 "VINSERTF64X4Zrm(b?)",1559 "VINSERTI32X4(Z|Z256)rm(b?)",1560 "VINSERTI32X8Zrm(b?)",1561 "VINSERTI64X2(Z|Z256)rm(b?)",1562 "VINSERTI64X4Zrm(b?)",1563 "VMOVAPD(Z|Z256)rm(b?)",1564 "VMOVAPS(Z|Z256)rm(b?)",1565 "VMOVDDUP(Z|Z256)rm(b?)",1566 "VMOVDQA32(Z|Z256)rm(b?)",1567 "VMOVDQA64(Z|Z256)rm(b?)",1568 "VMOVDQU16(Z|Z256)rm(b?)",1569 "VMOVDQU32(Z|Z256)rm(b?)",1570 "VMOVDQU64(Z|Z256)rm(b?)",1571 "VMOVDQU8(Z|Z256)rm(b?)",1572 "VMOVSHDUP(Z|Z256)rm(b?)",1573 "VMOVSLDUP(Z|Z256)rm(b?)",1574 "VMOVUPD(Z|Z256)rm(b?)",1575 "VMOVUPS(Z|Z256)rm(b?)",1576 "VPADD(B|D|Q|W)Yrm",1577 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",1578 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",1579 "VPBROADCASTD(Z|Z256)rm(b?)",1580 "VPBROADCASTQ(Z|Z256)rm(b?)",1581 "VPSUB(B|D|Q|W)Yrm",1582 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",1583 "VPTERNLOGD(Z|Z256)rm(b?)i",1584 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;1585 1586def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {1587 let Latency = 8;1588 let NumMicroOps = 4;1589 let ReleaseAtCycles = [1,2,1];1590}1591def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;1592 1593def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {1594 let Latency = 8;1595 let NumMicroOps = 5;1596 let ReleaseAtCycles = [1,1,1,2];1597}1598def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",1599 "RCR(8|16|32|64)m(1|i)")>;1600 1601def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {1602 let Latency = 8;1603 let NumMicroOps = 6;1604 let ReleaseAtCycles = [1,1,1,3];1605}1606def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",1607 "ROR(8|16|32|64)mCL",1608 "SAR(8|16|32|64)mCL",1609 "SHL(8|16|32|64)mCL",1610 "SHR(8|16|32|64)mCL")>;1611 1612def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {1613 let Latency = 8;1614 let NumMicroOps = 6;1615 let ReleaseAtCycles = [1,1,1,2,1];1616}1617def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;1618 1619def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {1620 let Latency = 8;1621 let NumMicroOps = 8;1622 let ReleaseAtCycles = [1,2,1,2,2];1623}1624def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,1625 VPSCATTERQDZ256mr,1626 VSCATTERQPSZ128mr,1627 VSCATTERQPSZ256mr)>;1628 1629def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {1630 let Latency = 8;1631 let NumMicroOps = 12;1632 let ReleaseAtCycles = [1,4,1,4,2];1633}1634def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,1635 VSCATTERDPSZ128mr)>;1636 1637def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {1638 let Latency = 8;1639 let NumMicroOps = 20;1640 let ReleaseAtCycles = [1,8,1,8,2];1641}1642def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,1643 VSCATTERDPSZ256mr)>;1644 1645def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {1646 let Latency = 8;1647 let NumMicroOps = 36;1648 let ReleaseAtCycles = [1,16,1,16,2];1649}1650def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;1651 1652def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {1653 let Latency = 9;1654 let NumMicroOps = 2;1655 let ReleaseAtCycles = [1,1];1656}1657def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;1658 1659def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {1660 let Latency = 9;1661 let NumMicroOps = 2;1662 let ReleaseAtCycles = [1,1];1663}1664def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,1665 VPMOVSXDQYrm,1666 VPMOVSXWDYrm,1667 VPMOVZXWDYrm)>;1668def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",1669 "VFPCLASSSDZm(b?)i",1670 "VFPCLASSSSZm(b?)i",1671 "(V?)PCMPGTQrm",1672 "VPERMI2DZ128rm(b?)",1673 "VPERMI2PDZ128rm(b?)",1674 "VPERMI2PSZ128rm(b?)",1675 "VPERMI2QZ128rm(b?)",1676 "VPERMT2DZ128rm(b?)",1677 "VPERMT2PDZ128rm(b?)",1678 "VPERMT2PSZ128rm(b?)",1679 "VPERMT2QZ128rm(b?)",1680 "VPMAXSQZ128rm(b?)",1681 "VPMAXUQZ128rm(b?)",1682 "VPMINSQZ128rm(b?)",1683 "VPMINUQZ128rm(b?)")>;1684 1685def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {1686 let Latency = 10;1687 let NumMicroOps = 2;1688 let ReleaseAtCycles = [1,1];1689}1690def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",1691 "VCMP(SD|SS)Zrm",1692 "VFPCLASSPDZ128m(b?)i",1693 "VFPCLASSPSZ128m(b?)i",1694 "VPCMPBZ128rm(b?)i",1695 "VPCMPDZ128rm(b?)i",1696 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",1697 "VPCMPGT(B|D|Q|W)Z128rm(b?)",1698 "VPCMPQZ128rm(b?)i",1699 "VPCMPU(B|D|Q|W)Z128rm(b?)i",1700 "VPCMPWZ128rm(b?)i",1701 "VPTESTMBZ128rm(b?)",1702 "VPTESTMDZ128rm(b?)",1703 "VPTESTMQZ128rm(b?)",1704 "VPTESTMWZ128rm(b?)",1705 "VPTESTNMBZ128rm(b?)",1706 "VPTESTNMDZ128rm(b?)",1707 "VPTESTNMQZ128rm(b?)",1708 "VPTESTNMWZ128rm(b?)")>;1709 1710def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort01]> {1711 let Latency = 9;1712 let NumMicroOps = 2;1713 let ReleaseAtCycles = [1,1];1714}1715def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",1716 "(V?)CVTPS2PDrm")>;1717 1718def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {1719 let Latency = 9;1720 let NumMicroOps = 4;1721 let ReleaseAtCycles = [2,1,1];1722}1723def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",1724 "(V?)PHSUBSWrm")>;1725 1726def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {1727 let Latency = 9;1728 let NumMicroOps = 5;1729 let ReleaseAtCycles = [1,2,1,1];1730}1731def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",1732 "LSL(16|32|64)rm")>;1733 1734def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {1735 let Latency = 10;1736 let NumMicroOps = 2;1737 let ReleaseAtCycles = [1,1];1738}1739def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;1740def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",1741 "ILD_F(16|32|64)m",1742 "VALIGND(Z|Z256)rm(b?)i",1743 "VALIGNQ(Z|Z256)rm(b?)i",1744 "VPMAXSQ(Z|Z256)rm(b?)",1745 "VPMAXUQ(Z|Z256)rm(b?)",1746 "VPMINSQ(Z|Z256)rm(b?)",1747 "VPMINUQ(Z|Z256)rm(b?)")>;1748 1749def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {1750 let Latency = 11;1751 let NumMicroOps = 2;1752 let ReleaseAtCycles = [1,1];1753}1754def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",1755 "VCMPPS(Z|Z256)rm(b?)i",1756 "VFPCLASSPD(Z|Z256)m(b?)i",1757 "VFPCLASSPS(Z|Z256)m(b?)i",1758 "VPCMPB(Z|Z256)rm(b?)i",1759 "VPCMPD(Z|Z256)rm(b?)i",1760 "VPCMPEQB(Z|Z256)rm(b?)",1761 "VPCMPEQD(Z|Z256)rm(b?)",1762 "VPCMPEQQ(Z|Z256)rm(b?)",1763 "VPCMPEQW(Z|Z256)rm(b?)",1764 "VPCMPGTB(Z|Z256)rm(b?)",1765 "VPCMPGTD(Z|Z256)rm(b?)",1766 "VPCMPGTQ(Z|Z256)rm(b?)",1767 "VPCMPGTW(Z|Z256)rm(b?)",1768 "VPCMPQ(Z|Z256)rm(b?)i",1769 "VPCMPU(B|D|Q|W)Z256rm(b?)i",1770 "VPCMPU(B|D|Q|W)Zrm(b?)i",1771 "VPCMPW(Z|Z256)rm(b?)i",1772 "VPTESTM(B|D|Q|W)Z256rm(b?)",1773 "VPTESTM(B|D|Q|W)Zrm(b?)",1774 "VPTESTNM(B|D|Q|W)Z256rm(b?)",1775 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;1776 1777def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort01]> {1778 let Latency = 10;1779 let NumMicroOps = 2;1780 let ReleaseAtCycles = [1,1];1781}1782def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",1783 "VCVTDQ2PSZ128rm(b?)",1784 "(V?)CVTDQ2PSrm",1785 "VCVTPD2QQZ128rm(b?)",1786 "VCVTPD2UQQZ128rm(b?)",1787 "VCVTPH2PSZ128rm(b?)",1788 "VCVTPS2DQZ128rm(b?)",1789 "(V?)CVTPS2DQrm",1790 "VCVTPS2PDZ128rm(b?)",1791 "VCVTPS2QQZ128rm(b?)",1792 "VCVTPS2UDQZ128rm(b?)",1793 "VCVTPS2UQQZ128rm(b?)",1794 "VCVTQQ2PDZ128rm(b?)",1795 "VCVTQQ2PSZ128rm(b?)",1796 "VCVTSS2SDZrm",1797 "(V?)CVTSS2SDrm",1798 "VCVTTPD2QQZ128rm(b?)",1799 "VCVTTPD2UQQZ128rm(b?)",1800 "VCVTTPS2DQZ128rm(b?)",1801 "(V?)CVTTPS2DQrm",1802 "VCVTTPS2QQZ128rm(b?)",1803 "VCVTTPS2UDQZ128rm(b?)",1804 "VCVTTPS2UQQZ128rm(b?)",1805 "VCVTUDQ2PDZ128rm(b?)",1806 "VCVTUDQ2PSZ128rm(b?)",1807 "VCVTUQQ2PDZ128rm(b?)",1808 "VCVTUQQ2PSZ128rm(b?)")>;1809 1810def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {1811 let Latency = 10;1812 let NumMicroOps = 3;1813 let ReleaseAtCycles = [2,1];1814}1815def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",1816 "VEXPANDPSZ128rm(b?)",1817 "VPEXPANDDZ128rm(b?)",1818 "VPEXPANDQZ128rm(b?)")>;1819 1820def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {1821 let Latency = 10;1822 let NumMicroOps = 4;1823 let ReleaseAtCycles = [2,1,1];1824}1825def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,1826 VPHSUBSWYrm)>;1827 1828def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {1829 let Latency = 10;1830 let NumMicroOps = 8;1831 let ReleaseAtCycles = [1,1,1,1,1,3];1832}1833def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;1834 1835def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {1836 let Latency = 11;1837 let NumMicroOps = 2;1838 let ReleaseAtCycles = [1,1];1839}1840def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;1841 1842def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort01]> {1843 let Latency = 11;1844 let NumMicroOps = 2;1845 let ReleaseAtCycles = [1,1];1846}1847def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,1848 VCVTPS2PDYrm)>;1849def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",1850 "VCVTPH2PS(Z|Z256)rm(b?)",1851 "VCVTPS2PD(Z|Z256)rm(b?)",1852 "VCVTQQ2PD(Z|Z256)rm(b?)",1853 "VCVTQQ2PSZ256rm(b?)",1854 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",1855 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",1856 "VCVT(T?)PS2DQYrm",1857 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",1858 "VCVT(T?)PS2QQZ256rm(b?)",1859 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",1860 "VCVT(T?)PS2UQQZ256rm(b?)",1861 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",1862 "VCVTUQQ2PD(Z|Z256)rm(b?)",1863 "VCVTUQQ2PSZ256rm(b?)")>;1864 1865def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {1866 let Latency = 11;1867 let NumMicroOps = 3;1868 let ReleaseAtCycles = [2,1];1869}1870def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",1871 "VEXPANDPD(Z|Z256)rm(b?)",1872 "VEXPANDPS(Z|Z256)rm(b?)",1873 "VPEXPANDD(Z|Z256)rm(b?)",1874 "VPEXPANDQ(Z|Z256)rm(b?)")>;1875 1876def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {1877 let Latency = 11;1878 let NumMicroOps = 3;1879 let ReleaseAtCycles = [1,1,1];1880}1881def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;1882 1883def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {1884 let Latency = 11;1885 let NumMicroOps = 3;1886 let ReleaseAtCycles = [1,1,1];1887}1888def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2DQrm,1889 CVTTPD2DQrm,1890 MMX_CVTPD2PIrm,1891 MMX_CVTTPD2PIrm)>;1892 1893def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {1894 let Latency = 11;1895 let NumMicroOps = 4;1896 let ReleaseAtCycles = [2,1,1];1897}1898def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;1899 1900def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {1901 let Latency = 11;1902 let NumMicroOps = 7;1903 let ReleaseAtCycles = [2,3,2];1904}1905def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",1906 "RCR(16|32|64)rCL")>;1907 1908def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {1909 let Latency = 11;1910 let NumMicroOps = 9;1911 let ReleaseAtCycles = [1,5,1,2];1912}1913def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;1914 1915def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {1916 let Latency = 11;1917 let NumMicroOps = 11;1918 let ReleaseAtCycles = [2,9];1919}1920def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;1921 1922def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {1923 let Latency = 15;1924 let NumMicroOps = 3;1925 let ReleaseAtCycles = [3];1926}1927def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;1928 1929def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {1930 let Latency = 15;1931 let NumMicroOps = 3;1932 let ReleaseAtCycles = [3];1933}1934def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;1935 1936def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {1937 let Latency = 12;1938 let NumMicroOps = 3;1939 let ReleaseAtCycles = [2,1];1940}1941def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;1942 1943def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort01]> {1944 let Latency = 12;1945 let NumMicroOps = 3;1946 let ReleaseAtCycles = [1,1,1];1947}1948def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",1949 "VCVT(T?)SS2USI64Zrm(b?)")>;1950 1951def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {1952 let Latency = 12;1953 let NumMicroOps = 3;1954 let ReleaseAtCycles = [1,1,1];1955}1956def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",1957 "VCVT(T?)PS2UQQZrm(b?)")>;1958 1959def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {1960 let Latency = 13;1961 let NumMicroOps = 3;1962 let ReleaseAtCycles = [2,1];1963}1964def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",1965 "VPERMWZ256rm(b?)",1966 "VPERMWZrm(b?)")>;1967 1968def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {1969 let Latency = 13;1970 let NumMicroOps = 3;1971 let ReleaseAtCycles = [1,1,1];1972}1973def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;1974 1975def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {1976 let Latency = 13;1977 let NumMicroOps = 4;1978 let ReleaseAtCycles = [2,1,1];1979}1980def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2WZ128rm(b?)",1981 "VPERMT2WZ128rm(b?)")>;1982 1983def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {1984 let Latency = 14;1985 let NumMicroOps = 3;1986 let ReleaseAtCycles = [1,1,1];1987}1988def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;1989 1990def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {1991 let Latency = 14;1992 let NumMicroOps = 3;1993 let ReleaseAtCycles = [1,1,1];1994}1995def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",1996 "VCVTPD2UDQZrm(b?)",1997 "VCVTQQ2PSZrm(b?)",1998 "VCVTTPD2DQZrm(b?)",1999 "VCVTTPD2UDQZrm(b?)",2000 "VCVTUQQ2PSZrm(b?)")>;2001 2002def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {2003 let Latency = 14;2004 let NumMicroOps = 4;2005 let ReleaseAtCycles = [2,1,1];2006}2007def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2WZ256rm(b?)",2008 "VPERMI2WZrm(b?)",2009 "VPERMT2WZ256rm(b?)",2010 "VPERMT2WZrm(b?)")>;2011 2012def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {2013 let Latency = 14;2014 let NumMicroOps = 10;2015 let ReleaseAtCycles = [2,4,1,3];2016}2017def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;2018 2019def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {2020 let Latency = 15;2021 let NumMicroOps = 1;2022 let ReleaseAtCycles = [1];2023}2024def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;2025 2026def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {2027 let Latency = 15;2028 let NumMicroOps = 8;2029 let ReleaseAtCycles = [1,2,2,1,2];2030}2031def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;2032 2033def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {2034 let Latency = 15;2035 let NumMicroOps = 10;2036 let ReleaseAtCycles = [1,1,1,5,1,1];2037}2038def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;2039 2040def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {2041 let Latency = 16;2042 let NumMicroOps = 14;2043 let ReleaseAtCycles = [1,1,1,4,2,5];2044}2045def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;2046 2047def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {2048 let Latency = 12;2049 let NumMicroOps = 34;2050 let ReleaseAtCycles = [1, 4, 5];2051}2052def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;2053 2054def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {2055 let Latency = 17;2056 let NumMicroOps = 15;2057 let ReleaseAtCycles = [2,1,2,4,2,4];2058}2059def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;2060 2061def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {2062 let Latency = 21;2063 let NumMicroOps = 4;2064 let ReleaseAtCycles = [1,3];2065}2066def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;2067 2068def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {2069 let Latency = 18;2070 let NumMicroOps = 8;2071 let ReleaseAtCycles = [1,1,1,5];2072}2073def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;2074 2075def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {2076 let Latency = 18;2077 let NumMicroOps = 11;2078 let ReleaseAtCycles = [2,1,1,4,1,2];2079}2080def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;2081 2082def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {2083 let Latency = 22;2084 let NumMicroOps = 4;2085 let ReleaseAtCycles = [1,3];2086}2087def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;2088 2089def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {2090 let Latency = 22;2091 let NumMicroOps = 4;2092 let ReleaseAtCycles = [1,3];2093}2094def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;2095 2096def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {2097 let Latency = 20;2098 let NumMicroOps = 1;2099 let ReleaseAtCycles = [1];2100}2101def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;2102 2103def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {2104 let Latency = 17;2105 let NumMicroOps = 5; // 2 uops perform multiple loads2106 let ReleaseAtCycles = [1,2,1,1];2107}2108def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,2109 VGATHERDPDZ128rm, VPGATHERDQZ128rm,2110 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;2111 2112def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {2113 let Latency = 19;2114 let NumMicroOps = 5; // 2 uops perform multiple loads2115 let ReleaseAtCycles = [1,4,1,1];2116}2117def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,2118 VGATHERQPDZ256rm, VPGATHERQQZ256rm,2119 VGATHERDPSZ128rm, VPGATHERDDZ128rm,2120 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;2121 2122def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {2123 let Latency = 21;2124 let NumMicroOps = 5; // 2 uops perform multiple loads2125 let ReleaseAtCycles = [1,8,1,1];2126}2127def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,2128 VGATHERDPDZrm, VPGATHERDQZrm,2129 VGATHERQPDZrm, VPGATHERQQZrm,2130 VGATHERQPSZrm, VPGATHERQDZrm)>;2131 2132def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {2133 let Latency = 25;2134 let NumMicroOps = 5; // 2 uops perform multiple loads2135 let ReleaseAtCycles = [1,16,1,1];2136}2137def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;2138 2139def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {2140 let Latency = 20;2141 let NumMicroOps = 8;2142 let ReleaseAtCycles = [1,1,1,1,1,1,2];2143}2144def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;2145 2146def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {2147 let Latency = 20;2148 let NumMicroOps = 10;2149 let ReleaseAtCycles = [1,2,7];2150}2151def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;2152 2153def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {2154 let Latency = 22;2155 let NumMicroOps = 2;2156 let ReleaseAtCycles = [1,1];2157}2158def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;2159 2160def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {2161 let Latency = 18;2162 let NumMicroOps = 5; // 2 uops perform multiple loads2163 let ReleaseAtCycles = [1,2,1,1];2164}2165def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,2166 VGATHERQPDrm, VPGATHERQQrm,2167 VGATHERQPSrm, VPGATHERQDrm)>;2168 2169def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {2170 let Latency = 20;2171 let NumMicroOps = 5; // 2 uops peform multiple loads2172 let ReleaseAtCycles = [1,4,1,1];2173}2174def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,2175 VGATHERDPSrm, VPGATHERDDrm,2176 VGATHERQPDYrm, VPGATHERQQYrm,2177 VGATHERQPSYrm, VPGATHERQDYrm)>;2178 2179def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {2180 let Latency = 22;2181 let NumMicroOps = 5; // 2 uops perform multiple loads2182 let ReleaseAtCycles = [1,8,1,1];2183}2184def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;2185 2186def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {2187 let Latency = 22;2188 let NumMicroOps = 14;2189 let ReleaseAtCycles = [5,5,4];2190}2191def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",2192 "VPCONFLICTQZ256rr")>;2193 2194def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {2195 let Latency = 23;2196 let NumMicroOps = 19;2197 let ReleaseAtCycles = [2,1,4,1,1,4,6];2198}2199def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;2200 2201def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {2202 let Latency = 25;2203 let NumMicroOps = 3;2204 let ReleaseAtCycles = [1,1,1];2205}2206def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;2207 2208def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {2209 let Latency = 27;2210 let NumMicroOps = 2;2211 let ReleaseAtCycles = [1,1];2212}2213def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;2214 2215def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {2216 let Latency = 29;2217 let NumMicroOps = 15;2218 let ReleaseAtCycles = [5,5,1,4];2219}2220def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;2221 2222def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {2223 let Latency = 30;2224 let NumMicroOps = 3;2225 let ReleaseAtCycles = [1,1,1];2226}2227def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;2228 2229def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {2230 let Latency = 35;2231 let NumMicroOps = 23;2232 let ReleaseAtCycles = [1,5,3,4,10];2233}2234def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",2235 "IN(8|16|32)rr")>;2236 2237def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {2238 let Latency = 35;2239 let NumMicroOps = 23;2240 let ReleaseAtCycles = [1,5,2,1,4,10];2241}2242def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",2243 "OUT(8|16|32)rr")>;2244 2245def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {2246 let Latency = 37;2247 let NumMicroOps = 21;2248 let ReleaseAtCycles = [9,7,5];2249}2250def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",2251 "VPCONFLICTQZrr")>;2252 2253def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {2254 let Latency = 37;2255 let NumMicroOps = 31;2256 let ReleaseAtCycles = [1,8,1,21];2257}2258def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;2259 2260def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {2261 let Latency = 40;2262 let NumMicroOps = 18;2263 let ReleaseAtCycles = [1,1,2,3,1,1,1,8];2264}2265def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;2266 2267def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {2268 let Latency = 41;2269 let NumMicroOps = 39;2270 let ReleaseAtCycles = [1,10,1,1,26];2271}2272def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;2273 2274def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {2275 let Latency = 42;2276 let NumMicroOps = 22;2277 let ReleaseAtCycles = [2,20];2278}2279def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;2280 2281def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {2282 let Latency = 42;2283 let NumMicroOps = 40;2284 let ReleaseAtCycles = [1,11,1,1,26];2285}2286def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;2287def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;2288 2289def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {2290 let Latency = 44;2291 let NumMicroOps = 22;2292 let ReleaseAtCycles = [9,7,1,5];2293}2294def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",2295 "VPCONFLICTQZrm(b?)")>;2296 2297def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {2298 let Latency = 62;2299 let NumMicroOps = 64;2300 let ReleaseAtCycles = [2,8,5,10,39];2301}2302def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;2303 2304def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {2305 let Latency = 63;2306 let NumMicroOps = 88;2307 let ReleaseAtCycles = [4,4,31,1,2,1,45];2308}2309def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;2310 2311def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {2312 let Latency = 63;2313 let NumMicroOps = 90;2314 let ReleaseAtCycles = [4,2,33,1,2,1,47];2315}2316def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;2317 2318def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {2319 let Latency = 67;2320 let NumMicroOps = 35;2321 let ReleaseAtCycles = [17,11,7];2322}2323def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;2324 2325def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {2326 let Latency = 74;2327 let NumMicroOps = 36;2328 let ReleaseAtCycles = [17,11,1,7];2329}2330def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;2331 2332def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {2333 let Latency = 75;2334 let NumMicroOps = 15;2335 let ReleaseAtCycles = [6,3,6];2336}2337def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;2338 2339def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {2340 let Latency = 106;2341 let NumMicroOps = 100;2342 let ReleaseAtCycles = [9,1,11,16,1,11,21,30];2343}2344def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;2345 2346def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {2347 let Latency = 140;2348 let NumMicroOps = 4;2349 let ReleaseAtCycles = [1,3];2350}2351def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;2352 2353def: InstRW<[WriteZero], (instrs CLC)>;2354 2355 2356// Instruction variants handled by the renamer. These might not need execution2357// ports in certain conditions.2358// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",2359// section "Skylake Pipeline" > "Register allocation and renaming".2360// These can be investigated with llvm-exegesis, e.g.2361// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-2362// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-2363 2364def SKXWriteZeroLatency : SchedWriteRes<[]> {2365 let Latency = 0;2366}2367 2368def SKXWriteZeroIdiom : SchedWriteVariant<[2369 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2370 SchedVar<NoSchedPred, [WriteALU]>2371]>;2372def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,2373 XOR32rr, XOR64rr)>;2374 2375def SKXWriteFZeroIdiom : SchedWriteVariant<[2376 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2377 SchedVar<NoSchedPred, [WriteFLogic]>2378]>;2379def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,2380 XORPDrr, VXORPDrr,2381 VXORPSZ128rr,2382 VXORPDZ128rr)>;2383 2384def SKXWriteFZeroIdiomY : SchedWriteVariant<[2385 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2386 SchedVar<NoSchedPred, [WriteFLogicY]>2387]>;2388def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,2389 VXORPSZ256rr, VXORPDZ256rr)>;2390 2391def SKXWriteFZeroIdiomZ : SchedWriteVariant<[2392 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2393 SchedVar<NoSchedPred, [WriteFLogicZ]>2394]>;2395def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;2396 2397def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[2398 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2399 SchedVar<NoSchedPred, [WriteVecLogicX]>2400]>;2401def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,2402 VPXORDZ128rr, VPXORQZ128rr)>;2403 2404def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[2405 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2406 SchedVar<NoSchedPred, [WriteVecLogicY]>2407]>;2408def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,2409 VPXORDZ256rr, VPXORQZ256rr)>;2410 2411def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[2412 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2413 SchedVar<NoSchedPred, [WriteVecLogicZ]>2414]>;2415def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;2416 2417def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[2418 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2419 SchedVar<NoSchedPred, [WriteVecALUX]>2420]>;2421def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,2422 PCMPGTDrr, VPCMPGTDrr,2423 PCMPGTWrr, VPCMPGTWrr)>;2424 2425def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[2426 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2427 SchedVar<NoSchedPred, [WriteVecALUY]>2428]>;2429def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,2430 VPCMPGTDYrr,2431 VPCMPGTWYrr)>;2432 2433def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {2434 let Latency = 1;2435 let NumMicroOps = 1;2436 let ReleaseAtCycles = [1];2437}2438 2439def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[2440 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2441 SchedVar<NoSchedPred, [SKXWritePSUB]>2442]>;2443 2444def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,2445 PSUBDrr, VPSUBDrr, VPSUBDZ128rr,2446 PSUBQrr, VPSUBQrr, VPSUBQZ128rr,2447 PSUBWrr, VPSUBWrr, VPSUBWZ128rr,2448 VPSUBBYrr, VPSUBBZ256rr,2449 VPSUBDYrr, VPSUBDZ256rr,2450 VPSUBQYrr, VPSUBQZ256rr,2451 VPSUBWYrr, VPSUBWZ256rr,2452 VPSUBBZrr,2453 VPSUBDZrr,2454 VPSUBQZrr,2455 VPSUBWZrr)>;2456def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {2457 let Latency = 3;2458 let NumMicroOps = 1;2459 let ReleaseAtCycles = [1];2460}2461 2462def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[2463 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,2464 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]>2465]>;2466def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,2467 VPCMPGTQYrr)>;2468 2469 2470// CMOVs that use both Z and C flag require an extra uop.2471def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {2472 let Latency = 2;2473 let ReleaseAtCycles = [2];2474 let NumMicroOps = 2;2475}2476 2477def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {2478 let Latency = 7;2479 let ReleaseAtCycles = [1,2];2480 let NumMicroOps = 3;2481}2482 2483def SKXCMOVA_CMOVBErr : SchedWriteVariant<[2484 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,2485 SchedVar<NoSchedPred, [WriteCMOV]>2486]>;2487 2488def SKXCMOVA_CMOVBErm : SchedWriteVariant<[2489 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,2490 SchedVar<NoSchedPred, [WriteCMOV.Folded]>2491]>;2492 2493def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;2494def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;2495 2496// SETCCs that use both Z and C flag require an extra uop.2497def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {2498 let Latency = 2;2499 let ReleaseAtCycles = [2];2500 let NumMicroOps = 2;2501}2502 2503def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {2504 let Latency = 3;2505 let ReleaseAtCycles = [1,1,2];2506 let NumMicroOps = 4;2507}2508 2509def SKXSETA_SETBErr : SchedWriteVariant<[2510 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,2511 SchedVar<NoSchedPred, [WriteSETCC]>2512]>;2513 2514def SKXSETA_SETBErm : SchedWriteVariant<[2515 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,2516 SchedVar<NoSchedPred, [WriteSETCCStore]>2517]>;2518 2519def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;2520def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;2521 2522///////////////////////////////////////////////////////////////////////////////2523// Dependency breaking instructions.2524///////////////////////////////////////////////////////////////////////////////2525 2526def : IsZeroIdiomFunction<[2527 // GPR Zero-idioms.2528 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,2529 2530 // SSE Zero-idioms.2531 DepBreakingClass<[2532 // fp variants.2533 XORPSrr, XORPDrr,2534 2535 // int variants.2536 PXORrr,2537 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,2538 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr2539 ], ZeroIdiomPredicate>,2540 2541 // AVX Zero-idioms.2542 DepBreakingClass<[2543 // xmm fp variants.2544 VXORPSrr, VXORPDrr,2545 2546 // xmm int variants.2547 VPXORrr,2548 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,2549 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,2550 2551 // ymm variants.2552 VXORPSYrr, VXORPDYrr, VPXORYrr,2553 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,2554 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr,2555 2556 // zmm variants.2557 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr,2558 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr,2559 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr,2560 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,2561 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,2562 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,2563 ], ZeroIdiomPredicate>,2564]>;2565 2566} // SchedModel2567