752 lines · plain
1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// InstrSchedModel annotations for out-of-order CPUs.11 12// Instructions with folded loads need to read the memory operand immediately,13// but other register operands don't have to be read until the load is ready.14// These operands are marked with ReadAfterLd.15def ReadAfterLd : SchedRead;16def ReadAfterVecLd : SchedRead;17def ReadAfterVecXLd : SchedRead;18def ReadAfterVecYLd : SchedRead;19 20// Instructions that move data between general purpose registers and vector21// registers may be subject to extra latency due to data bypass delays.22// This SchedRead describes a bypass delay caused by data being moved from the23// integer unit to the floating point unit.24def ReadInt2Fpu : SchedRead;25 26// Instructions with both a load and a store folded are modeled as a folded27// load + WriteRMW.28def WriteRMW : SchedWrite;29 30// Helper to set SchedWrite ExePorts/Latency/ReleaseAtCycles/NumMicroOps.31multiclass X86WriteRes<SchedWrite SchedRW,32 list<ProcResourceKind> ExePorts,33 int Lat, list<int> Res, int UOps> {34 def : WriteRes<SchedRW, ExePorts> {35 let Latency = Lat;36 let ReleaseAtCycles = Res;37 let NumMicroOps = UOps;38 }39}40 41// Most instructions can fold loads, so almost every SchedWrite comes in two42// variants: With and without a folded load.43// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite44// with a folded load.45class X86FoldableSchedWrite : SchedWrite {46 // The SchedWrite to use when a load is folded into the instruction.47 SchedWrite Folded;48 // The SchedRead to tag register operands than don't need to be ready49 // until the folded load has completed.50 SchedRead ReadAfterFold;51}52 53// Multiclass that produces a linked pair of SchedWrites.54multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {55 // Register-Memory operation.56 def Ld : SchedWrite;57 // Register-Register operation.58 def NAME : X86FoldableSchedWrite {59 let Folded = !cast<SchedWrite>(NAME#"Ld");60 let ReadAfterFold = ReadAfter;61 }62}63 64// Helpers to mark SchedWrites as unsupported.65multiclass X86WriteResUnsupported<SchedWrite SchedRW> {66 let Unsupported = 1 in {67 def : WriteRes<SchedRW, []>;68 }69}70multiclass X86WriteResPairUnsupported<X86FoldableSchedWrite SchedRW> {71 let Unsupported = 1 in {72 def : WriteRes<SchedRW, []>;73 def : WriteRes<SchedRW.Folded, []>;74 }75}76 77// Multiclass that wraps X86FoldableSchedWrite for each vector width.78class X86SchedWriteWidths<X86FoldableSchedWrite sScl,79 X86FoldableSchedWrite s128,80 X86FoldableSchedWrite s256,81 X86FoldableSchedWrite s512> {82 X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.83 X86FoldableSchedWrite MMX = sScl; // MMX operations.84 X86FoldableSchedWrite XMM = s128; // XMM operations.85 X86FoldableSchedWrite YMM = s256; // YMM operations.86 X86FoldableSchedWrite ZMM = s512; // ZMM operations.87}88 89// Multiclass that wraps X86SchedWriteWidths for each fp vector type.90class X86SchedWriteSizes<X86SchedWriteWidths sPH,91 X86SchedWriteWidths sPS,92 X86SchedWriteWidths sPD> {93 X86SchedWriteWidths PH = sPH;94 X86SchedWriteWidths PS = sPS;95 X86SchedWriteWidths PD = sPD;96}97 98// Multiclass that wraps move/load/store triple for a vector width.99class X86SchedWriteMoveLS<SchedWrite MoveRR,100 SchedWrite LoadRM,101 SchedWrite StoreMR> {102 SchedWrite RR = MoveRR;103 SchedWrite RM = LoadRM;104 SchedWrite MR = StoreMR;105}106 107// Multiclass that wraps masked load/store writes for a vector width.108class X86SchedWriteMaskMove<SchedWrite LoadRM, SchedWrite StoreMR> {109 SchedWrite RM = LoadRM;110 SchedWrite MR = StoreMR;111}112 113// Multiclass that wraps X86SchedWriteMoveLS for each vector width.114class X86SchedWriteMoveLSWidths<X86SchedWriteMoveLS sScl,115 X86SchedWriteMoveLS s128,116 X86SchedWriteMoveLS s256,117 X86SchedWriteMoveLS s512> {118 X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.119 X86SchedWriteMoveLS MMX = sScl; // MMX operations.120 X86SchedWriteMoveLS XMM = s128; // XMM operations.121 X86SchedWriteMoveLS YMM = s256; // YMM operations.122 X86SchedWriteMoveLS ZMM = s512; // ZMM operations.123}124 125// Loads, stores, and moves, not folded with other operations.126def WriteLoad : SchedWrite;127def WriteStore : SchedWrite;128def WriteStoreNT : SchedWrite;129def WriteMove : SchedWrite;130def WriteVecMaskedGatherWriteback : SchedWrite;131def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy132 133// Arithmetic.134defm WriteALU : X86SchedWritePair; // Simple integer ALU op.135defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.136def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;137def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>;138def WriteLEA : SchedWrite; // LEA instructions can't fold loads.139 140// Integer multiplication141defm WriteIMul8 : X86SchedWritePair; // Integer 8-bit multiplication.142defm WriteIMul16 : X86SchedWritePair; // Integer 16-bit multiplication.143defm WriteIMul16Imm : X86SchedWritePair; // Integer 16-bit multiplication by immediate.144defm WriteIMul16Reg : X86SchedWritePair; // Integer 16-bit multiplication by register.145defm WriteIMul32 : X86SchedWritePair; // Integer 32-bit multiplication.146defm WriteIMul32Imm : X86SchedWritePair; // Integer 32-bit multiplication by immediate.147defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by register.148defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.149defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.150defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.151defm WriteMULX32 : X86SchedWritePair; // Integer 32-bit Multiplication without affecting flags.152defm WriteMULX64 : X86SchedWritePair; // Integer 64-bit Multiplication without affecting flags.153def WriteIMulH : SchedWrite; // Integer multiplication, high part (only used by the RR variant of MULX).154def WriteIMulHLd : SchedWrite; // Integer multiplication, high part (only used by the RM variant of MULX).155 156def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.157def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.158defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.159def WriteCMPXCHGRMW : SchedWrite; // Compare and set, compare and swap.160def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.161 162// Integer division.163defm WriteDiv8 : X86SchedWritePair;164defm WriteDiv16 : X86SchedWritePair;165defm WriteDiv32 : X86SchedWritePair;166defm WriteDiv64 : X86SchedWritePair;167defm WriteIDiv8 : X86SchedWritePair;168defm WriteIDiv16 : X86SchedWritePair;169defm WriteIDiv32 : X86SchedWritePair;170defm WriteIDiv64 : X86SchedWritePair;171 172defm WriteBSF : X86SchedWritePair; // Bit scan forward.173defm WriteBSR : X86SchedWritePair; // Bit scan reverse.174defm WritePOPCNT : X86SchedWritePair; // Bit population count.175defm WriteLZCNT : X86SchedWritePair; // Leading zero count.176defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.177defm WriteCMOV : X86SchedWritePair; // Conditional move.178def WriteFCMOV : SchedWrite; // X87 conditional move.179def WriteSETCC : SchedWrite; // Set register based on condition code.180def WriteSETCCStore : SchedWrite;181def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.182 183def WriteBitTest : SchedWrite; // Bit Test184def WriteBitTestImmLd : SchedWrite;185def WriteBitTestRegLd : SchedWrite;186 187def WriteBitTestSet : SchedWrite; // Bit Test + Set188def WriteBitTestSetImmLd : SchedWrite;189def WriteBitTestSetRegLd : SchedWrite;190def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;191def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;192 193// Integer shifts and rotates.194defm WriteShift : X86SchedWritePair;195defm WriteShiftCL : X86SchedWritePair;196defm WriteRotate : X86SchedWritePair;197defm WriteRotateCL : X86SchedWritePair;198 199// Double shift instructions.200def WriteSHDrri : SchedWrite;201def WriteSHDrrcl : SchedWrite;202def WriteSHDmri : SchedWrite;203def WriteSHDmrcl : SchedWrite;204 205// BMI1 BEXTR/BLS, BMI2 BZHI206defm WriteBEXTR : X86SchedWritePair;207defm WriteBLS : X86SchedWritePair;208defm WriteBZHI : X86SchedWritePair;209 210// Idioms that clear a register, like xorps %xmm0, %xmm0.211// These can often bypass execution ports completely.212def WriteZero : SchedWrite;213 214// Branches don't produce values, so they have no latency, but they still215// consume resources. Indirect branches can fold loads.216defm WriteJump : X86SchedWritePair;217 218// Floating point. This covers both scalar and vector operations.219def WriteFLD0 : SchedWrite;220def WriteFLD1 : SchedWrite;221def WriteFLDC : SchedWrite;222def WriteFLoad : SchedWrite;223def WriteFLoadX : SchedWrite;224def WriteFLoadY : SchedWrite;225def WriteFMaskedLoad : SchedWrite;226def WriteFMaskedLoadY : SchedWrite;227def WriteFStore : SchedWrite;228def WriteFStoreX : SchedWrite;229def WriteFStoreY : SchedWrite;230def WriteFStoreNT : SchedWrite;231def WriteFStoreNTX : SchedWrite;232def WriteFStoreNTY : SchedWrite;233 234def WriteFMaskedStore32 : SchedWrite;235def WriteFMaskedStore64 : SchedWrite;236def WriteFMaskedStore32Y : SchedWrite;237def WriteFMaskedStore64Y : SchedWrite;238 239def WriteFMove : SchedWrite;240def WriteFMoveX : SchedWrite;241def WriteFMoveY : SchedWrite;242def WriteFMoveZ : SchedWrite;243 244defm WriteFAdd : X86SchedWritePair<ReadAfterVecLd>; // Floating point add/sub.245defm WriteFAddX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point add/sub (XMM).246defm WriteFAddY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (YMM).247defm WriteFAddZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (ZMM).248defm WriteFAdd64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double add/sub.249defm WriteFAdd64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double add/sub (XMM).250defm WriteFAdd64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (YMM).251defm WriteFAdd64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (ZMM).252defm WriteFCmp : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare.253defm WriteFCmpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point compare (XMM).254defm WriteFCmpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (YMM).255defm WriteFCmpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (ZMM).256defm WriteFCmp64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double compare.257defm WriteFCmp64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double compare (XMM).258defm WriteFCmp64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (YMM).259defm WriteFCmp64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (ZMM).260defm WriteFCom : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare to flags (X87).261defm WriteFComX : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare to flags (SSE).262defm WriteFMul : X86SchedWritePair<ReadAfterVecLd>; // Floating point multiplication.263defm WriteFMulX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point multiplication (XMM).264defm WriteFMulY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).265defm WriteFMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).266defm WriteFMul64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double multiplication.267defm WriteFMul64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double multiplication (XMM).268defm WriteFMul64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (YMM).269defm WriteFMul64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (ZMM).270defm WriteFDiv : X86SchedWritePair<ReadAfterVecLd>; // Floating point division.271defm WriteFDivX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point division (XMM).272defm WriteFDivY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (YMM).273defm WriteFDivZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (ZMM).274defm WriteFDiv64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double division.275defm WriteFDiv64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double division (XMM).276defm WriteFDiv64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (YMM).277defm WriteFDiv64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (ZMM).278defm WriteFSqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point square root.279defm WriteFSqrtX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point square root (XMM).280defm WriteFSqrtY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (YMM).281defm WriteFSqrtZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (ZMM).282defm WriteFSqrt64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double square root.283defm WriteFSqrt64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double square root (XMM).284defm WriteFSqrt64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (YMM).285defm WriteFSqrt64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (ZMM).286defm WriteFSqrt80 : X86SchedWritePair<ReadAfterVecLd>; // Floating point long double square root.287defm WriteFRcp : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal estimate.288defm WriteFRcpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal estimate (XMM).289defm WriteFRcpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (YMM).290defm WriteFRcpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (ZMM).291defm WriteFRsqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal square root estimate.292defm WriteFRsqrtX: X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal square root estimate (XMM).293defm WriteFRsqrtY: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (YMM).294defm WriteFRsqrtZ: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (ZMM).295defm WriteFMA : X86SchedWritePair<ReadAfterVecLd>; // Fused Multiply Add.296defm WriteFMAX : X86SchedWritePair<ReadAfterVecXLd>; // Fused Multiply Add (XMM).297defm WriteFMAY : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (YMM).298defm WriteFMAZ : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (ZMM).299defm WriteDPPD : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double dot product.300defm WriteDPPS : X86SchedWritePair<ReadAfterVecXLd>; // Floating point single dot product.301defm WriteDPPSY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point single dot product (YMM).302defm WriteFSign : X86SchedWritePair<ReadAfterVecLd>; // Floating point fabs/fchs.303defm WriteFRnd : X86SchedWritePair<ReadAfterVecXLd>; // Floating point rounding.304defm WriteFRndY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (YMM).305defm WriteFRndZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (ZMM).306defm WriteFLogic : X86SchedWritePair<ReadAfterVecXLd>; // Floating point and/or/xor logicals.307defm WriteFLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (YMM).308defm WriteFLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (ZMM).309defm WriteFTest : X86SchedWritePair<ReadAfterVecXLd>; // Floating point TEST instructions.310defm WriteFTestY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (YMM).311defm WriteFTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (ZMM).312defm WriteFShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector shuffles.313defm WriteFShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (YMM).314defm WriteFShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (ZMM).315defm WriteFVarShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector variable shuffles.316defm WriteFVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (YMM).317defm WriteFVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (ZMM).318defm WriteFBlend : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector blends.319defm WriteFBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (YMM).320defm WriteFBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (ZMM).321defm WriteFVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Fp vector variable blends.322defm WriteFVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMM).323defm WriteFVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMZMM).324 325// FMA Scheduling helper class.326class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }327 328// Horizontal Add/Sub (float and integer)329defm WriteFHAdd : X86SchedWritePair<ReadAfterVecXLd>;330defm WriteFHAddY : X86SchedWritePair<ReadAfterVecYLd>;331defm WriteFHAddZ : X86SchedWritePair<ReadAfterVecYLd>;332defm WritePHAdd : X86SchedWritePair<ReadAfterVecLd>;333defm WritePHAddX : X86SchedWritePair<ReadAfterVecXLd>;334defm WritePHAddY : X86SchedWritePair<ReadAfterVecYLd>;335defm WritePHAddZ : X86SchedWritePair<ReadAfterVecYLd>;336 337// Vector integer operations.338def WriteVecLoad : SchedWrite;339def WriteVecLoadX : SchedWrite;340def WriteVecLoadY : SchedWrite;341def WriteVecLoadNT : SchedWrite;342def WriteVecLoadNTY : SchedWrite;343def WriteVecMaskedLoad : SchedWrite;344def WriteVecMaskedLoadY : SchedWrite;345def WriteVecStore : SchedWrite;346def WriteVecStoreX : SchedWrite;347def WriteVecStoreY : SchedWrite;348def WriteVecStoreNT : SchedWrite;349def WriteVecStoreNTY : SchedWrite;350def WriteVecMaskedStore32 : SchedWrite;351def WriteVecMaskedStore64 : SchedWrite;352def WriteVecMaskedStore32Y : SchedWrite;353def WriteVecMaskedStore64Y : SchedWrite;354def WriteVecMove : SchedWrite;355def WriteVecMoveX : SchedWrite;356def WriteVecMoveY : SchedWrite;357def WriteVecMoveZ : SchedWrite;358def WriteVecMoveToGpr : SchedWrite;359def WriteVecMoveFromGpr : SchedWrite;360 361defm WriteVecALU : X86SchedWritePair<ReadAfterVecLd>; // Vector integer ALU op, no logicals.362defm WriteVecALUX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer ALU op, no logicals (XMM).363defm WriteVecALUY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (YMM).364defm WriteVecALUZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (ZMM).365defm WriteVecLogic : X86SchedWritePair<ReadAfterVecLd>; // Vector integer and/or/xor logicals.366defm WriteVecLogicX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer and/or/xor logicals (XMM).367defm WriteVecLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (YMM).368defm WriteVecLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (ZMM).369defm WriteVecTest : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer TEST instructions.370defm WriteVecTestY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (YMM).371defm WriteVecTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (ZMM).372defm WriteVecShift : X86SchedWritePair<ReadAfterVecLd>; // Vector integer shifts (default).373defm WriteVecShiftX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer shifts (XMM).374defm WriteVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (YMM).375defm WriteVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (ZMM).376defm WriteVecShiftImm : X86SchedWritePair<ReadAfterVecLd>; // Vector integer immediate shifts (default).377defm WriteVecShiftImmX: X86SchedWritePair<ReadAfterVecXLd>; // Vector integer immediate shifts (XMM).378defm WriteVecShiftImmY: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (YMM).379defm WriteVecShiftImmZ: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (ZMM).380defm WriteVecIMul : X86SchedWritePair<ReadAfterVecLd>; // Vector integer multiply (default).381defm WriteVecIMulX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer multiply (XMM).382defm WriteVecIMulY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (YMM).383defm WriteVecIMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (ZMM).384defm WritePMULLD : X86SchedWritePair<ReadAfterVecXLd>; // Vector PMULLD.385defm WritePMULLDY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (YMM).386defm WritePMULLDZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (ZMM).387defm WriteShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector shuffles.388defm WriteShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector shuffles (XMM).389defm WriteShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (YMM).390defm WriteShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (ZMM).391defm WriteVarShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector variable shuffles.392defm WriteVarShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable shuffles (XMM).393defm WriteVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (YMM).394defm WriteVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (ZMM).395defm WriteBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector blends.396defm WriteBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (YMM).397defm WriteBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (ZMM).398defm WriteVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable blends.399defm WriteVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (YMM).400defm WriteVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (ZMM).401defm WritePSADBW : X86SchedWritePair<ReadAfterVecLd>; // Vector PSADBW.402defm WritePSADBWX : X86SchedWritePair<ReadAfterVecXLd>; // Vector PSADBW (XMM).403defm WritePSADBWY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (YMM).404defm WritePSADBWZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (ZMM).405defm WriteMPSAD : X86SchedWritePair<ReadAfterVecXLd>; // Vector MPSAD.406defm WriteMPSADY : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (YMM).407defm WriteMPSADZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (ZMM).408defm WritePHMINPOS : X86SchedWritePair<ReadAfterVecXLd>; // Vector PHMINPOS.409 410// Vector insert/extract operations.411defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element.412def WriteVecExtract : SchedWrite; // Extract vector element to gpr.413def WriteVecExtractSt : SchedWrite; // Extract vector element and store.414 415// MOVMSK operations.416def WriteFMOVMSK : SchedWrite;417def WriteVecMOVMSK : SchedWrite;418def WriteVecMOVMSKY : SchedWrite;419def WriteMMXMOVMSK : SchedWrite;420 421// Conversion between integer and float.422defm WriteCvtSD2I : X86SchedWritePair<ReadAfterVecLd>; // Double -> Integer.423defm WriteCvtPD2I : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Integer (XMM).424defm WriteCvtPD2IY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (YMM).425defm WriteCvtPD2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (ZMM).426 427defm WriteCvtSS2I : X86SchedWritePair<ReadAfterVecLd>; // Float -> Integer.428defm WriteCvtPS2I : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Integer (XMM).429defm WriteCvtPS2IY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (YMM).430defm WriteCvtPS2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (ZMM).431 432defm WriteCvtI2SD : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Double.433defm WriteCvtI2PD : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Double (XMM).434defm WriteCvtI2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (YMM).435defm WriteCvtI2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (ZMM).436 437defm WriteCvtI2SS : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Float.438defm WriteCvtI2PS : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Float (XMM).439defm WriteCvtI2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (YMM).440defm WriteCvtI2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (ZMM).441 442defm WriteCvtSS2SD : X86SchedWritePair<ReadAfterVecLd>; // Float -> Double size conversion.443defm WriteCvtPS2PD : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Double size conversion (XMM).444defm WriteCvtPS2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (YMM).445defm WriteCvtPS2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (ZMM).446 447defm WriteCvtSD2SS : X86SchedWritePair<ReadAfterVecLd>; // Double -> Float size conversion.448defm WriteCvtPD2PS : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Float size conversion (XMM).449defm WriteCvtPD2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (YMM).450defm WriteCvtPD2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (ZMM).451 452defm WriteCvtPH2PS : X86SchedWritePair<ReadAfterVecXLd>; // Half -> Float size conversion.453defm WriteCvtPH2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (YMM).454defm WriteCvtPH2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (ZMM).455 456def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion.457def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM).458def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM).459def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion.460def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM).461def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM).462 463// CRC32 instruction.464defm WriteCRC32 : X86SchedWritePair<ReadAfterLd>;465 466// Strings instructions.467// Packed Compare Implicit Length Strings, Return Mask468defm WritePCmpIStrM : X86SchedWritePair<ReadAfterVecXLd>;469// Packed Compare Explicit Length Strings, Return Mask470defm WritePCmpEStrM : X86SchedWritePair<ReadAfterVecXLd>;471// Packed Compare Implicit Length Strings, Return Index472defm WritePCmpIStrI : X86SchedWritePair<ReadAfterVecXLd>;473// Packed Compare Explicit Length Strings, Return Index474defm WritePCmpEStrI : X86SchedWritePair<ReadAfterVecXLd>;475 476// AES instructions.477defm WriteAESDecEnc : X86SchedWritePair<ReadAfterVecXLd>; // Decryption, encryption.478defm WriteAESIMC : X86SchedWritePair<ReadAfterVecXLd>; // InvMixColumn.479defm WriteAESKeyGen : X86SchedWritePair<ReadAfterVecXLd>; // Key Generation.480 481// Carry-less multiplication instructions.482defm WriteCLMul : X86SchedWritePair<ReadAfterVecXLd>;483 484// EMMS/FEMMS485def WriteEMMS : SchedWrite;486 487// Load/store MXCSR488def WriteLDMXCSR : SchedWrite;489def WriteSTMXCSR : SchedWrite;490 491// Catch-all for expensive system instructions.492def WriteSystem : SchedWrite;493 494// AVX2.495defm WriteFShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width vector shuffles.496defm WriteFVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width variable shuffles.497defm WriteShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector shuffles.498defm WriteVPMOV256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width packed vector width-changing move.499defm WriteVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector variable shuffles.500defm WriteVarVecShift : X86SchedWritePair<ReadAfterVecXLd>; // Variable vector shifts.501defm WriteVarVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (YMM).502defm WriteVarVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (ZMM).503 504// Old microcoded instructions that nobody use.505def WriteMicrocoded : SchedWrite;506 507// Fence instructions.508def WriteFence : SchedWrite;509 510// Nop, not very useful expect it provides a model for nops!511def WriteNop : SchedWrite;512 513// Move/Load/Store wrappers.514def WriteFMoveLS515 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStore>;516def WriteFMoveLSX517 : X86SchedWriteMoveLS<WriteFMoveX, WriteFLoadX, WriteFStoreX>;518def WriteFMoveLSY519 : X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreY>;520def WriteFMoveLSZ521 : X86SchedWriteMoveLS<WriteFMoveZ, WriteFLoadY, WriteFStoreY>;522def SchedWriteFMoveLS523 : X86SchedWriteMoveLSWidths<WriteFMoveLS, WriteFMoveLSX,524 WriteFMoveLSY, WriteFMoveLSZ>;525 526def WriteFMoveLSNT527 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNT>;528def WriteFMoveLSNTX529 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNTX>;530def WriteFMoveLSNTY531 : X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreNTY>;532def SchedWriteFMoveLSNT533 : X86SchedWriteMoveLSWidths<WriteFMoveLSNT, WriteFMoveLSNTX,534 WriteFMoveLSNTY, WriteFMoveLSNTY>;535 536def WriteVecMoveLS537 : X86SchedWriteMoveLS<WriteVecMove, WriteVecLoad, WriteVecStore>;538def WriteVecMoveLSX539 : X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadX, WriteVecStoreX>;540def WriteVecMoveLSY541 : X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadY, WriteVecStoreY>;542def WriteVecMoveLSZ543 : X86SchedWriteMoveLS<WriteVecMoveZ, WriteVecLoadY, WriteVecStoreY>;544def SchedWriteVecMoveLS545 : X86SchedWriteMoveLSWidths<WriteVecMoveLS, WriteVecMoveLSX,546 WriteVecMoveLSY, WriteVecMoveLSZ>;547 548def WriteVecMoveLSNT549 : X86SchedWriteMoveLS<WriteVecMove, WriteVecLoadNT, WriteVecStoreNT>;550def WriteVecMoveLSNTX551 : X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadNT, WriteVecStoreNT>;552def WriteVecMoveLSNTY553 : X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadNTY, WriteVecStoreNTY>;554def SchedWriteVecMoveLSNT555 : X86SchedWriteMoveLSWidths<WriteVecMoveLSNT, WriteVecMoveLSNTX,556 WriteVecMoveLSNTY, WriteVecMoveLSNTY>;557 558// Conditional SIMD Packed Loads and Stores wrappers.559def WriteFMaskMove32560 : X86SchedWriteMaskMove<WriteFMaskedLoad, WriteFMaskedStore32>;561def WriteFMaskMove64562 : X86SchedWriteMaskMove<WriteFMaskedLoad, WriteFMaskedStore64>;563def WriteFMaskMove32Y564 : X86SchedWriteMaskMove<WriteFMaskedLoadY, WriteFMaskedStore32Y>;565def WriteFMaskMove64Y566 : X86SchedWriteMaskMove<WriteFMaskedLoadY, WriteFMaskedStore64Y>;567def WriteVecMaskMove32568 : X86SchedWriteMaskMove<WriteVecMaskedLoad, WriteVecMaskedStore32>;569def WriteVecMaskMove64570 : X86SchedWriteMaskMove<WriteVecMaskedLoad, WriteVecMaskedStore64>;571def WriteVecMaskMove32Y572 : X86SchedWriteMaskMove<WriteVecMaskedLoadY, WriteVecMaskedStore32Y>;573def WriteVecMaskMove64Y574 : X86SchedWriteMaskMove<WriteVecMaskedLoadY, WriteVecMaskedStore64Y>;575 576// Vector width wrappers.577def SchedWriteFAdd578 : X86SchedWriteWidths<WriteFAdd, WriteFAddX, WriteFAddY, WriteFAddZ>;579def SchedWriteFAdd64580 : X86SchedWriteWidths<WriteFAdd64, WriteFAdd64X, WriteFAdd64Y, WriteFAdd64Z>;581def SchedWriteFHAdd582 : X86SchedWriteWidths<WriteFHAdd, WriteFHAdd, WriteFHAddY, WriteFHAddZ>;583def SchedWriteFCmp584 : X86SchedWriteWidths<WriteFCmp, WriteFCmpX, WriteFCmpY, WriteFCmpZ>;585def SchedWriteFCmp64586 : X86SchedWriteWidths<WriteFCmp64, WriteFCmp64X, WriteFCmp64Y, WriteFCmp64Z>;587def SchedWriteFMul588 : X86SchedWriteWidths<WriteFMul, WriteFMulX, WriteFMulY, WriteFMulZ>;589def SchedWriteFMul64590 : X86SchedWriteWidths<WriteFMul64, WriteFMul64X, WriteFMul64Y, WriteFMul64Z>;591def SchedWriteFMA592 : X86SchedWriteWidths<WriteFMA, WriteFMAX, WriteFMAY, WriteFMAZ>;593def SchedWriteDPPD594 : X86SchedWriteWidths<WriteDPPD, WriteDPPD, WriteDPPD, WriteDPPD>;595def SchedWriteDPPS596 : X86SchedWriteWidths<WriteDPPS, WriteDPPS, WriteDPPSY, WriteDPPSY>;597def SchedWriteFDiv598 : X86SchedWriteWidths<WriteFDiv, WriteFDivX, WriteFDivY, WriteFDivZ>;599def SchedWriteFDiv64600 : X86SchedWriteWidths<WriteFDiv64, WriteFDiv64X, WriteFDiv64Y, WriteFDiv64Z>;601def SchedWriteFSqrt602 : X86SchedWriteWidths<WriteFSqrt, WriteFSqrtX,603 WriteFSqrtY, WriteFSqrtZ>;604def SchedWriteFSqrt64605 : X86SchedWriteWidths<WriteFSqrt64, WriteFSqrt64X,606 WriteFSqrt64Y, WriteFSqrt64Z>;607def SchedWriteFRcp608 : X86SchedWriteWidths<WriteFRcp, WriteFRcpX, WriteFRcpY, WriteFRcpZ>;609def SchedWriteFRsqrt610 : X86SchedWriteWidths<WriteFRsqrt, WriteFRsqrtX, WriteFRsqrtY, WriteFRsqrtZ>;611def SchedWriteFRnd612 : X86SchedWriteWidths<WriteFRnd, WriteFRnd, WriteFRndY, WriteFRndZ>;613def SchedWriteFLogic614 : X86SchedWriteWidths<WriteFLogic, WriteFLogic, WriteFLogicY, WriteFLogicZ>;615def SchedWriteFTest616 : X86SchedWriteWidths<WriteFTest, WriteFTest, WriteFTestY, WriteFTestZ>;617 618def SchedWriteFShuffle619 : X86SchedWriteWidths<WriteFShuffle, WriteFShuffle,620 WriteFShuffleY, WriteFShuffleZ>;621def SchedWriteFVarShuffle622 : X86SchedWriteWidths<WriteFVarShuffle, WriteFVarShuffle,623 WriteFVarShuffleY, WriteFVarShuffleZ>;624def SchedWriteFBlend625 : X86SchedWriteWidths<WriteFBlend, WriteFBlend, WriteFBlendY, WriteFBlendZ>;626def SchedWriteFVarBlend627 : X86SchedWriteWidths<WriteFVarBlend, WriteFVarBlend,628 WriteFVarBlendY, WriteFVarBlendZ>;629 630def SchedWriteCvtDQ2PD631 : X86SchedWriteWidths<WriteCvtI2SD, WriteCvtI2PD,632 WriteCvtI2PDY, WriteCvtI2PDZ>;633def SchedWriteCvtDQ2PS634 : X86SchedWriteWidths<WriteCvtI2SS, WriteCvtI2PS,635 WriteCvtI2PSY, WriteCvtI2PSZ>;636def SchedWriteCvtPD2DQ637 : X86SchedWriteWidths<WriteCvtSD2I, WriteCvtPD2I,638 WriteCvtPD2IY, WriteCvtPD2IZ>;639def SchedWriteCvtPS2DQ640 : X86SchedWriteWidths<WriteCvtSS2I, WriteCvtPS2I,641 WriteCvtPS2IY, WriteCvtPS2IZ>;642def SchedWriteCvtPS2PD643 : X86SchedWriteWidths<WriteCvtSS2SD, WriteCvtPS2PD,644 WriteCvtPS2PDY, WriteCvtPS2PDZ>;645def SchedWriteCvtPD2PS646 : X86SchedWriteWidths<WriteCvtSD2SS, WriteCvtPD2PS,647 WriteCvtPD2PSY, WriteCvtPD2PSZ>;648 649def SchedWriteVecALU650 : X86SchedWriteWidths<WriteVecALU, WriteVecALUX, WriteVecALUY, WriteVecALUZ>;651def SchedWritePHAdd652 : X86SchedWriteWidths<WritePHAdd, WritePHAddX, WritePHAddY, WritePHAddZ>;653def SchedWriteVecLogic654 : X86SchedWriteWidths<WriteVecLogic, WriteVecLogicX,655 WriteVecLogicY, WriteVecLogicZ>;656def SchedWriteVecTest657 : X86SchedWriteWidths<WriteVecTest, WriteVecTest,658 WriteVecTestY, WriteVecTestZ>;659def SchedWriteVecShift660 : X86SchedWriteWidths<WriteVecShift, WriteVecShiftX,661 WriteVecShiftY, WriteVecShiftZ>;662def SchedWriteVecShiftImm663 : X86SchedWriteWidths<WriteVecShiftImm, WriteVecShiftImmX,664 WriteVecShiftImmY, WriteVecShiftImmZ>;665def SchedWriteVarVecShift666 : X86SchedWriteWidths<WriteVarVecShift, WriteVarVecShift,667 WriteVarVecShiftY, WriteVarVecShiftZ>;668def SchedWriteVecIMul669 : X86SchedWriteWidths<WriteVecIMul, WriteVecIMulX,670 WriteVecIMulY, WriteVecIMulZ>;671def SchedWritePMULLD672 : X86SchedWriteWidths<WritePMULLD, WritePMULLD,673 WritePMULLDY, WritePMULLDZ>;674def SchedWriteMPSAD675 : X86SchedWriteWidths<WriteMPSAD, WriteMPSAD,676 WriteMPSADY, WriteMPSADZ>;677def SchedWritePSADBW678 : X86SchedWriteWidths<WritePSADBW, WritePSADBWX,679 WritePSADBWY, WritePSADBWZ>;680 681def SchedWriteVecExtend682 : X86SchedWriteWidths<WriteShuffle, WriteShuffleX,683 WriteVPMOV256, WriteVPMOV256>;684def SchedWriteVecTruncate685 : X86SchedWriteWidths<WriteVPMOV256, WriteVPMOV256,686 WriteVPMOV256, WriteVPMOV256>;687def SchedWriteShuffle688 : X86SchedWriteWidths<WriteShuffle, WriteShuffleX,689 WriteShuffleY, WriteShuffleZ>;690def SchedWriteVarShuffle691 : X86SchedWriteWidths<WriteVarShuffle, WriteVarShuffleX,692 WriteVarShuffleY, WriteVarShuffleZ>;693def SchedWriteBlend694 : X86SchedWriteWidths<WriteBlend, WriteBlend, WriteBlendY, WriteBlendZ>;695def SchedWriteVarBlend696 : X86SchedWriteWidths<WriteVarBlend, WriteVarBlend,697 WriteVarBlendY, WriteVarBlendZ>;698 699// Vector size wrappers.700// FIXME: Currently PH uses the same schedule method as PS.701// We may refine them later.702def SchedWriteFAddSizes703 : X86SchedWriteSizes<SchedWriteFAdd, SchedWriteFAdd, SchedWriteFAdd64>;704def SchedWriteFCmpSizes705 : X86SchedWriteSizes<SchedWriteFCmp, SchedWriteFCmp, SchedWriteFCmp64>;706def SchedWriteFMulSizes707 : X86SchedWriteSizes<SchedWriteFMul, SchedWriteFMul, SchedWriteFMul64>;708def SchedWriteFDivSizes709 : X86SchedWriteSizes<SchedWriteFDiv, SchedWriteFDiv, SchedWriteFDiv64>;710def SchedWriteFSqrtSizes711 : X86SchedWriteSizes<SchedWriteFSqrt, SchedWriteFSqrt, SchedWriteFSqrt64>;712def SchedWriteFLogicSizes713 : X86SchedWriteSizes<SchedWriteFLogic, SchedWriteFLogic, SchedWriteFLogic>;714def SchedWriteFShuffleSizes715 : X86SchedWriteSizes<SchedWriteFShuffle, SchedWriteFShuffle, SchedWriteFShuffle>;716 717//===----------------------------------------------------------------------===//718// Generic Processor Scheduler Models.719 720// IssueWidth is analogous to the number of decode units. Core and its721// descendents, including Nehalem and SandyBridge have 4 decoders.722// Resources beyond the decoder operate on micro-ops and are bufferred723// so adjacent micro-ops don't directly compete.724//725// MicroOpBufferSize > 1 indicates that RAW dependencies can be726// decoded in the same cycle. The value 32 is a reasonably arbitrary727// number of in-flight instructions.728//729// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef730// indicates high latency opcodes. Alternatively, InstrItinData731// entries may be included here to define specific operand732// latencies. Since these latencies are not used for pipeline hazards,733// they do not need to be exact.734//735// The GenericX86Model contains no instruction schedules736// and disables PostRAScheduler.737class GenericX86Model : SchedMachineModel {738 let IssueWidth = 4;739 let MicroOpBufferSize = 32;740 let LoadLatency = 4;741 let HighLatency = 10;742 let PostRAScheduler = 0;743 let CompleteModel = 0;744}745 746def GenericModel : GenericX86Model;747 748// Define a model with the PostRAScheduler enabled.749def GenericPostRAModel : GenericX86Model {750 let PostRAScheduler = 1;751}752