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1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the schedule class data for the Intel Atom10// in order (Saltwell-32nm/Bonnell-45nm) processors.11//12//===----------------------------------------------------------------------===//13 14//15// Scheduling information derived from the "Intel 64 and IA32 Architectures16// Optimization Reference Manual", Chapter 13, Section 4.17 18// Atom machine model.19def AtomModel : SchedMachineModel {20 let IssueWidth = 2; // Allows 2 instructions per scheduling group.21 let MicroOpBufferSize = 0; // In-order execution, always hide latency.22 let LoadLatency = 3; // Expected cycles, may be overriden.23 let HighLatency = 30;// Expected, may be overriden.24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small26 // simple loops, expand by a small factor to hide the backedge cost.27 let LoopMicroOpBufferSize = 10;28 let PostRAScheduler = 1;29 let CompleteModel = 0;30}31 32let SchedModel = AtomModel in {33 34// Functional Units35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA38 // SIMD/FP: SIMD ALU, FP Adder39 40// NOTE: This is for ops that can use EITHER port, not for ops that require BOTH ports.41def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>;42 43// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 344// cycles after the memory operand.45def : ReadAdvance<ReadAfterLd, 3>;46def : ReadAdvance<ReadAfterVecLd, 3>;47def : ReadAdvance<ReadAfterVecXLd, 3>;48def : ReadAdvance<ReadAfterVecYLd, 3>;49 50def : ReadAdvance<ReadInt2Fpu, 0>;51 52// This multiclass defines the resource usage for variants with and without53// folded loads.54multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,55 list<ProcResourceKind> RRPorts,56 list<ProcResourceKind> RMPorts,57 int RRLat = 1, int RMLat = 1,58 list<int> RRRes = [1],59 list<int> RMRes = [1],60 int RRUOps = 1,61 int RMUOps = 1> {62 // Register variant.63 def : WriteRes<SchedRW, RRPorts> {64 let Latency = RRLat;65 let ReleaseAtCycles = RRRes;66 let NumMicroOps = RRUOps;67 }68 69 // Memory variant.70 def : WriteRes<SchedRW.Folded, RMPorts> {71 let Latency = RMLat;72 let ReleaseAtCycles = RMRes;73 let NumMicroOps = RMUOps;74 }75}76 77// A folded store needs a cycle on Port0 for the store data.78def : WriteRes<WriteRMW, [AtomPort0]>;79 80////////////////////////////////////////////////////////////////////////////////81// Arithmetic.82////////////////////////////////////////////////////////////////////////////////83 84defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;85defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>;86 87defm : AtomWriteResPair<WriteIMul8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 7, [7,7], [7,7], 3, 3>;88defm : AtomWriteResPair<WriteIMul16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 4, 5>;89defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>;90defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>;91defm : AtomWriteResPair<WriteIMul32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>;92defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;93defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;94defm : AtomWriteResPair<WriteIMul64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 8, 8>;95defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 14, 14, [14,14], [14,14], 7, 7>;96defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 6, 6>;97defm : X86WriteResUnsupported<WriteIMulH>;98defm : X86WriteResUnsupported<WriteIMulHLd>;99defm : X86WriteResPairUnsupported<WriteMULX32>;100defm : X86WriteResPairUnsupported<WriteMULX64>;101 102defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>;103defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>;104defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>;105defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;106defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>;107 108defm : AtomWriteResPair<WriteDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 68, [50,50], [68,68], 9, 9>;109defm : AtomWriteResPair<WriteDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>;110defm : AtomWriteResPair<WriteDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>;111defm : AtomWriteResPair<WriteDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 38, 38>;112defm : AtomWriteResPair<WriteIDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 26, 26>;113defm : AtomWriteResPair<WriteIDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>;114defm : AtomWriteResPair<WriteIDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>;115defm : AtomWriteResPair<WriteIDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 60, 60>;116 117defm : X86WriteResPairUnsupported<WriteCRC32>;118 119defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>;120defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move.121 122def : WriteRes<WriteSETCC, [AtomPort01]>;123def : WriteRes<WriteSETCCStore, [AtomPort01]> {124 let Latency = 2;125 let ReleaseAtCycles = [2];126}127def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {128 let Latency = 2;129 let ReleaseAtCycles = [2];130}131defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;132defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;133defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;134defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;135//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>;136//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>;137 138// This is for simple LEAs with one or two input operands.139def : WriteRes<WriteLEA, [AtomPort1]>;140 141// Bit counts.142defm : AtomWriteResPair<WriteBSF, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 16, 16, [16,16], [16,16], 10, 10>;143defm : AtomWriteResPair<WriteBSR, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 16, 16, [16,16], [16,16], 10, 10>;144defm : X86WriteResPairUnsupported<WritePOPCNT>;145defm : X86WriteResPairUnsupported<WriteLZCNT>;146defm : X86WriteResPairUnsupported<WriteTZCNT>;147 148// BMI1 BEXTR/BLS, BMI2 BZHI149defm : X86WriteResPairUnsupported<WriteBEXTR>;150defm : X86WriteResPairUnsupported<WriteBLS>;151defm : X86WriteResPairUnsupported<WriteBZHI>;152 153////////////////////////////////////////////////////////////////////////////////154// Integer shifts and rotates.155////////////////////////////////////////////////////////////////////////////////156 157defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;158defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>;159defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>;160defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>;161 162defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>;163defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>;164defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>;165defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>;166 167////////////////////////////////////////////////////////////////////////////////168// Loads, stores, and moves, not folded with other operations.169////////////////////////////////////////////////////////////////////////////////170 171def : WriteRes<WriteLoad, [AtomPort0]>;172def : WriteRes<WriteStore, [AtomPort0]>;173def : WriteRes<WriteStoreNT, [AtomPort0]>;174def : WriteRes<WriteMove, [AtomPort01]>;175defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;176 177// Treat misc copies as a move.178def : InstRW<[WriteMove], (instrs COPY)>;179 180////////////////////////////////////////////////////////////////////////////////181// Idioms that clear a register, like xorps %xmm0, %xmm0.182// These can often bypass execution ports completely.183////////////////////////////////////////////////////////////////////////////////184 185def : WriteRes<WriteZero, []>;186 187////////////////////////////////////////////////////////////////////////////////188// Branches don't produce values, so they have no latency, but they still189// consume resources. Indirect branches can fold loads.190////////////////////////////////////////////////////////////////////////////////191 192defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;193 194////////////////////////////////////////////////////////////////////////////////195// Special case scheduling classes.196////////////////////////////////////////////////////////////////////////////////197 198def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }199def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }200def : WriteRes<WriteFence, [AtomPort0]>;201 202// Nops don't have dependencies, so there's no actual latency, but we set this203// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.204def : WriteRes<WriteNop, [AtomPort01]>;205 206////////////////////////////////////////////////////////////////////////////////207// Floating point. This covers both scalar and vector operations.208////////////////////////////////////////////////////////////////////////////////209 210defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>;211defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>;212def : WriteRes<WriteFLoad, [AtomPort0]>;213def : WriteRes<WriteFLoadX, [AtomPort0]>;214defm : X86WriteResUnsupported<WriteFLoadY>;215defm : X86WriteResUnsupported<WriteFMaskedLoad>;216defm : X86WriteResUnsupported<WriteFMaskedLoadY>;217 218def : WriteRes<WriteFStore, [AtomPort0]>;219def : WriteRes<WriteFStoreX, [AtomPort0]>;220defm : X86WriteResUnsupported<WriteFStoreY>;221def : WriteRes<WriteFStoreNT, [AtomPort0]>;222def : WriteRes<WriteFStoreNTX, [AtomPort0]>;223defm : X86WriteResUnsupported<WriteFStoreNTY>;224defm : X86WriteResUnsupported<WriteFMaskedStore32>;225defm : X86WriteResUnsupported<WriteFMaskedStore32Y>;226defm : X86WriteResUnsupported<WriteFMaskedStore64>;227defm : X86WriteResUnsupported<WriteFMaskedStore64Y>;228 229def : WriteRes<WriteFMove, [AtomPort01]>;230def : WriteRes<WriteFMoveX, [AtomPort01]>;231defm : X86WriteResUnsupported<WriteFMoveY>;232defm : X86WriteResUnsupported<WriteFMoveZ>;233 234defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>;235 236defm : AtomWriteResPair<WriteFAdd, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>;237defm : AtomWriteResPair<WriteFAddX, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>;238defm : X86WriteResPairUnsupported<WriteFAddY>;239defm : X86WriteResPairUnsupported<WriteFAddZ>;240defm : AtomWriteResPair<WriteFAdd64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>;241defm : AtomWriteResPair<WriteFAdd64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>;242defm : X86WriteResPairUnsupported<WriteFAdd64Y>;243defm : X86WriteResPairUnsupported<WriteFAdd64Z>;244defm : AtomWriteResPair<WriteFCmp, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>;245defm : AtomWriteResPair<WriteFCmpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>;246defm : X86WriteResPairUnsupported<WriteFCmpY>;247defm : X86WriteResPairUnsupported<WriteFCmpZ>;248defm : AtomWriteResPair<WriteFCmp64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>;249defm : AtomWriteResPair<WriteFCmp64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>;250defm : X86WriteResPairUnsupported<WriteFCmp64Y>;251defm : X86WriteResPairUnsupported<WriteFCmp64Z>;252defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;253defm : AtomWriteResPair<WriteFComX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9],[10,10], 4, 5>;254defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [2], [2]>;255defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>;256defm : X86WriteResPairUnsupported<WriteFMulY>;257defm : X86WriteResPairUnsupported<WriteFMulZ>;258defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>;259defm : AtomWriteResPair<WriteFMul64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9],[10,10], 6, 7>;260defm : X86WriteResPairUnsupported<WriteFMul64Y>;261defm : X86WriteResPairUnsupported<WriteFMul64Z>;262defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;263defm : AtomWriteResPair<WriteFRcpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10], 5, 6>;264defm : X86WriteResPairUnsupported<WriteFRcpY>;265defm : X86WriteResPairUnsupported<WriteFRcpZ>;266defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;267defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10], 5, 6>;268defm : X86WriteResPairUnsupported<WriteFRsqrtY>;269defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;270defm : AtomWriteResPair<WriteFDiv, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 34, 34, [34,34], [34,34], 3, 4>;271defm : AtomWriteResPair<WriteFDivX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 70, 70, [70,70], [70,70], 6, 7>;272defm : X86WriteResPairUnsupported<WriteFDivY>;273defm : X86WriteResPairUnsupported<WriteFDivZ>;274defm : AtomWriteResPair<WriteFDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 3, 4>;275defm : AtomWriteResPair<WriteFDiv64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],125,125,[125,125],[125,125], 6, 7>;276defm : X86WriteResPairUnsupported<WriteFDiv64Y>;277defm : X86WriteResPairUnsupported<WriteFDiv64Z>;278defm : AtomWriteResPair<WriteFSqrt, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 34, 34, [34,34], [34,34], 3, 4>;279defm : AtomWriteResPair<WriteFSqrtX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 70, 70, [70,70], [70,70], 5, 6>;280defm : X86WriteResPairUnsupported<WriteFSqrtY>;281defm : X86WriteResPairUnsupported<WriteFSqrtZ>;282defm : AtomWriteResPair<WriteFSqrt64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 3, 4>;283defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],125,125,[125,125],[125,125], 5, 6>;284defm : X86WriteResPairUnsupported<WriteFSqrt64Y>;285defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;286defm : AtomWriteResPair<WriteFSqrt80, [AtomPort0], [AtomPort0], 71, 71, [71], [71]>;287defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>;288defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;289defm : X86WriteResPairUnsupported<WriteFRndY>;290defm : X86WriteResPairUnsupported<WriteFRndZ>;291defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;292defm : X86WriteResPairUnsupported<WriteFLogicY>;293defm : X86WriteResPairUnsupported<WriteFLogicZ>;294defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>;295defm : X86WriteResPairUnsupported<WriteFTestY>;296defm : X86WriteResPairUnsupported<WriteFTestZ>;297defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;298defm : X86WriteResPairUnsupported<WriteFShuffleY>;299defm : X86WriteResPairUnsupported<WriteFShuffleZ>;300defm : X86WriteResPairUnsupported<WriteFVarShuffle>;301defm : X86WriteResPairUnsupported<WriteFVarShuffleY>;302defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;303defm : X86WriteResPairUnsupported<WriteFMA>;304defm : X86WriteResPairUnsupported<WriteFMAX>;305defm : X86WriteResPairUnsupported<WriteFMAY>;306defm : X86WriteResPairUnsupported<WriteFMAZ>;307defm : X86WriteResPairUnsupported<WriteDPPD>;308defm : X86WriteResPairUnsupported<WriteDPPS>;309defm : X86WriteResPairUnsupported<WriteDPPSY>;310defm : X86WriteResPairUnsupported<WriteFBlend>;311defm : X86WriteResPairUnsupported<WriteFBlendY>;312defm : X86WriteResPairUnsupported<WriteFBlendZ>;313defm : X86WriteResPairUnsupported<WriteFVarBlend>;314defm : X86WriteResPairUnsupported<WriteFVarBlendY>;315defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;316defm : X86WriteResPairUnsupported<WriteFShuffle256>;317defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;318 319////////////////////////////////////////////////////////////////////////////////320// Conversions.321////////////////////////////////////////////////////////////////////////////////322 323defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8], [9,9], 3, 4>;324defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>;325defm : X86WriteResPairUnsupported<WriteCvtPS2IY>;326defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;327defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8],[10,10], 3, 4>;328defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 4, 5>;329defm : X86WriteResPairUnsupported<WriteCvtPD2IY>;330defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;331 332defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [6,6], 3, 1>;333defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>;334defm : X86WriteResPairUnsupported<WriteCvtI2PSY>;335defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;336defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 3>;337defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7], 3, 4>;338defm : X86WriteResPairUnsupported<WriteCvtI2PDY>;339defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;340 341defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>;342defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7], 4, 5>;343defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>;344defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;345defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 10, 11,[10,10],[12,12], 3, 4>;346defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 11, 12,[11,11],[12,12], 4, 5>;347defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>;348defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;349 350defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;351defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;352defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;353defm : X86WriteResUnsupported<WriteCvtPS2PH>;354defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;355defm : X86WriteResUnsupported<WriteCvtPS2PHY>;356defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;357defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;358defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;359 360////////////////////////////////////////////////////////////////////////////////361// Vector integer operations.362////////////////////////////////////////////////////////////////////////////////363 364def : WriteRes<WriteVecLoad, [AtomPort0]>;365def : WriteRes<WriteVecLoadX, [AtomPort0]>;366defm : X86WriteResUnsupported<WriteVecLoadY>;367def : WriteRes<WriteVecLoadNT, [AtomPort0]>;368defm : X86WriteResUnsupported<WriteVecLoadNTY>;369defm : X86WriteResUnsupported<WriteVecMaskedLoad>;370defm : X86WriteResUnsupported<WriteVecMaskedLoadY>;371 372def : WriteRes<WriteVecStore, [AtomPort0]>;373def : WriteRes<WriteVecStoreX, [AtomPort0]>;374defm : X86WriteResUnsupported<WriteVecStoreY>;375def : WriteRes<WriteVecStoreNT, [AtomPort0]>;376defm : X86WriteResUnsupported<WriteVecStoreNTY>;377defm : X86WriteResUnsupported<WriteVecMaskedStore32>;378defm : X86WriteResUnsupported<WriteVecMaskedStore64>;379defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>;380defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>;381 382def : WriteRes<WriteVecMove, [AtomPort0]>;383def : WriteRes<WriteVecMoveX, [AtomPort01]>;384defm : X86WriteResUnsupported<WriteVecMoveY>;385defm : X86WriteResUnsupported<WriteVecMoveZ>;386defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>;387defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>;388 389defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>;390defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>;391defm : X86WriteResPairUnsupported<WriteVecALUY>;392defm : X86WriteResPairUnsupported<WriteVecALUZ>;393defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;394defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>;395defm : X86WriteResPairUnsupported<WriteVecLogicY>;396defm : X86WriteResPairUnsupported<WriteVecLogicZ>;397defm : X86WriteResPairUnsupported<WriteVecTest>;398defm : X86WriteResPairUnsupported<WriteVecTestY>;399defm : X86WriteResPairUnsupported<WriteVecTestZ>;400defm : AtomWriteResPair<WriteVecShift, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2], 2, 3>;401defm : AtomWriteResPair<WriteVecShiftX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2], 2, 3>;402defm : X86WriteResPairUnsupported<WriteVecShiftY>;403defm : X86WriteResPairUnsupported<WriteVecShiftZ>;404defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort0], [AtomPort0], 1, 1>;405defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort0], [AtomPort0], 1, 1>;406defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;407defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;408defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>;409defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>;410defm : X86WriteResPairUnsupported<WriteVecIMulY>;411defm : X86WriteResPairUnsupported<WriteVecIMulZ>;412defm : X86WriteResPairUnsupported<WritePMULLD>;413defm : X86WriteResPairUnsupported<WritePMULLDY>;414defm : X86WriteResPairUnsupported<WritePMULLDZ>;415defm : X86WriteResPairUnsupported<WritePHMINPOS>;416defm : X86WriteResPairUnsupported<WriteMPSAD>;417defm : X86WriteResPairUnsupported<WriteMPSADY>;418defm : X86WriteResPairUnsupported<WriteMPSADZ>;419defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>;420defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>;421defm : X86WriteResPairUnsupported<WritePSADBWY>;422defm : X86WriteResPairUnsupported<WritePSADBWZ>;423defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;424defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>;425defm : X86WriteResPairUnsupported<WriteShuffleY>;426defm : X86WriteResPairUnsupported<WriteShuffleZ>;427defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>;428defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 4, 5, [3,3], [4,4], 4, 5>;429defm : X86WriteResPairUnsupported<WriteVarShuffleY>;430defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;431defm : X86WriteResPairUnsupported<WriteBlend>;432defm : X86WriteResPairUnsupported<WriteBlendY>;433defm : X86WriteResPairUnsupported<WriteBlendZ>;434defm : X86WriteResPairUnsupported<WriteVarBlend>;435defm : X86WriteResPairUnsupported<WriteVarBlendY>;436defm : X86WriteResPairUnsupported<WriteVarBlendZ>;437defm : X86WriteResPairUnsupported<WriteShuffle256>;438defm : X86WriteResPairUnsupported<WriteVPMOV256>;439defm : X86WriteResPairUnsupported<WriteVarShuffle256>;440defm : X86WriteResPairUnsupported<WriteVarVecShift>;441defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;442defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;443 444////////////////////////////////////////////////////////////////////////////////445// Vector insert/extract operations.446////////////////////////////////////////////////////////////////////////////////447 448defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>;449def : WriteRes<WriteVecExtract, [AtomPort0]>;450def : WriteRes<WriteVecExtractSt, [AtomPort0]>;451 452////////////////////////////////////////////////////////////////////////////////453// SSE42 String instructions.454////////////////////////////////////////////////////////////////////////////////455 456defm : X86WriteResPairUnsupported<WritePCmpIStrI>;457defm : X86WriteResPairUnsupported<WritePCmpIStrM>;458defm : X86WriteResPairUnsupported<WritePCmpEStrI>;459defm : X86WriteResPairUnsupported<WritePCmpEStrM>;460 461////////////////////////////////////////////////////////////////////////////////462// MOVMSK Instructions.463////////////////////////////////////////////////////////////////////////////////464 465def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }466def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }467defm : X86WriteResUnsupported<WriteVecMOVMSKY>;468def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }469 470////////////////////////////////////////////////////////////////////////////////471// AES instructions.472////////////////////////////////////////////////////////////////////////////////473 474defm : X86WriteResPairUnsupported<WriteAESIMC>;475defm : X86WriteResPairUnsupported<WriteAESKeyGen>;476defm : X86WriteResPairUnsupported<WriteAESDecEnc>;477 478////////////////////////////////////////////////////////////////////////////////479// Horizontal add/sub instructions.480////////////////////////////////////////////////////////////////////////////////481 482defm : AtomWriteResPair<WriteFHAdd, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8], [9,9], 5, 6>;483defm : X86WriteResPairUnsupported<WriteFHAddY>;484defm : AtomWriteResPair<WritePHAdd, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 3, 4, [3,3], [4,4], 3, 4>;485defm : AtomWriteResPair<WritePHAddX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 3, 4>;486defm : X86WriteResPairUnsupported<WritePHAddY>;487 488////////////////////////////////////////////////////////////////////////////////489// Carry-less multiplication instructions.490////////////////////////////////////////////////////////////////////////////////491 492defm : X86WriteResPairUnsupported<WriteCLMul>;493 494////////////////////////////////////////////////////////////////////////////////495// Load/store MXCSR.496////////////////////////////////////////////////////////////////////////////////497 498defm : X86WriteRes<WriteLDMXCSR, [AtomPort0,AtomPort1], 5, [5,5], 4>;499defm : X86WriteRes<WriteSTMXCSR, [AtomPort0,AtomPort1], 15, [15,15], 4>;500 501////////////////////////////////////////////////////////////////////////////////502// Special Cases.503////////////////////////////////////////////////////////////////////////////////504 505// Port0506def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {507 let Latency = 1;508 let ReleaseAtCycles = [1];509}510def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr,511 MOVSX64rr32)>;512def : SchedAlias<WriteALURMW, AtomWrite0_1>;513def : SchedAlias<WriteADCRMW, AtomWrite0_1>;514def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",515 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;516 517// Port1518def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {519 let Latency = 1;520 let ReleaseAtCycles = [1];521}522def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;523def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;524 525def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {526 let Latency = 5;527 let ReleaseAtCycles = [5];528}529def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,530 MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>;531 532// Port0 and Port1533def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {534 let Latency = 1;535 let ReleaseAtCycles = [1, 1];536}537def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,538 POP16rmr, POP32rmr, POP64rmr,539 PUSH16r, PUSH32r, PUSH64r,540 PUSH16i, PUSH32i,541 PUSH16rmr, PUSH32rmr, PUSH64rmr,542 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,543 XCH_F)>;544def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",545 "IRET(16|32|64)?")>;546 547def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {548 let Latency = 5;549 let ReleaseAtCycles = [5, 5];550}551def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>;552def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;553 554def AtomWrite0_1_7 : SchedWriteRes<[AtomPort0,AtomPort1]> {555 let Latency = 7;556 let ReleaseAtCycles = [6,6];557}558def : InstRW<[AtomWrite0_1_7], (instregex "CVTSI642SDrm(_Int)?")>;559 560def AtomWrite0_1_7_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {561 let Latency = 7;562 let ReleaseAtCycles = [8,8];563 let NumMicroOps = 4;564}565def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSr(r|m)(_Int)?")>;566 567def AtomWrite0_1_9 : SchedWriteRes<[AtomPort0,AtomPort1]> {568 let Latency = 9;569 let ReleaseAtCycles = [9,9];570 let NumMicroOps = 4;571}572def : InstRW<[AtomWrite0_1_9], (instregex "CVT(T)?SS2SI64rr(_Int)?")>;573 574def AtomWrite0_1_10 : SchedWriteRes<[AtomPort0,AtomPort1]> {575 let Latency = 10;576 let ReleaseAtCycles = [11,11];577 let NumMicroOps = 5;578}579def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;580 581// Port0 or Port1582def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {583 let Latency = 1;584 let ReleaseAtCycles = [1];585}586def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,587 LFENCE,588 STOSB, STOSL, STOSQ, STOSW,589 MOVSSrr, MOVSSrr_REV)>;590 591def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {592 let Latency = 2;593 let ReleaseAtCycles = [2];594}595def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,596 PUSH16rmm, PUSH32rmm, PUSH64rmm,597 LODSB, LODSL, LODSQ, LODSW,598 SCASB, SCASL, SCASQ, SCASW)>;599def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",600 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",601 "MMX_P(ADD|SUB)Qrr",602 "MOV(S|Z)X16rr8",603 "MOV(UPS|UPD|DQU)mr",604 "MASKMOVDQU(64)?",605 "P(ADD|SUB)Qrr")>;606def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;607 608def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {609 let Latency = 3;610 let ReleaseAtCycles = [3];611}612def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,613 CMPSB, CMPSL, CMPSQ, CMPSW,614 MOVSB, MOVSL, MOVSQ, MOVSW,615 POP16rmm, POP32rmm, POP64rmm)>;616def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",617 "XCHG(8|16|32|64)rm",618 "PH(ADD|SUB)Drr",619 "MOV(S|Z)X16rm8",620 "MMX_P(ADD|SUB)Qrm",621 "MOV(UPS|UPD|DQU)rm",622 "P(ADD|SUB)Qrm")>;623 624def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {625 let Latency = 4;626 let ReleaseAtCycles = [4];627}628def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,629 JCXZ, JECXZ, JRCXZ,630 LD_F80m)>;631def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",632 "(MMX_)?PEXTRWrr(_REV)?")>;633 634def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {635 let Latency = 5;636 let ReleaseAtCycles = [5];637}638def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;639def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;640 641def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {642 let Latency = 6;643 let ReleaseAtCycles = [6];644}645def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,646 SHLD16rrCL, SHRD16rrCL,647 SHLD16rri8, SHRD16rri8,648 SHLD16mrCL, SHRD16mrCL,649 SHLD16mri8, SHRD16mri8)>;650def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",651 "MMX_PH(ADD|SUB)S?Wrm")>;652 653def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {654 let Latency = 7;655 let ReleaseAtCycles = [7];656}657def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;658 659def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {660 let Latency = 8;661 let ReleaseAtCycles = [8];662}663def : InstRW<[AtomWrite01_8], (instrs LOOPE,664 PUSHA16, PUSHA32,665 SHLD64rrCL, SHRD64rrCL,666 FNSTCW16m)>;667 668def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {669 let Latency = 9;670 let ReleaseAtCycles = [9];671}672def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,673 PUSHF16, PUSHF32, PUSHF64,674 SHLD64mrCL, SHRD64mrCL,675 SHLD64mri8, SHRD64mri8,676 SHLD64rri8, SHRD64rri8,677 CMPXCHG8rr)>;678def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F")>;679 680def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {681 let Latency = 10;682 let ReleaseAtCycles = [10];683}684def : SchedAlias<WriteFLDC, AtomWrite01_10>;685 686def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {687 let Latency = 11;688 let ReleaseAtCycles = [11];689}690def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;691def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;692 693def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {694 let Latency = 13;695 let ReleaseAtCycles = [13];696}697def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;698 699def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {700 let Latency = 14;701 let ReleaseAtCycles = [14];702}703def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;704 705def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {706 let Latency = 17;707 let ReleaseAtCycles = [17];708}709def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;710 711def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {712 let Latency = 18;713 let ReleaseAtCycles = [18];714}715def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;716 717def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {718 let Latency = 20;719 let ReleaseAtCycles = [20];720}721def : InstRW<[AtomWrite01_20], (instrs DAS)>;722 723def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {724 let Latency = 21;725 let ReleaseAtCycles = [21];726}727def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;728 729def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {730 let Latency = 22;731 let ReleaseAtCycles = [22];732}733def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;734 735def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {736 let Latency = 23;737 let ReleaseAtCycles = [23];738}739def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;740 741def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {742 let Latency = 25;743 let ReleaseAtCycles = [25];744}745def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;746 747def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {748 let Latency = 26;749 let ReleaseAtCycles = [26];750}751def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;752 753def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {754 let Latency = 29;755 let ReleaseAtCycles = [29];756}757def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;758 759def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {760 let Latency = 30;761 let ReleaseAtCycles = [30];762}763def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;764 765def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {766 let Latency = 32;767 let ReleaseAtCycles = [32];768}769def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;770 771def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {772 let Latency = 45;773 let ReleaseAtCycles = [45];774}775def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;776 777def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {778 let Latency = 46;779 let ReleaseAtCycles = [46];780}781def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;782 783def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {784 let Latency = 48;785 let ReleaseAtCycles = [48];786}787def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;788 789def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {790 let Latency = 55;791 let ReleaseAtCycles = [55];792}793def : InstRW<[AtomWrite01_55], (instrs FPREM)>;794 795def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {796 let Latency = 59;797 let ReleaseAtCycles = [59];798}799def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;800 801def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {802 let Latency = 63;803 let ReleaseAtCycles = [63];804}805def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;806 807def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {808 let Latency = 68;809 let ReleaseAtCycles = [68];810}811def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;812 813def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {814 let Latency = 71;815 let ReleaseAtCycles = [71];816}817def : InstRW<[AtomWrite01_71], (instrs FPREM1,818 INVLPG, INVLPGA32, INVLPGA64)>;819 820def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {821 let Latency = 72;822 let ReleaseAtCycles = [72];823}824def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;825 826def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {827 let Latency = 74;828 let ReleaseAtCycles = [74];829}830def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;831 832def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {833 let Latency = 77;834 let ReleaseAtCycles = [77];835}836def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;837 838def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {839 let Latency = 78;840 let ReleaseAtCycles = [78];841}842def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;843 844def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {845 let Latency = 79;846 let ReleaseAtCycles = [79];847}848def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",849 "LRETI?(16|32|64)")>;850 851def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {852 let Latency = 92;853 let ReleaseAtCycles = [92];854}855def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;856 857def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {858 let Latency = 94;859 let ReleaseAtCycles = [94];860}861def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;862 863def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {864 let Latency = 99;865 let ReleaseAtCycles = [99];866}867def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;868 869def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {870 let Latency = 121;871 let ReleaseAtCycles = [121];872}873def : InstRW<[AtomWrite01_121], (instrs CPUID)>;874 875def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {876 let Latency = 127;877 let ReleaseAtCycles = [127];878}879def : InstRW<[AtomWrite01_127], (instrs INT)>;880 881def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {882 let Latency = 130;883 let ReleaseAtCycles = [130];884}885def : InstRW<[AtomWrite01_130], (instrs INT3)>;886 887def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {888 let Latency = 140;889 let ReleaseAtCycles = [140];890}891def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;892 893def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {894 let Latency = 141;895 let ReleaseAtCycles = [141];896}897def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;898 899def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {900 let Latency = 146;901 let ReleaseAtCycles = [146];902}903def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;904 905def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {906 let Latency = 147;907 let ReleaseAtCycles = [147];908}909def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;910 911def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {912 let Latency = 168;913 let ReleaseAtCycles = [168];914}915def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;916 917def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {918 let Latency = 174;919 let ReleaseAtCycles = [174];920}921def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;922 923def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {924 let Latency = 183;925 let ReleaseAtCycles = [183];926}927def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;928 929def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {930 let Latency = 202;931 let ReleaseAtCycles = [202];932}933def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;934 935} // SchedModel936