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1//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Intel Silvermont to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14def SLMModel : SchedMachineModel {15 // All x86 instructions are modeled as a single micro-op, and SLM can decode 216 // instructions per cycle.17 let IssueWidth = 2;18 let MicroOpBufferSize = 32; // Based on the reorder buffer.19 let LoadLatency = 3;20 let MispredictPenalty = 10;21 let PostRAScheduler = 1;22 23 // For small loops, expand by a small factor to hide the backedge cost.24 let LoopMicroOpBufferSize = 10;25 26 // FIXME: SSE4 is unimplemented. This flag is set to allow27 // the scheduler to assign a default model to unrecognized opcodes.28 let CompleteModel = 0;29}30 31let SchedModel = SLMModel in {32 33// Silvermont has 5 reservation stations for micro-ops34def SLM_IEC_RSV0 : ProcResource<1>;35def SLM_IEC_RSV1 : ProcResource<1>;36def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }37def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }38def SLM_MEC_RSV : ProcResource<1>;39 40// Many micro-ops are capable of issuing on multiple ports.41def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;42def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;43 44def SLMDivider : ProcResource<1>;45def SLMFPMultiplier : ProcResource<1>;46def SLMFPDivider : ProcResource<1>;47 48// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 349// cycles after the memory operand.50def : ReadAdvance<ReadAfterLd, 3>;51def : ReadAdvance<ReadAfterVecLd, 3>;52def : ReadAdvance<ReadAfterVecXLd, 3>;53def : ReadAdvance<ReadAfterVecYLd, 3>;54 55def : ReadAdvance<ReadInt2Fpu, 0>;56 57// Many SchedWrites are defined in pairs with and without a folded load.58// Instructions with folded loads are usually micro-fused, so they only appear59// as two micro-ops when queued in the reservation station.60// This multiclass defines the resource usage for variants with and without61// folded loads.62multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,63 list<ProcResourceKind> ExePorts,64 int Lat, list<int> Res = [1], int UOps = 1,65 int LoadUOps = 0, int LoadLat = 3> {66 // Register variant is using a single cycle on ExePort.67 def : WriteRes<SchedRW, ExePorts> {68 let Latency = Lat;69 let ReleaseAtCycles = Res;70 let NumMicroOps = UOps;71 }72 73 // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to74 // the latency (default = 3).75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {76 let Latency = !add(Lat, LoadLat);77 let ReleaseAtCycles = !listconcat([1], Res);78 let NumMicroOps = !add(UOps, LoadUOps);79 }80}81 82// A folded store needs a cycle on MEC_RSV for the store data (using the same uop),83// but it does not need an extra port cycle to recompute the address.84def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; }85 86def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;87def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;88def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }89def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;90def : WriteRes<WriteZero, []>;91defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;92 93// Load/store MXCSR.94defm : X86WriteRes<WriteSTMXCSR, [SLM_MEC_RSV], 12,[11], 4>;95defm : X86WriteRes<WriteLDMXCSR, [SLM_MEC_RSV], 10, [8], 5>;96 97// Treat misc copies as a move.98def : InstRW<[WriteMove], (instrs COPY)>;99 100defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;101defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>;102 103defm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 5, [5], 3>;104defm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 5, [5], 4, 1>;105defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 4, [4], 2, 1>;106defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 4, [4], 2, 1>;107defm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 5, [5], 3, 1>;108defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>;109defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>;110defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 7, [7], 3>;111defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 5, [2]>;112defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 5, [2]>;113defm : X86WriteResUnsupported<WriteIMulH>;114defm : X86WriteResUnsupported<WriteIMulHLd>;115defm : X86WriteResPairUnsupported<WriteMULX32>;116defm : X86WriteResPairUnsupported<WriteMULX64>;117 118defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;119defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;120defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 6, [6], 5>;121defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 10, [6, 2], 8>;122defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 3, [3], 3>;123 124defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;125defm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>;126defm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>;127defm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>;128 129defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>;130defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>;131defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;132defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;133 134defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;135defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>;136 137defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>;138defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move.139def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;140def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {141 // FIXME Latency and NumMicrOps?142 let ReleaseAtCycles = [2,1];143}144defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;145defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;146defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 1>;147defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 7>;148defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;149defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 1>;150defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 8>;151 152// This is for simple LEAs with one or two input operands.153// The complex ones can only execute on port 1, and they require two cycles on154// the port to read all inputs. We don't model that.155def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;156 157// Bit counts.158defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>;159defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>;160defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;161defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;162defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;163 164// BMI1 BEXTR/BLS, BMI2 BZHI165defm : X86WriteResPairUnsupported<WriteBEXTR>;166defm : X86WriteResPairUnsupported<WriteBLS>;167defm : X86WriteResPairUnsupported<WriteBZHI>;168 169defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;170defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;171defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;172defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;173defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;174defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;175defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;176defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>;177 178// Scalar and vector floating point.179defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>;180defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>;181defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>;182def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }183def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; }184defm : X86WriteResUnsupported<WriteFLoadY>;185def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }186defm : X86WriteResUnsupported<WriteFMaskedLoadY>;187def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;188def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>;189defm : X86WriteResUnsupported<WriteFStoreY>;190def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>;191def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>;192defm : X86WriteResUnsupported<WriteFStoreNTY>;193 194def : WriteRes<WriteFMaskedStore32, [SLM_MEC_RSV]>;195defm : X86WriteResUnsupported<WriteFMaskedStore32Y>;196def : WriteRes<WriteFMaskedStore64, [SLM_MEC_RSV]>;197defm : X86WriteResUnsupported<WriteFMaskedStore64Y>;198 199def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;200def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>;201defm : X86WriteResUnsupported<WriteFMoveY>;202defm : X86WriteResUnsupported<WriteFMoveZ>;203defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>;204 205defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;206defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>;207defm : X86WriteResPairUnsupported<WriteFAddY>;208defm : X86WriteResPairUnsupported<WriteFAddZ>;209defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>;210defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 4, [2]>;211defm : X86WriteResPairUnsupported<WriteFAdd64Y>;212defm : X86WriteResPairUnsupported<WriteFAdd64Z>;213defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;214defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>;215defm : X86WriteResPairUnsupported<WriteFCmpY>;216defm : X86WriteResPairUnsupported<WriteFCmpZ>;217defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>;218defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>;219defm : X86WriteResPairUnsupported<WriteFCmp64Y>;220defm : X86WriteResPairUnsupported<WriteFCmp64Z>;221defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;222defm : SLMWriteResPair<WriteFComX, [SLM_FPC_RSV1], 3>;223defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;224defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;225defm : X86WriteResPairUnsupported<WriteFMulY>;226defm : X86WriteResPairUnsupported<WriteFMulZ>;227defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;228defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>;229defm : X86WriteResPairUnsupported<WriteFMul64Y>;230defm : X86WriteResPairUnsupported<WriteFMul64Z>;231defm : X86WriteResPairUnsupported<WriteFMA>;232defm : X86WriteResPairUnsupported<WriteFMAX>;233defm : X86WriteResPairUnsupported<WriteFMAY>;234defm : X86WriteResPairUnsupported<WriteFMAZ>;235defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>;236defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39], 6, 1>;237defm : X86WriteResPairUnsupported<WriteFDivY>;238defm : X86WriteResPairUnsupported<WriteFDivZ>;239defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>;240defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69], 6, 1>;241defm : X86WriteResPairUnsupported<WriteFDiv64Y>;242defm : X86WriteResPairUnsupported<WriteFDiv64Z>;243defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 4>;244defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 9, [8], 5, 1>;245defm : X86WriteResPairUnsupported<WriteFRcpY>;246defm : X86WriteResPairUnsupported<WriteFRcpZ>;247defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 4>;248defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 9, [8], 5, 1>;249defm : X86WriteResPairUnsupported<WriteFRsqrtY>;250defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;251defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0, SLMFPDivider], 20, [1,20]>;252defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0, SLMFPDivider], 41, [1,40], 5, 1>;253defm : X86WriteResPairUnsupported<WriteFSqrtY>;254defm : X86WriteResPairUnsupported<WriteFSqrtZ>;255defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0, SLMFPDivider], 35, [1,35]>;256defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0, SLMFPDivider], 71, [1,70], 5, 1>;257defm : X86WriteResPairUnsupported<WriteFSqrt64Y>;258defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;259defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>;260defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 12, [8], 5, 1>;261defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 15, [12], 9, 1>;262defm : X86WriteResPairUnsupported<WriteDPPSY>;263defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>;264defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>;265defm : X86WriteResPairUnsupported<WriteFRndY>;266defm : X86WriteResPairUnsupported<WriteFRndZ>;267defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;268defm : X86WriteResPairUnsupported<WriteFLogicY>;269defm : X86WriteResPairUnsupported<WriteFLogicZ>;270defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>;271defm : X86WriteResPairUnsupported<WriteFTestY>;272defm : X86WriteResPairUnsupported<WriteFTestZ>;273defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;274defm : X86WriteResPairUnsupported<WriteFShuffleY>;275defm : X86WriteResPairUnsupported<WriteFShuffleZ>;276defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;277defm : X86WriteResPairUnsupported<WriteFVarShuffleY>;278defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;279defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;280defm : X86WriteResPairUnsupported<WriteFBlendY>;281defm : X86WriteResPairUnsupported<WriteFBlendZ>;282defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>;283defm : X86WriteResPairUnsupported<WriteFVarBlendY>;284defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;285defm : X86WriteResPairUnsupported<WriteFShuffle256>;286defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;287 288// Conversion between integer and float.289defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV0], 5>;290defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV0], 5, [2]>;291defm : X86WriteResPairUnsupported<WriteCvtPS2IY>;292defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;293defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV0], 5>;294defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV0], 5, [2]>;295defm : X86WriteResPairUnsupported<WriteCvtPD2IY>;296defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;297 298defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV0], 5, [2]>;299defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV0], 5, [2]>;300defm : X86WriteResPairUnsupported<WriteCvtI2PSY>;301defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;302defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV0], 5, [2]>;303defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV0], 5, [2]>;304defm : X86WriteResPairUnsupported<WriteCvtI2PDY>;305defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;306 307defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV0], 4, [2]>;308defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV0], 5, [2]>;309defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>;310defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;311defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV0], 4, [2]>;312defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV0], 5, [2]>;313defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>;314defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;315 316defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;317defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;318defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;319 320defm : X86WriteResUnsupported<WriteCvtPS2PH>;321defm : X86WriteResUnsupported<WriteCvtPS2PHY>;322defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;323defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;324defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;325defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;326 327// Vector integer operations.328def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }329def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; }330defm : X86WriteResUnsupported<WriteVecLoadY>;331def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; }332defm : X86WriteResUnsupported<WriteVecLoadNTY>;333def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }334defm : X86WriteResUnsupported<WriteVecMaskedLoadY>;335def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>;336def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>;337defm : X86WriteResUnsupported<WriteVecStoreY>;338def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>;339defm : X86WriteResUnsupported<WriteVecStoreNTY>;340def : WriteRes<WriteVecMaskedStore32, [SLM_MEC_RSV]>;341defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>;342def : WriteRes<WriteVecMaskedStore64, [SLM_MEC_RSV]>;343defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>;344def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;345def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>;346defm : X86WriteResUnsupported<WriteVecMoveY>;347defm : X86WriteResUnsupported<WriteVecMoveZ>;348def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>;349def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>;350 351defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 2, [2]>;352defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 2, [2]>;353defm : X86WriteResPairUnsupported<WriteVecShiftY>;354defm : X86WriteResPairUnsupported<WriteVecShiftZ>;355defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>;356defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>;357defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;358defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;359defm : X86WriteResPairUnsupported<WriteVarVecShift>;360defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;361defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;362 363defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;364defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>;365defm : X86WriteResPairUnsupported<WriteVecLogicY>;366defm : X86WriteResPairUnsupported<WriteVecLogicZ>;367defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>;368defm : X86WriteResPairUnsupported<WriteVecTestY>;369defm : X86WriteResPairUnsupported<WriteVecTestZ>;370defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;371defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>;372defm : X86WriteResPairUnsupported<WriteVecALUY>;373defm : X86WriteResPairUnsupported<WriteVecALUZ>;374defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;375defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 5, [2]>;376defm : X86WriteResPairUnsupported<WriteVecIMulY>;377defm : X86WriteResPairUnsupported<WriteVecIMulZ>;378defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;379defm : X86WriteResPairUnsupported<WritePMULLDY>;380defm : X86WriteResPairUnsupported<WritePMULLDZ>;381defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;382defm : X86WriteResPairUnsupported<WriteShuffleY>;383defm : X86WriteResPairUnsupported<WriteShuffleZ>;384defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>;385defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;386defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 5, [5], 4, 1>;387defm : X86WriteResPairUnsupported<WriteVarShuffleY>;388defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;389defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;390defm : X86WriteResPairUnsupported<WriteBlendY>;391defm : X86WriteResPairUnsupported<WriteBlendZ>;392defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>;393defm : X86WriteResPairUnsupported<WriteVarBlendY>;394defm : X86WriteResPairUnsupported<WriteVarBlendZ>;395defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7, [5], 3, 1>;396defm : X86WriteResPairUnsupported<WriteMPSADY>;397defm : X86WriteResPairUnsupported<WriteMPSADZ>;398defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;399defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 5, [2]>;400defm : X86WriteResPairUnsupported<WritePSADBWY>;401defm : X86WriteResPairUnsupported<WritePSADBWZ>;402defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;403defm : X86WriteResPairUnsupported<WriteShuffle256>;404defm : X86WriteResPairUnsupported<WriteVarShuffle256>;405defm : X86WriteResPairUnsupported<WriteVPMOV256>;406 407// Vector insert/extract operations.408defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>;409 410def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {411 let NumMicroOps = 2;412}413def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {414 let Latency = 4;415 let NumMicroOps = 5;416 let ReleaseAtCycles = [1, 2];417}418 419////////////////////////////////////////////////////////////////////////////////420// Horizontal add/sub instructions.421////////////////////////////////////////////////////////////////////////////////422 423defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV1], 6, [6], 4, 1>;424defm : X86WriteResPairUnsupported<WriteFHAddY>;425defm : X86WriteResPairUnsupported<WriteFHAddZ>;426defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 6, [6], 3, 1>;427defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 6, [6], 3, 1>;428defm : X86WriteResPairUnsupported<WritePHAddY>;429defm : X86WriteResPairUnsupported<WritePHAddZ>;430 431// String instructions.432// Packed Compare Implicit Length Strings, Return Mask433defm : SLMWriteResPair<WritePCmpIStrM, [SLM_FPC_RSV0], 13, [13], 5, 1>;434 435// Packed Compare Explicit Length Strings, Return Mask436defm : SLMWriteResPair<WritePCmpEStrM, [SLM_FPC_RSV0], 17, [17], 8, 1>;437 438// Packed Compare Implicit Length Strings, Return Index439defm : SLMWriteResPair<WritePCmpIStrI, [SLM_FPC_RSV0], 17, [17], 6, 1>;440 441// Packed Compare Explicit Length Strings, Return Index442defm : SLMWriteResPair<WritePCmpEStrI, [SLM_FPC_RSV0], 21, [21], 9, 1>;443 444// MOVMSK Instructions.445def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }446def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }447def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }448defm : X86WriteResUnsupported<WriteVecMOVMSKY>;449 450// AES Instructions.451defm : SLMWriteResPair<WriteAESDecEnc, [SLM_FPC_RSV0], 8, [5], 4, 1>;452defm : SLMWriteResPair<WriteAESIMC, [SLM_FPC_RSV0], 8, [4], 3, 1>;453defm : SLMWriteResPair<WriteAESKeyGen, [SLM_FPC_RSV0], 8, [4], 3, 1>;454 455// Carry-less multiplication instructions.456defm : SLMWriteResPair<WriteCLMul, [SLM_FPC_RSV0], 10, [10], 8, 1>;457 458def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; }459def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }460def : WriteRes<WriteFence, [SLM_MEC_RSV]>;461def : WriteRes<WriteNop, []>;462 463// Remaining SLM instrs.464 465def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {466 let Latency = 4;467 let NumMicroOps = 2;468 let ReleaseAtCycles = [8];469}470def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,471 MMX_PSUBQrr, PSUBQrr,472 PCMPEQQrr)>;473 474def SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> {475 let Latency = 5;476 let NumMicroOps = 1;477 let ReleaseAtCycles = [2];478}479def: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>;480 481def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {482 let Latency = 7;483 let NumMicroOps = 3;484 let ReleaseAtCycles = [1,8];485}486 487def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,488 MMX_PSUBQrm, PSUBQrm,489 PCMPEQQrm)>;490 491def SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> {492 let Latency = 8;493 let NumMicroOps = 2;494 let ReleaseAtCycles = [1,2];495}496def: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>;497 498///////////////////////////////////////////////////////////////////////////////499// Dependency breaking instructions.500///////////////////////////////////////////////////////////////////////////////501 502def : IsZeroIdiomFunction<[503 // GPR Zero-idioms.504 DepBreakingClass<[ XOR32rr ], ZeroIdiomPredicate>,505 506 // SSE Zero-idioms.507 DepBreakingClass<[508 // fp variants.509 XORPSrr, XORPDrr,510 511 // int variants.512 PXORrr,513 ], ZeroIdiomPredicate>,514]>;515 516} // SchedModel517