654 lines · cpp
1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the X86 specific subclass of TargetMachine.10//11//===----------------------------------------------------------------------===//12 13#include "X86TargetMachine.h"14#include "MCTargetDesc/X86MCTargetDesc.h"15#include "TargetInfo/X86TargetInfo.h"16#include "X86.h"17#include "X86MachineFunctionInfo.h"18#include "X86MacroFusion.h"19#include "X86Subtarget.h"20#include "X86TargetObjectFile.h"21#include "X86TargetTransformInfo.h"22#include "llvm-c/Visibility.h"23#include "llvm/ADT/SmallString.h"24#include "llvm/ADT/StringRef.h"25#include "llvm/Analysis/TargetTransformInfo.h"26#include "llvm/CodeGen/ExecutionDomainFix.h"27#include "llvm/CodeGen/GlobalISel/CSEInfo.h"28#include "llvm/CodeGen/GlobalISel/CallLowering.h"29#include "llvm/CodeGen/GlobalISel/IRTranslator.h"30#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"31#include "llvm/CodeGen/GlobalISel/Legalizer.h"32#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"33#include "llvm/CodeGen/MIRParser/MIParser.h"34#include "llvm/CodeGen/MIRYamlMapping.h"35#include "llvm/CodeGen/MachineScheduler.h"36#include "llvm/CodeGen/Passes.h"37#include "llvm/CodeGen/TargetPassConfig.h"38#include "llvm/IR/Attributes.h"39#include "llvm/IR/DataLayout.h"40#include "llvm/IR/Function.h"41#include "llvm/MC/MCAsmInfo.h"42#include "llvm/MC/TargetRegistry.h"43#include "llvm/Pass.h"44#include "llvm/Support/CodeGen.h"45#include "llvm/Support/CommandLine.h"46#include "llvm/Support/ErrorHandling.h"47#include "llvm/Target/TargetLoweringObjectFile.h"48#include "llvm/Target/TargetOptions.h"49#include "llvm/TargetParser/Triple.h"50#include "llvm/Transforms/CFGuard.h"51#include <memory>52#include <optional>53 54using namespace llvm;55 56static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",57 cl::desc("Enable the machine combiner pass"),58 cl::init(true), cl::Hidden);59 60static cl::opt<bool>61 EnableTileRAPass("x86-tile-ra",62 cl::desc("Enable the tile register allocation pass"),63 cl::init(true), cl::Hidden);64 65extern "C" LLVM_C_ABI void LLVMInitializeX86Target() {66 // Register the target.67 RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());68 RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());69 70 PassRegistry &PR = *PassRegistry::getPassRegistry();71 initializeX86LowerAMXIntrinsicsLegacyPassPass(PR);72 initializeX86LowerAMXTypeLegacyPassPass(PR);73 initializeX86PreTileConfigPass(PR);74 initializeGlobalISel(PR);75 initializeWinEHStatePassPass(PR);76 initializeFixupBWInstPassPass(PR);77 initializeCompressEVEXPassPass(PR);78 initializeFixupLEAPassPass(PR);79 initializeX86FPStackifierLegacyPass(PR);80 initializeX86FixupSetCCPassPass(PR);81 initializeX86CallFrameOptimizationPass(PR);82 initializeX86CmovConverterPassPass(PR);83 initializeX86TileConfigPass(PR);84 initializeX86FastPreTileConfigPass(PR);85 initializeX86FastTileConfigPass(PR);86 initializeKCFIPass(PR);87 initializeX86LowerTileCopyPass(PR);88 initializeX86ExpandPseudoPass(PR);89 initializeX86ExecutionDomainFixPass(PR);90 initializeX86DomainReassignmentPass(PR);91 initializeX86AvoidSFBPassPass(PR);92 initializeX86AvoidTrailingCallLegacyPassPass(PR);93 initializeX86SpeculativeLoadHardeningPassPass(PR);94 initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);95 initializeX86FlagsCopyLoweringPassPass(PR);96 initializeX86LoadValueInjectionLoadHardeningPassPass(PR);97 initializeX86LoadValueInjectionRetHardeningPassPass(PR);98 initializeX86OptimizeLEAPassPass(PR);99 initializeX86PartialReductionLegacyPass(PR);100 initializePseudoProbeInserterPass(PR);101 initializeX86ReturnThunksPass(PR);102 initializeX86DAGToDAGISelLegacyPass(PR);103 initializeX86ArgumentStackSlotPassPass(PR);104 initializeX86AsmPrinterPass(PR);105 initializeX86FixupInstTuningPassPass(PR);106 initializeX86FixupVectorConstantsPassPass(PR);107 initializeX86DynAllocaExpanderLegacyPass(PR);108 initializeX86SuppressAPXForRelocationPassPass(PR);109 initializeX86WinEHUnwindV2Pass(PR);110}111 112static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {113 if (TT.isOSBinFormatMachO()) {114 if (TT.isX86_64())115 return std::make_unique<X86_64MachoTargetObjectFile>();116 return std::make_unique<TargetLoweringObjectFileMachO>();117 }118 119 if (TT.isOSBinFormatCOFF())120 return std::make_unique<TargetLoweringObjectFileCOFF>();121 122 if (TT.isX86_64())123 return std::make_unique<X86_64ELFTargetObjectFile>();124 return std::make_unique<X86ELFTargetObjectFile>();125}126 127static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,128 std::optional<Reloc::Model> RM) {129 bool is64Bit = TT.isX86_64();130 if (!RM) {131 // JIT codegen should use static relocations by default, since it's132 // typically executed in process and not relocatable.133 if (JIT)134 return Reloc::Static;135 136 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.137 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we138 // use static relocation model by default.139 if (TT.isOSDarwin()) {140 if (is64Bit)141 return Reloc::PIC_;142 return Reloc::DynamicNoPIC;143 }144 if (TT.isOSWindows() && is64Bit)145 return Reloc::PIC_;146 return Reloc::Static;147 }148 149 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC150 // is defined as a model for code which may be used in static or dynamic151 // executables but not necessarily a shared library. On X86-32 we just152 // compile in -static mode, in x86-64 we use PIC.153 if (*RM == Reloc::DynamicNoPIC) {154 if (is64Bit)155 return Reloc::PIC_;156 if (!TT.isOSDarwin())157 return Reloc::Static;158 }159 160 // If we are on Darwin, disallow static relocation model in X86-64 mode, since161 // the Mach-O file format doesn't support it.162 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)163 return Reloc::PIC_;164 165 return *RM;166}167 168static CodeModel::Model169getEffectiveX86CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,170 bool JIT) {171 bool Is64Bit = TT.isX86_64();172 if (CM) {173 if (*CM == CodeModel::Tiny)174 reportFatalUsageError("target does not support the tiny CodeModel");175 return *CM;176 }177 if (JIT)178 return Is64Bit ? CodeModel::Large : CodeModel::Small;179 return CodeModel::Small;180}181 182/// Create an X86 target.183///184X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,185 StringRef CPU, StringRef FS,186 const TargetOptions &Options,187 std::optional<Reloc::Model> RM,188 std::optional<CodeModel::Model> CM,189 CodeGenOptLevel OL, bool JIT)190 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,191 getEffectiveRelocModel(TT, JIT, RM),192 getEffectiveX86CodeModel(TT, CM, JIT), OL),193 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {194 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within195 // the calling function. Note that this also includes __stack_chk_fail,196 // so there was some target-specific logic in the instruction selectors197 // to handle that. That code has since been generalized, so the only thing198 // needed is to set TrapUnreachable here.199 if (TT.isPS() || TT.isOSBinFormatMachO()) {200 this->Options.TrapUnreachable = true;201 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();202 }203 204 setMachineOutliner(true);205 206 // x86 supports the debug entry values.207 setSupportsDebugEntryValues(true);208 209 initAsmInfo();210}211 212X86TargetMachine::~X86TargetMachine() = default;213 214const X86Subtarget *215X86TargetMachine::getSubtargetImpl(const Function &F) const {216 Attribute CPUAttr = F.getFnAttribute("target-cpu");217 Attribute TuneAttr = F.getFnAttribute("tune-cpu");218 Attribute FSAttr = F.getFnAttribute("target-features");219 220 StringRef CPU =221 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;222 // "x86-64" is a default target setting for many front ends. In these cases,223 // they actually request for "generic" tuning unless the "tune-cpu" was224 // specified.225 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()226 : CPU == "x86-64" ? "generic"227 : (StringRef)CPU;228 StringRef FS =229 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;230 231 SmallString<512> Key;232 // The additions here are ordered so that the definitely short strings are233 // added first so we won't exceed the small size. We append the234 // much longer FS string at the end so that we only heap allocate at most235 // one time.236 237 // Extract prefer-vector-width attribute.238 unsigned PreferVectorWidthOverride = 0;239 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");240 if (PreferVecWidthAttr.isValid()) {241 StringRef Val = PreferVecWidthAttr.getValueAsString();242 unsigned Width;243 if (!Val.getAsInteger(0, Width)) {244 Key += 'p';245 Key += Val;246 PreferVectorWidthOverride = Width;247 }248 }249 250 // Extract min-legal-vector-width attribute.251 unsigned RequiredVectorWidth = UINT32_MAX;252 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");253 if (MinLegalVecWidthAttr.isValid()) {254 StringRef Val = MinLegalVecWidthAttr.getValueAsString();255 unsigned Width;256 if (!Val.getAsInteger(0, Width)) {257 Key += 'm';258 Key += Val;259 RequiredVectorWidth = Width;260 }261 }262 263 // Add CPU to the Key.264 Key += CPU;265 266 // Add tune CPU to the Key.267 Key += TuneCPU;268 269 // Keep track of the start of the feature portion of the string.270 unsigned FSStart = Key.size();271 272 // FIXME: This is related to the code below to reset the target options,273 // we need to know whether or not the soft float flag is set on the274 // function before we can generate a subtarget. We also need to use275 // it as a key for the subtarget since that can be the only difference276 // between two functions.277 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();278 // If the soft float attribute is set on the function turn on the soft float279 // subtarget feature.280 if (SoftFloat)281 Key += FS.empty() ? "+soft-float" : "+soft-float,";282 283 Key += FS;284 285 // We may have added +soft-float to the features so move the StringRef to286 // point to the full string in the Key.287 FS = Key.substr(FSStart);288 289 auto &I = SubtargetMap[Key];290 if (!I) {291 // This needs to be done before we create a new subtarget since any292 // creation will depend on the TM and the code generation flags on the293 // function that reside in TargetOptions.294 resetTargetOptions(F);295 I = std::make_unique<X86Subtarget>(296 TargetTriple, CPU, TuneCPU, FS, *this,297 MaybeAlign(F.getParent()->getOverrideStackAlignment()),298 PreferVectorWidthOverride, RequiredVectorWidth);299 }300 return I.get();301}302 303yaml::MachineFunctionInfo *X86TargetMachine::createDefaultFuncInfoYAML() const {304 return new yaml::X86MachineFunctionInfo();305}306 307yaml::MachineFunctionInfo *308X86TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {309 const auto *MFI = MF.getInfo<X86MachineFunctionInfo>();310 return new yaml::X86MachineFunctionInfo(*MFI);311}312 313bool X86TargetMachine::parseMachineFunctionInfo(314 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,315 SMDiagnostic &Error, SMRange &SourceRange) const {316 const auto &YamlMFI = static_cast<const yaml::X86MachineFunctionInfo &>(MFI);317 PFS.MF.getInfo<X86MachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);318 return false;319}320 321bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,322 unsigned DestAS) const {323 assert(SrcAS != DestAS && "Expected different address spaces!");324 if (getPointerSize(SrcAS) != getPointerSize(DestAS))325 return false;326 return SrcAS < 256 && DestAS < 256;327}328 329void X86TargetMachine::reset() { SubtargetMap.clear(); }330 331ScheduleDAGInstrs *332X86TargetMachine::createMachineScheduler(MachineSchedContext *C) const {333 ScheduleDAGMILive *DAG = createSchedLive(C);334 DAG->addMutation(createX86MacroFusionDAGMutation());335 return DAG;336}337 338ScheduleDAGInstrs *339X86TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {340 ScheduleDAGMI *DAG = createSchedPostRA(C);341 DAG->addMutation(createX86MacroFusionDAGMutation());342 return DAG;343}344 345//===----------------------------------------------------------------------===//346// X86 TTI query.347//===----------------------------------------------------------------------===//348 349TargetTransformInfo350X86TargetMachine::getTargetTransformInfo(const Function &F) const {351 return TargetTransformInfo(std::make_unique<X86TTIImpl>(this, F));352}353 354//===----------------------------------------------------------------------===//355// Pass Pipeline Configuration356//===----------------------------------------------------------------------===//357 358namespace {359 360/// X86 Code Generator Pass Configuration Options.361class X86PassConfig : public TargetPassConfig {362public:363 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)364 : TargetPassConfig(TM, PM) {}365 366 X86TargetMachine &getX86TargetMachine() const {367 return getTM<X86TargetMachine>();368 }369 370 void addIRPasses() override;371 bool addInstSelector() override;372 bool addIRTranslator() override;373 bool addLegalizeMachineIR() override;374 bool addRegBankSelect() override;375 bool addGlobalInstructionSelect() override;376 bool addILPOpts() override;377 bool addPreISel() override;378 void addMachineSSAOptimization() override;379 void addPreRegAlloc() override;380 bool addPostFastRegAllocRewrite() override;381 void addPostRegAlloc() override;382 void addPreEmitPass() override;383 void addPreEmitPass2() override;384 void addPreSched2() override;385 bool addRegAssignAndRewriteOptimized() override;386 387 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;388};389 390class X86ExecutionDomainFix : public ExecutionDomainFix {391public:392 static char ID;393 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}394 StringRef getPassName() const override {395 return "X86 Execution Dependency Fix";396 }397};398char X86ExecutionDomainFix::ID;399 400} // end anonymous namespace401 402INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",403 "X86 Execution Domain Fix", false, false)404INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)405INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",406 "X86 Execution Domain Fix", false, false)407 408TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {409 return new X86PassConfig(*this, PM);410}411 412MachineFunctionInfo *X86TargetMachine::createMachineFunctionInfo(413 BumpPtrAllocator &Allocator, const Function &F,414 const TargetSubtargetInfo *STI) const {415 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,416 STI);417}418 419void X86PassConfig::addIRPasses() {420 addPass(createAtomicExpandLegacyPass());421 422 // We add both pass anyway and when these two passes run, we skip the pass423 // based on the option level and option attribute.424 addPass(createX86LowerAMXIntrinsicsLegacyPass());425 addPass(createX86LowerAMXTypeLegacyPass());426 427 TargetPassConfig::addIRPasses();428 429 if (TM->getOptLevel() != CodeGenOptLevel::None) {430 addPass(createInterleavedAccessPass());431 addPass(createX86PartialReductionLegacyPass());432 }433 434 // Add passes that handle indirect branch removal and insertion of a retpoline435 // thunk. These will be a no-op unless a function subtarget has the retpoline436 // feature enabled.437 addPass(createIndirectBrExpandPass());438 439 // Add Control Flow Guard checks.440 const Triple &TT = TM->getTargetTriple();441 if (TT.isOSWindows()) {442 if (TT.isX86_64()) {443 addPass(createCFGuardDispatchPass());444 } else {445 addPass(createCFGuardCheckPass());446 }447 }448 449 if (TM->Options.JMCInstrument)450 addPass(createJMCInstrumenterPass());451}452 453bool X86PassConfig::addInstSelector() {454 // Install an instruction selector.455 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));456 457 // For ELF, cleanup any local-dynamic TLS accesses.458 if (TM->getTargetTriple().isOSBinFormatELF() &&459 getOptLevel() != CodeGenOptLevel::None)460 addPass(createCleanupLocalDynamicTLSPass());461 462 addPass(createX86GlobalBaseRegPass());463 addPass(createX86ArgumentStackSlotPass());464 return false;465}466 467bool X86PassConfig::addIRTranslator() {468 addPass(new IRTranslator(getOptLevel()));469 return false;470}471 472bool X86PassConfig::addLegalizeMachineIR() {473 addPass(new Legalizer());474 return false;475}476 477bool X86PassConfig::addRegBankSelect() {478 addPass(new RegBankSelect());479 return false;480}481 482bool X86PassConfig::addGlobalInstructionSelect() {483 addPass(new InstructionSelect(getOptLevel()));484 // Add GlobalBaseReg in case there is no SelectionDAG passes afterwards485 if (isGlobalISelAbortEnabled())486 addPass(createX86GlobalBaseRegPass());487 return false;488}489 490bool X86PassConfig::addILPOpts() {491 addPass(&EarlyIfConverterLegacyID);492 if (EnableMachineCombinerPass)493 addPass(&MachineCombinerID);494 addPass(createX86CmovConverterPass());495 return true;496}497 498bool X86PassConfig::addPreISel() {499 // Only add this pass for 32-bit x86 Windows.500 const Triple &TT = TM->getTargetTriple();501 if (TT.isOSWindows() && TT.isX86_32())502 addPass(createX86WinEHStatePass());503 return true;504}505 506void X86PassConfig::addPreRegAlloc() {507 if (getOptLevel() != CodeGenOptLevel::None) {508 addPass(&LiveRangeShrinkID);509 addPass(createX86FixupSetCC());510 addPass(createX86OptimizeLEAs());511 addPass(createX86CallFrameOptimization());512 addPass(createX86AvoidStoreForwardingBlocks());513 }514 515 addPass(createX86SuppressAPXForRelocationPass());516 517 addPass(createX86SpeculativeLoadHardeningPass());518 addPass(createX86FlagsCopyLoweringPass());519 addPass(createX86DynAllocaExpanderLegacyPass());520 521 if (getOptLevel() != CodeGenOptLevel::None)522 addPass(createX86PreTileConfigPass());523 else524 addPass(createX86FastPreTileConfigPass());525}526 527void X86PassConfig::addMachineSSAOptimization() {528 addPass(createX86DomainReassignmentPass());529 TargetPassConfig::addMachineSSAOptimization();530}531 532void X86PassConfig::addPostRegAlloc() {533 addPass(createX86LowerTileCopyPass());534 addPass(createX86FPStackifierLegacyPass());535 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back536 // to using the Speculative Execution Side Effect Suppression pass for537 // mitigation. This is to prevent slow downs due to538 // analyses needed by the LVIHardening pass when compiling at -O0.539 if (getOptLevel() != CodeGenOptLevel::None)540 addPass(createX86LoadValueInjectionLoadHardeningPass());541}542 543void X86PassConfig::addPreSched2() {544 addPass(createX86ExpandPseudoPass());545 addPass(createKCFIPass());546}547 548void X86PassConfig::addPreEmitPass() {549 if (getOptLevel() != CodeGenOptLevel::None) {550 addPass(new X86ExecutionDomainFix());551 addPass(createBreakFalseDeps());552 }553 554 addPass(createX86IndirectBranchTrackingPass());555 556 addPass(createX86IssueVZeroUpperPass());557 558 if (getOptLevel() != CodeGenOptLevel::None) {559 addPass(createX86FixupBWInsts());560 addPass(createX86PadShortFunctions());561 addPass(createX86FixupLEAs());562 addPass(createX86FixupInstTuning());563 addPass(createX86FixupVectorConstants());564 }565 addPass(createX86CompressEVEXPass());566 addPass(createX86InsertX87waitPass());567}568 569void X86PassConfig::addPreEmitPass2() {570 const Triple &TT = TM->getTargetTriple();571 const MCAsmInfo *MAI = TM->getMCAsmInfo();572 573 // The X86 Speculative Execution Pass must run after all control574 // flow graph modifying passes. As a result it was listed to run right before575 // the X86 Retpoline Thunks pass. The reason it must run after control flow576 // graph modifications is that the model of LFENCE in LLVM has to be updated577 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the578 // placement of this pass was hand checked to ensure that the subsequent579 // passes don't move the code around the LFENCEs in a way that will hurt the580 // correctness of this pass. This placement has been shown to work based on581 // hand inspection of the codegen output.582 addPass(createX86SpeculativeExecutionSideEffectSuppression());583 addPass(createX86IndirectThunksPass());584 addPass(createX86ReturnThunksPass());585 586 // Insert extra int3 instructions after trailing call instructions to avoid587 // issues in the unwinder.588 if (TT.isOSWindows() && TT.isX86_64())589 addPass(createX86AvoidTrailingCallLegacyPass());590 591 // Verify basic block incoming and outgoing cfa offset and register values and592 // correct CFA calculation rule where needed by inserting appropriate CFI593 // instructions.594 if (!TT.isOSDarwin() &&595 (!TT.isOSWindows() ||596 MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))597 addPass(createCFIInstrInserter());598 599 if (TT.isOSWindows()) {600 // Identify valid longjmp targets for Windows Control Flow Guard.601 addPass(createCFGuardLongjmpPass());602 // Identify valid eh continuation targets for Windows EHCont Guard.603 addPass(createEHContGuardTargetsPass());604 }605 addPass(createX86LoadValueInjectionRetHardeningPass());606 607 // Insert pseudo probe annotation for callsite profiling608 addPass(createPseudoProbeInserter());609 610 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,611 // also CALL_RVMARKER.612 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {613 // Only run bundle expansion if the module uses kcfi, or there are relevant614 // ObjC runtime functions present in the module.615 const Function &F = MF.getFunction();616 const Module *M = F.getParent();617 return M->getModuleFlag("kcfi") ||618 (TT.isOSDarwin() &&619 (M->getFunction("objc_retainAutoreleasedReturnValue") ||620 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));621 }));622 623 // Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run624 // after all real instructions have been added to the epilog.625 if (TT.isOSWindows() && TT.isX86_64())626 addPass(createX86WinEHUnwindV2Pass());627}628 629bool X86PassConfig::addPostFastRegAllocRewrite() {630 addPass(createX86FastTileConfigPass());631 return true;632}633 634std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {635 return getStandardCSEConfigForOpt(TM->getOptLevel());636}637 638static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI,639 const MachineRegisterInfo &MRI,640 const Register Reg) {641 const TargetRegisterClass *RC = MRI.getRegClass(Reg);642 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(RC);643}644 645bool X86PassConfig::addRegAssignAndRewriteOptimized() {646 // Don't support tile RA when RA is specified by command line "-regalloc".647 if (!isCustomizedRegAlloc() && EnableTileRAPass) {648 // Allocate tile register first.649 addPass(createGreedyRegisterAllocator(onlyAllocateTileRegisters));650 addPass(createX86TileConfigPass());651 }652 return TargetPassConfig::addRegAssignAndRewriteOptimized();653}654