663 lines · cpp
1//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file is part of the XCore Disassembler.11///12//===----------------------------------------------------------------------===//13 14#include "TargetInfo/XCoreTargetInfo.h"15#include "XCore.h"16#include "XCoreRegisterInfo.h"17#include "llvm/MC/MCContext.h"18#include "llvm/MC/MCDecoder.h"19#include "llvm/MC/MCDecoderOps.h"20#include "llvm/MC/MCDisassembler/MCDisassembler.h"21#include "llvm/MC/MCInst.h"22#include "llvm/MC/MCSubtargetInfo.h"23#include "llvm/MC/TargetRegistry.h"24#include "llvm/Support/Compiler.h"25 26using namespace llvm;27using namespace llvm::MCD;28 29#define DEBUG_TYPE "xcore-disassembler"30 31typedef MCDisassembler::DecodeStatus DecodeStatus;32 33namespace {34 35/// A disassembler class for XCore.36class XCoreDisassembler : public MCDisassembler {37public:38 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :39 MCDisassembler(STI, Ctx) {}40 41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,42 ArrayRef<uint8_t> Bytes, uint64_t Address,43 raw_ostream &CStream) const override;44};45}46 47static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,48 uint64_t &Size, uint16_t &Insn) {49 // We want to read exactly 2 Bytes of data.50 if (Bytes.size() < 2) {51 Size = 0;52 return false;53 }54 // Encoded as a little-endian 16-bit word in the stream.55 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);56 return true;57}58 59static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,60 uint64_t &Size, uint32_t &Insn) {61 // We want to read exactly 4 Bytes of data.62 if (Bytes.size() < 4) {63 Size = 0;64 return false;65 }66 // Encoded as a little-endian 32-bit word in the stream.67 Insn =68 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);69 return true;70}71 72static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {73 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();74 return RegInfo->getRegClass(RC).getRegister(RegNo);75}76 77static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,78 uint64_t Address,79 const MCDisassembler *Decoder) {80 if (RegNo > 11)81 return MCDisassembler::Fail;82 MCRegister Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);83 Inst.addOperand(MCOperand::createReg(Reg));84 return MCDisassembler::Success;85}86 87static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,88 uint64_t Address,89 const MCDisassembler *Decoder) {90 if (RegNo > 15)91 return MCDisassembler::Fail;92 MCRegister Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);93 Inst.addOperand(MCOperand::createReg(Reg));94 return MCDisassembler::Success;95}96 97static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,98 uint64_t Address,99 const MCDisassembler *Decoder) {100 if (Val > 11)101 return MCDisassembler::Fail;102 static const unsigned Values[] = {103 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32104 };105 Inst.addOperand(MCOperand::createImm(Values[Val]));106 return MCDisassembler::Success;107}108 109static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,110 uint64_t Address,111 const MCDisassembler *Decoder) {112 Inst.addOperand(MCOperand::createImm(-(int64_t)Val));113 return MCDisassembler::Success;114}115 116static DecodeStatus117Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {118 unsigned Combined = fieldFromInstruction(Insn, 6, 5);119 if (Combined < 27)120 return MCDisassembler::Fail;121 if (fieldFromInstruction(Insn, 5, 1)) {122 if (Combined == 31)123 return MCDisassembler::Fail;124 Combined += 5;125 }126 Combined -= 27;127 unsigned Op1High = Combined % 3;128 unsigned Op2High = Combined / 3;129 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);130 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);131 return MCDisassembler::Success;132}133 134static DecodeStatus135Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,136 unsigned &Op3) {137 unsigned Combined = fieldFromInstruction(Insn, 6, 5);138 if (Combined >= 27)139 return MCDisassembler::Fail;140 141 unsigned Op1High = Combined % 3;142 unsigned Op2High = (Combined / 3) % 3;143 unsigned Op3High = Combined / 9;144 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);145 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);146 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);147 return MCDisassembler::Success;148}149 150static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,151 uint64_t Address,152 const MCDisassembler *Decoder) {153 unsigned Op1, Op2, Op3;154 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);155 if (S == MCDisassembler::Success) {156 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);157 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);158 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);159 }160 return S;161}162 163static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,164 uint64_t Address,165 const MCDisassembler *Decoder) {166 unsigned Op1, Op2, Op3;167 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);168 if (S == MCDisassembler::Success) {169 Inst.addOperand(MCOperand::createImm(Op1));170 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);171 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);172 }173 return S;174}175 176static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,177 uint64_t Address,178 const MCDisassembler *Decoder) {179 unsigned Op1, Op2, Op3;180 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);181 if (S == MCDisassembler::Success) {182 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);183 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);184 Inst.addOperand(MCOperand::createImm(Op3));185 }186 return S;187}188 189static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,190 uint64_t Address,191 const MCDisassembler *Decoder) {192 unsigned Op1, Op2, Op3;193 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);194 if (S == MCDisassembler::Success) {195 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);196 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);197 DecodeBitpOperand(Inst, Op3, Address, Decoder);198 }199 return S;200}201 202static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,203 uint64_t Address,204 const MCDisassembler *Decoder) {205 unsigned Op1, Op2, Op3;206 DecodeStatus S =207 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);208 if (S == MCDisassembler::Success) {209 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);210 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);211 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);212 }213 return S;214}215 216static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,217 uint64_t Address,218 const MCDisassembler *Decoder) {219 unsigned Op1, Op2, Op3;220 DecodeStatus S =221 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);222 if (S == MCDisassembler::Success) {223 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);224 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);225 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);226 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);227 }228 return S;229}230 231static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,232 uint64_t Address,233 const MCDisassembler *Decoder) {234 unsigned Op1, Op2, Op3;235 DecodeStatus S =236 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);237 if (S == MCDisassembler::Success) {238 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);239 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);240 Inst.addOperand(MCOperand::createImm(Op3));241 }242 return S;243}244 245static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,246 uint64_t Address,247 const MCDisassembler *Decoder) {248 unsigned Op1, Op2, Op3;249 DecodeStatus S =250 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);251 if (S == MCDisassembler::Success) {252 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);253 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);254 DecodeBitpOperand(Inst, Op3, Address, Decoder);255 }256 return S;257}258 259 260static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn,261 uint64_t Address,262 const MCDisassembler *Decoder) {263 // Try and decode as a 3R instruction.264 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);265 switch (Opcode) {266 case 0x0:267 Inst.setOpcode(XCore::STW_2rus);268 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);269 case 0x1:270 Inst.setOpcode(XCore::LDW_2rus);271 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);272 case 0x2:273 Inst.setOpcode(XCore::ADD_3r);274 return Decode3RInstruction(Inst, Insn, Address, Decoder);275 case 0x3:276 Inst.setOpcode(XCore::SUB_3r);277 return Decode3RInstruction(Inst, Insn, Address, Decoder);278 case 0x4:279 Inst.setOpcode(XCore::SHL_3r);280 return Decode3RInstruction(Inst, Insn, Address, Decoder);281 case 0x5:282 Inst.setOpcode(XCore::SHR_3r);283 return Decode3RInstruction(Inst, Insn, Address, Decoder);284 case 0x6:285 Inst.setOpcode(XCore::EQ_3r);286 return Decode3RInstruction(Inst, Insn, Address, Decoder);287 case 0x7:288 Inst.setOpcode(XCore::AND_3r);289 return Decode3RInstruction(Inst, Insn, Address, Decoder);290 case 0x8:291 Inst.setOpcode(XCore::OR_3r);292 return Decode3RInstruction(Inst, Insn, Address, Decoder);293 case 0x9:294 Inst.setOpcode(XCore::LDW_3r);295 return Decode3RInstruction(Inst, Insn, Address, Decoder);296 case 0x10:297 Inst.setOpcode(XCore::LD16S_3r);298 return Decode3RInstruction(Inst, Insn, Address, Decoder);299 case 0x11:300 Inst.setOpcode(XCore::LD8U_3r);301 return Decode3RInstruction(Inst, Insn, Address, Decoder);302 case 0x12:303 Inst.setOpcode(XCore::ADD_2rus);304 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);305 case 0x13:306 Inst.setOpcode(XCore::SUB_2rus);307 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);308 case 0x14:309 Inst.setOpcode(XCore::SHL_2rus);310 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);311 case 0x15:312 Inst.setOpcode(XCore::SHR_2rus);313 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);314 case 0x16:315 Inst.setOpcode(XCore::EQ_2rus);316 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);317 case 0x17:318 Inst.setOpcode(XCore::TSETR_3r);319 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);320 case 0x18:321 Inst.setOpcode(XCore::LSS_3r);322 return Decode3RInstruction(Inst, Insn, Address, Decoder);323 case 0x19:324 Inst.setOpcode(XCore::LSU_3r);325 return Decode3RInstruction(Inst, Insn, Address, Decoder);326 }327 return MCDisassembler::Fail;328}329 330static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,331 uint64_t Address,332 const MCDisassembler *Decoder) {333 unsigned Op1, Op2;334 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);335 if (S != MCDisassembler::Success)336 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);337 338 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);339 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);340 return S;341}342 343static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,344 uint64_t Address,345 const MCDisassembler *Decoder) {346 unsigned Op1, Op2;347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);348 if (S != MCDisassembler::Success)349 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);350 351 Inst.addOperand(MCOperand::createImm(Op1));352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);353 return S;354}355 356static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,357 uint64_t Address,358 const MCDisassembler *Decoder) {359 unsigned Op1, Op2;360 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);361 if (S != MCDisassembler::Success)362 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);363 364 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);366 return S;367}368 369static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,370 uint64_t Address,371 const MCDisassembler *Decoder) {372 unsigned Op1, Op2;373 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);374 if (S != MCDisassembler::Success)375 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);376 377 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);378 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);380 return S;381}382 383static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,384 uint64_t Address,385 const MCDisassembler *Decoder) {386 unsigned Op1, Op2;387 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);388 if (S != MCDisassembler::Success)389 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);390 391 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);392 Inst.addOperand(MCOperand::createImm(Op2));393 return S;394}395 396static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,397 uint64_t Address,398 const MCDisassembler *Decoder) {399 unsigned Op1, Op2;400 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);401 if (S != MCDisassembler::Success)402 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);403 404 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);405 DecodeBitpOperand(Inst, Op2, Address, Decoder);406 return S;407}408 409static DecodeStatus410DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,411 const MCDisassembler *Decoder) {412 unsigned Op1, Op2;413 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);414 if (S != MCDisassembler::Success)415 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);416 417 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);418 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);419 DecodeBitpOperand(Inst, Op2, Address, Decoder);420 return S;421}422 423static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn,424 uint64_t Address,425 const MCDisassembler *Decoder) {426 // Try and decode as a L3R / L2RUS instruction.427 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |428 fieldFromInstruction(Insn, 27, 5) << 4;429 switch (Opcode) {430 case 0x0c:431 Inst.setOpcode(XCore::STW_l3r);432 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);433 case 0x1c:434 Inst.setOpcode(XCore::XOR_l3r);435 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);436 case 0x2c:437 Inst.setOpcode(XCore::ASHR_l3r);438 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);439 case 0x3c:440 Inst.setOpcode(XCore::LDAWF_l3r);441 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);442 case 0x4c:443 Inst.setOpcode(XCore::LDAWB_l3r);444 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);445 case 0x5c:446 Inst.setOpcode(XCore::LDA16F_l3r);447 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);448 case 0x6c:449 Inst.setOpcode(XCore::LDA16B_l3r);450 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);451 case 0x7c:452 Inst.setOpcode(XCore::MUL_l3r);453 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);454 case 0x8c:455 Inst.setOpcode(XCore::DIVS_l3r);456 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);457 case 0x9c:458 Inst.setOpcode(XCore::DIVU_l3r);459 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);460 case 0x10c:461 Inst.setOpcode(XCore::ST16_l3r);462 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);463 case 0x11c:464 Inst.setOpcode(XCore::ST8_l3r);465 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);466 case 0x12c:467 Inst.setOpcode(XCore::ASHR_l2rus);468 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);469 case 0x12d:470 Inst.setOpcode(XCore::OUTPW_l2rus);471 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);472 case 0x12e:473 Inst.setOpcode(XCore::INPW_l2rus);474 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);475 case 0x13c:476 Inst.setOpcode(XCore::LDAWF_l2rus);477 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);478 case 0x14c:479 Inst.setOpcode(XCore::LDAWB_l2rus);480 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);481 case 0x15c:482 Inst.setOpcode(XCore::CRC_l3r);483 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);484 case 0x18c:485 Inst.setOpcode(XCore::REMS_l3r);486 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);487 case 0x19c:488 Inst.setOpcode(XCore::REMU_l3r);489 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);490 }491 return MCDisassembler::Fail;492}493 494static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,495 uint64_t Address,496 const MCDisassembler *Decoder) {497 unsigned Op1, Op2;498 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),499 Op1, Op2);500 if (S != MCDisassembler::Success)501 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);502 503 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);504 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);505 return S;506}507 508static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,509 uint64_t Address,510 const MCDisassembler *Decoder) {511 unsigned Op1, Op2;512 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),513 Op1, Op2);514 if (S != MCDisassembler::Success)515 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);516 517 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);518 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);519 return S;520}521 522static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,523 uint64_t Address,524 const MCDisassembler *Decoder) {525 unsigned Op1, Op2, Op3, Op4, Op5, Op6;526 DecodeStatus S =527 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);528 if (S != MCDisassembler::Success)529 return S;530 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);531 if (S != MCDisassembler::Success)532 return S;533 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);534 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);535 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);536 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);537 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);538 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);539 return S;540}541 542static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn,543 uint64_t Address,544 const MCDisassembler *Decoder) {545 // Try and decode as a L6R instruction.546 Inst.clear();547 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);548 switch (Opcode) {549 case 0x00:550 Inst.setOpcode(XCore::LMUL_l6r);551 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);552 }553 return MCDisassembler::Fail;554}555 556static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,557 uint64_t Address,558 const MCDisassembler *Decoder) {559 unsigned Op1, Op2, Op3, Op4, Op5;560 DecodeStatus S =561 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);562 if (S != MCDisassembler::Success)563 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);564 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);565 if (S != MCDisassembler::Success)566 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);567 568 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);569 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);570 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);571 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);572 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);573 return S;574}575 576static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,577 uint64_t Address,578 const MCDisassembler *Decoder) {579 unsigned Op1, Op2, Op3;580 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);581 DecodeStatus S =582 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);583 if (S == MCDisassembler::Success) {584 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);585 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);586 }587 if (S == MCDisassembler::Success) {588 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);589 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);590 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);591 }592 return S;593}594 595static DecodeStatus596DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,597 const MCDisassembler *Decoder) {598 unsigned Op1, Op2, Op3;599 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);600 DecodeStatus S =601 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);602 if (S == MCDisassembler::Success) {603 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);604 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);605 }606 if (S == MCDisassembler::Success) {607 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);608 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);609 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);610 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);611 }612 return S;613}614 615#include "XCoreGenDisassemblerTables.inc"616 617MCDisassembler::DecodeStatus618XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,619 ArrayRef<uint8_t> Bytes, uint64_t Address,620 raw_ostream &cStream) const {621 uint16_t insn16;622 623 if (!readInstruction16(Bytes, Address, Size, insn16)) {624 return Fail;625 }626 627 // Calling the auto-generated decoder function.628 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,629 Address, this, STI);630 if (Result != Fail) {631 Size = 2;632 return Result;633 }634 635 uint32_t insn32;636 637 if (!readInstruction32(Bytes, Address, Size, insn32)) {638 return Fail;639 }640 641 // Calling the auto-generated decoder function.642 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);643 if (Result != Fail) {644 Size = 4;645 return Result;646 }647 648 return Fail;649}650 651static MCDisassembler *createXCoreDisassembler(const Target &T,652 const MCSubtargetInfo &STI,653 MCContext &Ctx) {654 return new XCoreDisassembler(STI, Ctx);655}656 657extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void658LLVMInitializeXCoreDisassembler() {659 // Register the disassembler.660 TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),661 createXCoreDisassembler);662}663