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1//===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This is the top level entry point for the XCore target.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Target-independent interfaces which we are implementing15//===----------------------------------------------------------------------===//16 17include "llvm/Target/Target.td"18 19//===----------------------------------------------------------------------===//20// Descriptions21//===----------------------------------------------------------------------===//22 23include "XCoreRegisterInfo.td"24include "XCoreInstrInfo.td"25include "XCoreCallingConv.td"26 27defm : RemapAllTargetPseudoPointerOperands<GRRegs>;28 29def XCoreInstrInfo : InstrInfo;30 31//===----------------------------------------------------------------------===//32// XCore processors supported.33//===----------------------------------------------------------------------===//34 35class Proc<string Name, list<SubtargetFeature> Features>36 : Processor<Name, NoItineraries, Features>;37 38def : Proc<"generic", []>;39def : Proc<"xs1b-generic", []>;40 41//===----------------------------------------------------------------------===//42// Declare the target which we are implementing43//===----------------------------------------------------------------------===//44 45def XCore : Target {46 // Pull in Instruction Info:47 let InstructionSet = XCoreInstrInfo;48}49