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1//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the XCore implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H14#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H15 16#include "XCoreRegisterInfo.h"17#include "llvm/CodeGen/TargetInstrInfo.h"18 19#define GET_INSTRINFO_HEADER20#include "XCoreGenInstrInfo.inc"21 22namespace llvm {23class XCoreSubtarget;24 25class XCoreInstrInfo : public XCoreGenInstrInfo {26 const XCoreRegisterInfo RI;27 virtual void anchor();28public:29 explicit XCoreInstrInfo(const XCoreSubtarget &ST);30 31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As32 /// such, whenever a client has an instance of instruction info, it should33 /// always be able to get register info as well (through this method).34 ///35 const TargetRegisterInfo &getRegisterInfo() const { return RI; }36 37 /// isLoadFromStackSlot - If the specified machine instruction is a direct38 /// load from a stack slot, return the virtual or physical register number of39 /// the destination along with the FrameIndex of the loaded stack slot. If40 /// not, return 0. This predicate must return 0 if the instruction has41 /// any side effects other than loading from the stack slot.42 Register isLoadFromStackSlot(const MachineInstr &MI,43 int &FrameIndex) const override;44 45 /// isStoreToStackSlot - If the specified machine instruction is a direct46 /// store to a stack slot, return the virtual or physical register number of47 /// the source reg along with the FrameIndex of the loaded stack slot. If48 /// not, return 0. This predicate must return 0 if the instruction has49 /// any side effects other than storing to the stack slot.50 Register isStoreToStackSlot(const MachineInstr &MI,51 int &FrameIndex) const override;52 53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,54 MachineBasicBlock *&FBB,55 SmallVectorImpl<MachineOperand> &Cond,56 bool AllowModify) const override;57 58 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,60 const DebugLoc &DL,61 int *BytesAdded = nullptr) const override;62 63 unsigned removeBranch(MachineBasicBlock &MBB,64 int *BytesRemoved = nullptr) const override;65 66 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,67 const DebugLoc &DL, Register DestReg, Register SrcReg,68 bool KillSrc, bool RenamableDest = false,69 bool RenamableSrc = false) const override;70 71 void storeRegToStackSlot(72 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,73 bool isKill, int FrameIndex, const TargetRegisterClass *RC,74 75 Register VReg,76 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;77 78 void loadRegFromStackSlot(79 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,80 int FrameIndex, const TargetRegisterClass *RC,81 82 Register VReg,83 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;84 85 bool reverseBranchCondition(86 SmallVectorImpl<MachineOperand> &Cond) const override;87 88 // Emit code before MBBI to load immediate value into physical register Reg.89 // Returns an iterator to the new instruction.90 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,91 MachineBasicBlock::iterator MI,92 unsigned Reg, uint64_t Value) const;93};94 95}96 97#endif98