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1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the XCore instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13// Uses of CP, DP are not currently reflected in the patterns, since14// having a physical register as an operand prevents loop hoisting and15// since the value of these registers never changes during the life of the16// function.17 18//===----------------------------------------------------------------------===//19// Instruction format superclass.20//===----------------------------------------------------------------------===//21 22include "XCoreInstrFormats.td"23 24//===----------------------------------------------------------------------===//25// XCore specific DAG Nodes.26//27 28// Call29def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;30def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,31 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,32 SDNPVariadic]>;33 34def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,35 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;36 37def SDT_XCoreEhRet : SDTypeProfile<0, 2,38 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;39def XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet,40 [SDNPHasChain, SDNPOptInGlue]>;41 42def SDT_XCoreBR_JT : SDTypeProfile<0, 2,43 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;44 45def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,46 [SDNPHasChain]>;47 48def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,49 [SDNPHasChain]>;50 51def SDT_XCoreAddress : SDTypeProfile<1, 1,52 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;53 54def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,55 []>;56 57def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,58 []>;59 60def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,61 []>;62 63def frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf,64 []>;65 66def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;67def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,68 [SDNPHasChain, SDNPMayStore]>;69 70def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>;71def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp,72 [SDNPHasChain, SDNPMayLoad]>;73 74def SDT_XCoreLAddSub : SDTypeProfile<2, 3, [75 SDTCisVT<0, i32>, // result76 SDTCisVT<1, i32>, // carry out77 SDTCisVT<2, i32>, // lhs78 SDTCisVT<3, i32>, // rhs79 SDTCisVT<4, i32> // carry in80]>;81 82def XCoreLAdd : SDNode<"XCoreISD::LADD", SDT_XCoreLAddSub>;83def XCoreLSub : SDNode<"XCoreISD::LSUB", SDT_XCoreLAddSub>;84 85// Used for both long multiplication and multiply-accumulate.86def SDT_XCoreMul : SDTypeProfile<2, 4, [87 SDTCisVT<0, i32>, // result (high part)88 SDTCisVT<1, i32>, // result (low part)89 SDTCisVT<2, i32>, // lhs90 SDTCisVT<3, i32>, // rhs91 SDTCisVT<4, i32>, // addend 192 SDTCisVT<5, i32>, // addend 293]>;94 95def XCoreLMul : SDNode<"XCoreISD::LMUL", SDT_XCoreMul>;96def XCoreMAccU : SDNode<"XCoreISD::MACCU", SDT_XCoreMul>;97def XCoreMAccS : SDNode<"XCoreISD::MACCS", SDT_XCoreMul>;98 99def XCoreCRC8 : SDNode<"XCoreISD::CRC8",100 SDTypeProfile<2, 3, [101 SDTCisVT<0, i32>, // shifted data102 SDTCisVT<1, i32>, // result crc103 SDTCisVT<2, i32>, // initial crc104 SDTCisVT<3, i32>, // data105 SDTCisVT<4, i32>, // polynomial106 ]>107>;108 109// These are target-independent nodes, but have target-specific formats.110def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,111 SDTCisVT<1, i32> ]>;112def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,113 SDTCisVT<1, i32> ]>;114 115def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,116 [SDNPHasChain, SDNPOutGlue]>;117def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;119 120//===----------------------------------------------------------------------===//121// Instruction Pattern Stuff122//===----------------------------------------------------------------------===//123 124def div4_xform : SDNodeXForm<imm, [{125 // Transformation function: imm/4126 assert(N->getZExtValue() % 4 == 0);127 return getI32Imm(N->getZExtValue()/4, SDLoc(N));128}]>;129 130def msksize_xform : SDNodeXForm<imm, [{131 // Transformation function: get the size of a mask132 assert(isMask_32(N->getZExtValue()));133 // look for the first non-zero bit134 return getI32Imm(llvm::bit_width((uint32_t)N->getZExtValue()),135 SDLoc(N));136}]>;137 138def neg_xform : SDNodeXForm<imm, [{139 // Transformation function: -imm140 uint32_t value = N->getZExtValue();141 return getI32Imm(-value, SDLoc(N));142}]>;143 144def bpwsub_xform : SDNodeXForm<imm, [{145 // Transformation function: 32-imm146 uint32_t value = N->getZExtValue();147 return getI32Imm(32 - value, SDLoc(N));148}]>;149 150def div4neg_xform : SDNodeXForm<imm, [{151 // Transformation function: -imm/4152 uint32_t value = N->getZExtValue();153 assert(-value % 4 == 0);154 return getI32Imm(-value/4, SDLoc(N));155}]>;156 157def immUs4Neg : PatLeaf<(imm), [{158 uint32_t value = (uint32_t)N->getZExtValue();159 return (-value)%4 == 0 && (-value)/4 <= 11;160}]>;161 162def immUs4 : PatLeaf<(imm), [{163 uint32_t value = (uint32_t)N->getZExtValue();164 return value%4 == 0 && value/4 <= 11;165}]>;166 167def immUsNeg : PatLeaf<(imm), [{168 return -((uint32_t)N->getZExtValue()) <= 11;169}]>;170 171def immUs : PatLeaf<(imm), [{172 return (uint32_t)N->getZExtValue() <= 11;173}]>;174 175def immU6 : PatLeaf<(imm), [{176 return (uint32_t)N->getZExtValue() < (1 << 6);177}]>;178 179def immU16 : PatLeaf<(imm), [{180 return (uint32_t)N->getZExtValue() < (1 << 16);181}]>;182 183def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;184 185def immBitp : PatLeaf<(imm), [{186 uint32_t value = (uint32_t)N->getZExtValue();187 return (value >= 1 && value <= 8)188 || value == 16189 || value == 24190 || value == 32;191}]>;192 193def immBpwSubBitp : PatLeaf<(imm), [{194 uint32_t value = (uint32_t)N->getZExtValue();195 return (value >= 24 && value <= 31)196 || value == 16197 || value == 8198 || value == 0;199}]>;200 201def lda16f : PatFrag<(ops node:$addr, node:$offset),202 (add node:$addr, (shl node:$offset, 1))>;203def lda16b : PatFrag<(ops node:$addr, node:$offset),204 (sub node:$addr, (shl node:$offset, 1))>;205def ldawf : PatFrag<(ops node:$addr, node:$offset),206 (add node:$addr, (shl node:$offset, 2))>;207def ldawb : PatFrag<(ops node:$addr, node:$offset),208 (sub node:$addr, (shl node:$offset, 2))>;209 210// Instruction operand types211def pcrel_imm : Operand<i32>;212def pcrel_imm_neg : Operand<i32> {213 let DecoderMethod = "DecodeNegImmOperand";214}215def brtarget : Operand<OtherVT>;216def brtarget_neg : Operand<OtherVT> {217 let DecoderMethod = "DecodeNegImmOperand";218}219 220// Addressing modes221def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;222 223// Address operands224def MEMii : Operand<i32> {225 let MIOperandInfo = (ops i32imm, i32imm);226}227 228// Jump tables.229def InlineJT : Operand<i32> {230 let PrintMethod = "printInlineJT";231}232 233def InlineJT32 : Operand<i32> {234 let PrintMethod = "printInlineJT32";235}236 237//===----------------------------------------------------------------------===//238// Instruction Class Templates239//===----------------------------------------------------------------------===//240 241// Three operand short242 243multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {244 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),245 !strconcat(OpcStr, " $dst, $b, $c"),246 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;247 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),248 !strconcat(OpcStr, " $dst, $b, $c"),249 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;250}251 252multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {253 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),254 !strconcat(OpcStr, " $dst, $b, $c"), []>;255 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),256 !strconcat(OpcStr, " $dst, $b, $c"), []>;257}258 259multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,260 SDNode OpNode> {261 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),262 !strconcat(OpcStr, " $dst, $b, $c"),263 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;264 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),265 !strconcat(OpcStr, " $dst, $b, $c"),266 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;267}268 269class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :270 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),271 !strconcat(OpcStr, " $dst, $b, $c"),272 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;273 274class F3R_np<bits<5> opc, string OpcStr> :275 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),276 !strconcat(OpcStr, " $dst, $b, $c"), []>;277// Three operand long278 279/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.280multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,281 SDNode OpNode> {282 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),283 !strconcat(OpcStr, " $dst, $b, $c"),284 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;285 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),286 !strconcat(OpcStr, " $dst, $b, $c"),287 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;288}289 290/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.291multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,292 SDNode OpNode> {293 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),294 !strconcat(OpcStr, " $dst, $b, $c"),295 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;296 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),297 !strconcat(OpcStr, " $dst, $b, $c"),298 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;299}300 301class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :302 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),303 !strconcat(OpcStr, " $dst, $b, $c"),304 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;305 306// Register - U6307// Operand register - U6308multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {309 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),310 !strconcat(OpcStr, " $a, $b"), []>;311 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),312 !strconcat(OpcStr, " $a, $b"), []>;313}314 315multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {316 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),317 !strconcat(OpcStr, " $a, $b"), []>;318 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),319 !strconcat(OpcStr, " $a, $b"), []>;320}321 322 323// U6324multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {325 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),326 [(OpNode immU6:$a)]>;327 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),328 [(OpNode immU16:$a)]>;329}330 331multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {332 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),333 [(Int immU6:$a)]>;334 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),335 [(Int immU16:$a)]>;336}337 338multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {339 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;340 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;341}342 343// Two operand short344 345class F2R_np<bits<6> opc, string OpcStr> :346 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),347 !strconcat(OpcStr, " $dst, $b"), []>;348 349// Two operand long350 351//===----------------------------------------------------------------------===//352// Pseudo Instructions353//===----------------------------------------------------------------------===//354 355let Defs = [SP], Uses = [SP] in {356def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),357 "# ADJCALLSTACKDOWN $amt, $amt2",358 [(callseq_start timm:$amt, timm:$amt2)]>;359def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),360 "# ADJCALLSTACKUP $amt1",361 [(callseq_end timm:$amt1, timm:$amt2)]>;362}363 364let isReMaterializable = 1 in365def FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins),366 "# FRAME_TO_ARGS_OFFSET $dst",367 [(set GRRegs:$dst, (frametoargsoffset))]>;368 369let isReturn = 1, isTerminator = 1, isBarrier = 1 in370def EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler),371 "# EH_RETURN $s, $handler",372 [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>;373 374def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),375 "# LDWFI $dst, $addr",376 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;377 378def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),379 "# LDAWFI $dst, $addr",380 [(set GRRegs:$dst, ADDRspii:$addr)]>;381 382def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),383 "# STWFI $src, $addr",384 [(store GRRegs:$src, ADDRspii:$addr)]>;385 386// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after387// instruction selection into a branch sequence.388let usesCustomInserter = 1 in {389 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),390 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),391 "# SELECT_CC PSEUDO!",392 [(set GRRegs:$dst,393 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;394}395 396//===----------------------------------------------------------------------===//397// Instructions398//===----------------------------------------------------------------------===//399 400// Three operand short401defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;402defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;403let hasSideEffects = 0 in {404defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;405def LSS_3r : F3R_np<0b11000, "lss">;406def LSU_3r : F3R_np<0b11001, "lsu">;407}408def AND_3r : F3R<0b00111, "and", and>;409def OR_3r : F3R<0b01000, "or", or>;410 411let mayLoad=1 in {412def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),413 (ins GRRegs:$addr, GRRegs:$offset),414 "ldw $dst, $addr[$offset]", []>;415 416def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),417 (ins GRRegs:$addr, i32imm:$offset),418 "ldw $dst, $addr[$offset]", []>;419 420def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),421 (ins GRRegs:$addr, GRRegs:$offset),422 "ld16s $dst, $addr[$offset]", []>;423 424def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),425 (ins GRRegs:$addr, GRRegs:$offset),426 "ld8u $dst, $addr[$offset]", []>;427}428 429let mayStore=1 in {430def STW_l3r : _FL3R<0b000001100, (outs),431 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),432 "stw $val, $addr[$offset]", []>;433 434def STW_2rus : _F2RUS<0b00000, (outs),435 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),436 "stw $val, $addr[$offset]", []>;437}438 439defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;440defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;441 442// The first operand is treated as an immediate since it refers to a register443// number in another thread.444def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),445 "set t[$c]:r$a, $b", []>;446 447// Three operand long448def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),449 (ins GRRegs:$addr, GRRegs:$offset),450 "ldaw $dst, $addr[$offset]",451 [(set GRRegs:$dst,452 (ldawf GRRegs:$addr, GRRegs:$offset))]>;453 454let hasSideEffects = 0 in455def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),456 (ins GRRegs:$addr, i32imm:$offset),457 "ldaw $dst, $addr[$offset]", []>;458 459def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),460 (ins GRRegs:$addr, GRRegs:$offset),461 "ldaw $dst, $addr[-$offset]",462 [(set GRRegs:$dst,463 (ldawb GRRegs:$addr, GRRegs:$offset))]>;464 465let hasSideEffects = 0 in466def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),467 (ins GRRegs:$addr, i32imm:$offset),468 "ldaw $dst, $addr[-$offset]", []>;469 470def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),471 (ins GRRegs:$addr, GRRegs:$offset),472 "lda16 $dst, $addr[$offset]",473 [(set GRRegs:$dst,474 (lda16f GRRegs:$addr, GRRegs:$offset))]>;475 476def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),477 (ins GRRegs:$addr, GRRegs:$offset),478 "lda16 $dst, $addr[-$offset]",479 [(set GRRegs:$dst,480 (lda16b GRRegs:$addr, GRRegs:$offset))]>;481 482def MUL_l3r : FL3R<0b001111100, "mul", mul>;483// Instructions which may trap are marked as side effecting.484let hasSideEffects = 1 in {485def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;486def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;487def REMS_l3r : FL3R<0b110001100, "rems", srem>;488def REMU_l3r : FL3R<0b110011100, "remu", urem>;489}490def XOR_l3r : FL3R<0b000011100, "xor", xor>;491defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;492 493let Constraints = "$src1 = $dst" in494def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),496 "crc32 $dst, $src2, $src3",497 [(set GRRegs:$dst,498 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,499 GRRegs:$src3))]>;500 501let mayStore=1 in {502def ST16_l3r : _FL3R<0b100001100, (outs),503 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),504 "st16 $val, $addr[$offset]", []>;505 506def ST8_l3r : _FL3R<0b100011100, (outs),507 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),508 "st8 $val, $addr[$offset]", []>;509}510 511def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),512 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",513 []>;514 515def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),516 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),517 "outpw res[$b], $a, $c", []>;518 519// Four operand long520let Constraints = "$e = $a,$f = $b" in {521def MACCU_l4r : _FL4RSrcDstSrcDst<522 0b000001, (outs GRRegs:$a, GRRegs:$b),523 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d",524 [(set i32:$a, i32:$b, (XCoreMAccU i32:$e, i32:$f, i32:$c, i32:$d))]>;525 526def MACCS_l4r : _FL4RSrcDstSrcDst<527 0b000010, (outs GRRegs:$a, GRRegs:$b),528 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d",529 [(set i32:$a, i32:$b, (XCoreMAccS i32:$e, i32:$f, i32:$c, i32:$d))]>;530}531 532let Constraints = "$e = $b" in533def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),534 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),535 "crc8 $b, $a, $c, $d",536 [(set i32:$a, i32:$b,537 (XCoreCRC8 i32:$e, i32:$c, i32:$d))]>;538 539// Five operand long540 541def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),542 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),543 "ladd $dst2, $dst1, $src1, $src2, $src3",544 [(set i32:$dst1, i32:$dst2,545 (XCoreLAdd i32:$src1, i32:$src2, i32:$src3))]>;546 547def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),548 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),549 "lsub $dst2, $dst1, $src1, $src2, $src3",550 [(set i32:$dst1, i32:$dst2,551 (XCoreLSub i32:$src1, i32:$src2, i32:$src3))]>;552 553def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),554 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),555 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;556 557// Six operand long558 559def LMUL_l6r : _FL6R<560 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),561 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),562 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",563 [(set i32:$dst1, i32:$dst2,564 (XCoreLMul i32:$src1, i32:$src2, i32:$src3, i32:$src4))]>;565 566// Register - U6567 568//let Uses = [DP] in ...569let hasSideEffects = 0, isReMaterializable = 1 in570def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),571 "ldaw $a, dp[$b]", []>;572 573let isReMaterializable = 1 in574def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b),575 "ldaw $a, dp[$b]",576 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;577 578let mayLoad=1 in579def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),580 "ldw $a, dp[$b]", []>;581 582def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b),583 "ldw $a, dp[$b]",584 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>;585 586let mayStore=1 in587def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),588 "stw $a, dp[$b]", []>;589 590def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b),591 "stw $a, dp[$b]",592 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>;593 594//let Uses = [CP] in ..595let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in {596def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),597 "ldw $a, cp[$b]", []>;598def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b),599 "ldw $a, cp[$b]",600 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>;601}602 603let Uses = [SP] in {604let mayStore=1 in {605def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),606 "stw $a, sp[$b]",607 [(XCoreStwsp RRegs:$a, immU6:$b)]>;608 609def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),610 "stw $a, sp[$b]",611 [(XCoreStwsp RRegs:$a, immU16:$b)]>;612}613 614let mayLoad=1 in {615def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),616 "ldw $a, sp[$b]",617 [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>;618 619def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),620 "ldw $a, sp[$b]",621 [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>;622}623 624let hasSideEffects = 0 in {625def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),626 "ldaw $a, sp[$b]", []>;627 628def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),629 "ldaw $a, sp[$b]", []>;630}631}632 633let isReMaterializable = 1 in {634def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),635 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;636 637def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),638 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;639}640 641def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),642 "setc res[$a], $b",643 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;644 645def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),646 "setc res[$a], $b",647 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;648 649// Operand register - U6650let isBranch = 1, isTerminator = 1 in {651defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;652defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;653defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;654defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;655}656 657// U6658let Defs = [SP], Uses = [SP] in {659let hasSideEffects = 0 in660defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;661 662let mayStore = 1 in663defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;664 665let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {666defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;667}668}669 670let hasSideEffects = 0 in671defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;672 673let Uses = [R11], isCall=1 in674defm BLAT : FU6_LU6_np<0b0111001101, "blat">;675 676let isBranch = 1, isTerminator = 1, isBarrier = 1 in {677def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;678 679def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;680 681def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;682 683def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;684}685 686//let Uses = [CP] in ...687let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in688def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",689 []>;690 691let Defs = [R11], isReMaterializable = 1 in692def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]",693 [(set R11, (cprelwrapper tglobaladdr:$a))]>;694 695let Defs = [R11] in696defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;697 698defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;699 700defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;701 702// setsr may cause a branch if it is used to enable events. clrsr may703// branch if it is executed while events are enabled.704let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,705 isCodeGenOnly = 1 in {706defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;707defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;708}709 710defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;711 712let Uses = [SP], Defs = [SP], mayStore = 1 in713defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;714 715let Uses = [SP], Defs = [SP], mayLoad = 1 in716defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;717 718// U10719 720let Defs = [R11], isReMaterializable = 1 in {721let hasSideEffects = 0 in722def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>;723 724def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",725 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;726 727let hasSideEffects = 0 in728def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a",729 []>;730 731let hasSideEffects = 0 in732def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a),733 "ldap r11, $a",734 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;735 736let isCodeGenOnly = 1 in737def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a",738 [(set R11, (pcrelwrapper tblockaddress:$a))]>;739}740 741let isCall=1,742// All calls clobber the link register and the non-callee-saved registers:743Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {744def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;745 746def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;747 748def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",749 []>;750 751def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a",752 [(XCoreBranchLink tglobaladdr:$a)]>;753 754def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;755 756def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>;757}758 759let Defs = [R11], mayLoad = 1, isReMaterializable = 1,760 hasSideEffects = 0 in {761def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;762 763def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",764 []>;765}766 767// Two operand short768def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),769 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;770 771def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),772 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;773 774let Constraints = "$src1 = $dst" in {775def SEXT_rus :776 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),777 "sext $dst, $src2",778 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,779 immBitp:$src2))]>;780 781def SEXT_2r :782 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),783 "sext $dst, $src2",784 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;785 786def ZEXT_rus :787 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),788 "zext $dst, $src2",789 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,790 immBitp:$src2))]>;791 792def ZEXT_2r :793 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),794 "zext $dst, $src2",795 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;796 797def ANDNOT_2r :798 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),799 "andnot $dst, $src2",800 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;801}802 803let isReMaterializable = 1, hasSideEffects = 0 in804def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),805 "mkmsk $dst, $size", []>;806 807def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),808 "mkmsk $dst, $size",809 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;810 811def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),812 "getr $dst, $type",813 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;814 815def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),816 "getts $dst, res[$r]",817 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;818 819def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),820 "setpt res[$r], $val",821 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;822 823def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),824 "outct res[$r], $val",825 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;826 827def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),828 "outct res[$r], $val",829 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;830 831def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),832 "outt res[$r], $val",833 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;834 835def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),836 "out res[$r], $val",837 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;838 839let Constraints = "$src = $dst" in840def OUTSHR_2r :841 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),842 "outshr res[$r], $src",843 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;844 845def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),846 "inct $dst, res[$r]",847 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;848 849def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),850 "int $dst, res[$r]",851 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;852 853def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),854 "in $dst, res[$r]",855 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;856 857let Constraints = "$src = $dst" in858def INSHR_2r :859 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),860 "inshr $dst, res[$r]",861 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;862 863def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),864 "chkct res[$r], $val",865 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;866 867def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),868 "chkct res[$r], $val",869 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;870 871def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),872 "testct $dst, res[$src]",873 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;874 875def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),876 "testwct $dst, res[$src]",877 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;878 879def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),880 "setd res[$r], $val",881 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;882 883def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),884 "setpsc res[$src1], $src2",885 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;886 887def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),888 "getst $dst, res[$r]",889 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;890 891def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),892 "init t[$t]:sp, $src",893 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;894 895def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),896 "init t[$t]:pc, $src",897 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;898 899def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),900 "init t[$t]:cp, $src",901 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;902 903def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),904 "init t[$t]:dp, $src",905 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;906 907def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),908 "peek $dst, res[$src]",909 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;910 911def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),912 "endin $dst, res[$src]",913 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;914 915def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),916 "eef $a, res[$b]", []>;917 918def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),919 "eet $a, res[$b]", []>;920 921def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),922 "tsetmr r$a, $b", []>;923 924// Two operand long925def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),926 "bitrev $dst, $src",927 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;928 929def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),930 "byterev $dst, $src",931 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;932 933def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src),934 "clz $dst, $src",935 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;936 937def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),938 "getd $dst, res[$src]", []>;939 940def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),941 "getn $dst, res[$src]", []>;942 943def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),944 "setc res[$r], $val",945 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;946 947def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),948 "settw res[$r], $val",949 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;950 951def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),952 "get $dst, ps[$src]",953 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;954 955def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),956 "set ps[$src1], $src2",957 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;958 959def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),960 "init t[$t]:lr, $src",961 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;962 963def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),964 "setclk res[$src1], $src2",965 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;966 967def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),968 "setn res[$src1], $src2", []>;969 970def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),971 "setrdy res[$src1], $src2",972 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;973 974def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),975 "testlcl $dst, res[$src]", []>;976 977// One operand short978def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),979 "msync res[$a]",980 [(int_xcore_msync GRRegs:$a)]>;981def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),982 "mjoin res[$a]",983 [(int_xcore_mjoin GRRegs:$a)]>;984 985let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in986def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),987 "bau $a",988 [(brind GRRegs:$a)]>;989 990let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in991def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),992 "bru $i\n$t",993 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;994 995let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in996def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),997 "bru $i\n$t",998 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;999 1000let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in1001def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>;1002 1003let Defs=[SP], hasSideEffects=0 in1004def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;1005 1006let hasSideEffects=0 in1007def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;1008 1009let hasSideEffects=0 in1010def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;1011 1012let hasCtrlDep = 1 in1013def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),1014 "ecallt $a",1015 []>;1016 1017let hasCtrlDep = 1 in1018def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),1019 "ecallf $a",1020 []>;1021 1022let isCall=1,1023// All calls clobber the link register and the non-callee-saved registers:1024Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {1025def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),1026 "bla $a",1027 [(XCoreBranchLink GRRegs:$a)]>;1028}1029 1030def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),1031 "syncr res[$a]",1032 [(int_xcore_syncr GRRegs:$a)]>;1033 1034def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),1035 "freer res[$a]",1036 [(int_xcore_freer GRRegs:$a)]>;1037 1038let Uses=[R11] in {1039def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),1040 "setv res[$a], r11",1041 [(int_xcore_setv GRRegs:$a, R11)]>;1042 1043def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),1044 "setev res[$a], r11",1045 [(int_xcore_setev GRRegs:$a, R11)]>;1046}1047 1048def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;1049 1050def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]",1051 [(int_xcore_edu GRRegs:$a)]>;1052 1053def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),1054 "eeu res[$a]",1055 [(int_xcore_eeu GRRegs:$a)]>;1056 1057def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;1058 1059def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;1060 1061def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;1062 1063def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;1064 1065def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]",1066 [(int_xcore_clrpt GRRegs:$a)]>;1067 1068// Zero operand short1069 1070def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;1071 1072def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;1073 1074let Defs = [SP], Uses = [SP] in1075def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;1076 1077let Defs = [SP] in1078def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;1079 1080def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;1081 1082def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;1083 1084let Defs = [R11] in {1085def GETID_0R : _F0R<0b0001001110, (outs), (ins),1086 "get r11, id",1087 [(set R11, (int_xcore_getid))]>;1088 1089def GETED_0R : _F0R<0b0000111110, (outs), (ins),1090 "get r11, ed",1091 [(set R11, (int_xcore_geted))]>;1092 1093def GETET_0R : _F0R<0b0000111111, (outs), (ins),1094 "get r11, et",1095 [(set R11, (int_xcore_getet))]>;1096 1097def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),1098 "get r11, kep", []>;1099 1100def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),1101 "get r11, ksp", []>;1102}1103 1104let Defs = [SP] in1105def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;1106 1107let Uses = [SP], mayLoad = 1 in {1108def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;1109 1110def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;1111 1112def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;1113 1114def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;1115}1116 1117let Uses=[R11] in1118def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;1119 1120def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),1121 "ssync",1122 [(int_xcore_ssync)]>;1123 1124let Uses = [SP], mayStore = 1 in {1125def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;1126 1127def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;1128 1129def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;1130 1131def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;1132}1133 1134let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,1135 hasSideEffects = 1 in1136def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),1137 "waiteu",1138 [(brind (int_xcore_waitevent))]>;1139 1140//===----------------------------------------------------------------------===//1141// Non-Instruction Patterns1142//===----------------------------------------------------------------------===//1143 1144def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;1145 1146/// sext_inreg1147def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;1148def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;1149def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;1150 1151/// loads1152def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),1153 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;1154def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;1155 1156def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),1157 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;1158def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;1159 1160def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),1161 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;1162def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),1163 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;1164def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;1165 1166/// anyext1167def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),1168 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;1169def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;1170def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),1171 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;1172def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;1173 1174/// stores1175def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),1176 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;1177def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),1178 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;1179 1180def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),1181 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;1182def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),1183 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;1184 1185def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),1186 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;1187def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),1188 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;1189def : Pat<(store GRRegs:$val, GRRegs:$addr),1190 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;1191 1192/// bitrev1193def : Pat<(bitreverse GRRegs:$src), (BITREV_l2r GRRegs:$src)>;1194 1195/// cttz1196def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;1197 1198/// trap1199def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;1200 1201///1202/// branch patterns1203///1204 1205// unconditional branch1206def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;1207 1208// direct match equal/notequal zero brcond1209def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),1210 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;1211def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),1212 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;1213 1214def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),1215 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;1216def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),1217 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;1218def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),1219 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;1220def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),1221 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;1222def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),1223 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;1224def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),1225 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;1226 1227// generic brcond pattern1228def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;1229 1230 1231///1232/// Select patterns1233///1234 1235// direct match equal/notequal zero select1236def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),1237 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;1238 1239def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),1240 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;1241 1242def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),1243 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;1244def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),1245 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;1246def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),1247 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;1248def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),1249 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;1250def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),1251 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;1252def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),1253 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;1254 1255///1256/// setcc patterns, only matched when none of the above brcond1257/// patterns match1258///1259 1260// setcc 2 register operands1261def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),1262 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;1263def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),1264 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;1265 1266def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),1267 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;1268def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),1269 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;1270 1271def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),1272 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;1273def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),1274 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;1275 1276def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),1277 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;1278def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),1279 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;1280 1281def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),1282 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;1283 1284def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),1285 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;1286 1287// setcc reg/imm operands1288def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),1289 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;1290def : Pat<(setne GRRegs:$lhs, immUs:$rhs),1291 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;1292 1293// misc1294def : Pat<(add GRRegs:$addr, immUs4:$offset),1295 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;1296 1297def : Pat<(sub GRRegs:$addr, immUs4:$offset),1298 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;1299 1300def : Pat<(and GRRegs:$val, immMskBitp:$mask),1301 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;1302 1303// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.1304def : Pat<(add GRRegs:$src1, immUsNeg:$src2),1305 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;1306 1307def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),1308 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;1309 1310///1311/// Some peepholes1312///1313 1314def : Pat<(mul GRRegs:$src, 3),1315 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;1316 1317def : Pat<(mul GRRegs:$src, 5),1318 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;1319 1320def : Pat<(mul GRRegs:$src, -3),1321 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;1322 1323// ashr X, 32 is equivalent to ashr X, 31 on the XCore.1324def : Pat<(sra GRRegs:$src, 31),1325 (ASHR_l2rus GRRegs:$src, 32)>;1326 1327def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),1328 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;1329 1330// setge X, 0 is canonicalized to setgt X, -11331def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),1332 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;1333 1334def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),1335 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;1336 1337def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),1338 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;1339 1340def : Pat<(setgt GRRegs:$lhs, -1),1341 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;1342 1343def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),1344 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;1345 1346def : Pat<(load (cprelwrapper tconstpool:$b)),1347 (LDWCP_lru6 tconstpool:$b)>;1348 1349def : Pat<(cprelwrapper tconstpool:$b),1350 (LDAWCP_lu6 tconstpool:$b)>;1351