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1//===-- XtensaMCTargetDesc.h - Xtensa Target Descriptions -------*- C++ -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file provides Xtensa specific target descriptions.12//13//===----------------------------------------------------------------------===//14 15#ifndef LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H16#define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H17#include "llvm/Support/DataTypes.h"18#include <memory>19 20namespace llvm {21 22class FeatureBitset;23class MCAsmBackend;24class MCCodeEmitter;25class MCContext;26class MCInstrInfo;27class MCObjectTargetWriter;28class MCObjectWriter;29class MCRegister;30class MCRegisterInfo;31class MCSubtargetInfo;32class MCTargetOptions;33class MachineInstr;34class StringRef;35class Target;36class raw_ostream;37 38extern Target TheXtensaTarget;39 40MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII,41 MCContext &Ctx);42 43MCAsmBackend *createXtensaAsmBackend(const Target &T,44 const MCSubtargetInfo &STI,45 const MCRegisterInfo &MRI,46 const MCTargetOptions &Options);47std::unique_ptr<MCObjectTargetWriter>48createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian);49 50namespace Xtensa {51// Check address offset for load/store instructions.52// The offset should be multiple of scale.53bool isValidAddrOffset(int Scale, int64_t OffsetVal);54 55// Check address offset for load/store instructions.56bool isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset);57 58enum RegisterAccessType {59 REGISTER_WRITE = 1,60 REGISTER_READ = 2,61 REGISTER_EXCHANGE = 362};63 64// Verify if it's correct to use a special register.65bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,66 RegisterAccessType RA);67 68// Get Xtensa User Register by register encoding value.69MCRegister getUserRegister(unsigned Code, const MCRegisterInfo &MRI);70} // namespace Xtensa71} // end namespace llvm72 73// Defines symbolic names for Xtensa registers.74// This defines a mapping from register name to register number.75#define GET_REGINFO_ENUM76#include "XtensaGenRegisterInfo.inc"77 78// Defines symbolic names for the Xtensa instructions.79#define GET_INSTRINFO_ENUM80#include "XtensaGenInstrInfo.inc"81 82#define GET_SUBTARGETINFO_ENUM83#include "XtensaGenSubtargetInfo.inc"84 85#endif // LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H86