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1//===- XtensaDSPInstrInfo.td - Xtensa Target Description ---*- tablegen -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file describes the Xtensa DSP instructions in TableGen format.12//13//===----------------------------------------------------------------------===//14 15// Multiply16class UMUL_AA<bits<4> oper1, string instrAsm>17 : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),18 instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {19 let r = 0;20 let Defs = [M1, M2, ACCLO, ACCHI];21}22 23def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll">;24def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl">;25def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh">;26def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh">;27 28class MUL_AA<bits<4> oper1, string instrAsm>29 : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),30 instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {31 let r = 0;32 let Defs = [M1, M2, ACCLO, ACCHI];33}34 35def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll">;36def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl">;37def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh">;38def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh">;39 40class MUL_AD<bits<4> oper1, string instrAsm>41 : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),42 instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {43 bits<2> y;44 45 let r = 0;46 let t{3} = 0;47 let t{2} = y{0};48 let t{1-0} = 0;49 let Defs = [M1, M2, ACCLO, ACCHI];50}51 52def MUL_AD_LL : MUL_AD<0x04, "mul.ad.ll">;53def MUL_AD_HL : MUL_AD<0x05, "mul.ad.hl">;54def MUL_AD_LH : MUL_AD<0x06, "mul.ad.lh">;55def MUL_AD_HH : MUL_AD<0x07, "mul.ad.hh">;56 57class MUL_DA<bits<4> oper1, string instrAsm>58 : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),59 instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {60 bits<2> x;61 62 let r{3} = 0;63 let r{2} = x{0};64 let r{1-0} = 0;65 let s = 0;66 let Defs = [M1, M2, ACCLO, ACCHI];67}68 69def MUL_DA_LL : MUL_DA<0x04, "mul.da.ll">;70def MUL_DA_HL : MUL_DA<0x05, "mul.da.hl">;71def MUL_DA_LH : MUL_DA<0x06, "mul.da.lh">;72def MUL_DA_HH : MUL_DA<0x07, "mul.da.hh">;73 74class MUL_DD<bits<4> oper1, string instrAsm>75 : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),76 instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {77 bits<2> x;78 bits<2> y;79 80 let r{3} = 0;81 let r{2} = x{0};82 let r{1-0} = 0;83 let s = 0;84 let t{3} = 0;85 let t{2} = y{0};86 let t{1-0} = 0;87 let Defs = [M1, M2, ACCLO, ACCHI];88}89 90def MUL_DD_LL : MUL_DD<0x04, "mul.dd.ll">;91def MUL_DD_HL : MUL_DD<0x05, "mul.dd.hl">;92def MUL_DD_LH : MUL_DD<0x06, "mul.dd.lh">;93def MUL_DD_HH : MUL_DD<0x07, "mul.dd.hh">;94 95class MULA_AA<bits<4> oper1, string instrAsm>96 : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),97 instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {98 let r = 0;99 let Defs = [M1, M2, ACCLO, ACCHI];100}101 102def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll">;103def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl">;104def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh">;105def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh">;106 107class MULA_AD<bits<4> oper1, string instrAsm>108 : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),109 instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {110 bits<2> y;111 112 let r = 0;113 let t{3} = 0;114 let t{2} = y{0};115 let t{1-0} = 0;116 117 let Uses = [ACCLO, ACCHI];118 let Defs = [M1, M2, ACCLO, ACCHI];119}120 121def MULA_AD_LL : MULA_AD<0x08, "mula.ad.ll">;122def MULA_AD_HL : MULA_AD<0x09, "mula.ad.hl">;123def MULA_AD_LH : MULA_AD<0x0A, "mula.ad.lh">;124def MULA_AD_HH : MULA_AD<0x0B, "mula.ad.hh">;125 126class MULA_DA<bits<4> oper1, string instrAsm>127 : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),128 instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {129 bits<2> x;130 131 let r{3} = 0;132 let r{2} = x{0};133 let r{1-0} = 0;134 let s = 0;135 136 let Uses = [ACCLO, ACCHI];137 let Defs = [M1, M2, ACCLO, ACCHI];138}139 140def MULA_DA_LL : MULA_DA<0x08, "mula.da.ll">;141def MULA_DA_HL : MULA_DA<0x09, "mula.da.hl">;142def MULA_DA_LH : MULA_DA<0x0A, "mula.da.lh">;143def MULA_DA_HH : MULA_DA<0x0B, "mula.da.hh">;144 145class MULA_DD<bits<4> oper1, string instrAsm>146 : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),147 instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {148 bits<2> x;149 bits<2> y;150 151 let r{3} = 0;152 let r{2} = x{0};153 let r{1-0} = 0;154 let s = 0;155 let t{3} = 0;156 let t{2} = y{0};157 let t{1-0} = 0;158 159 let Uses = [ACCLO, ACCHI];160 let Defs = [M1, M2, ACCLO, ACCHI];161}162 163def MULA_DD_LL : MULA_DD<0x08, "mula.dd.ll">;164def MULA_DD_HL : MULA_DD<0x09, "mula.dd.hl">;165def MULA_DD_LH : MULA_DD<0x0A, "mula.dd.lh">;166def MULA_DD_HH : MULA_DD<0x0B, "mula.dd.hh">;167 168class MULS_AA<bits<4> oper1, string instrAsm>169 : RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),170 instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {171 let r = 0;172 let Uses = [ACCLO, ACCHI];173 let Defs = [M1, M2, ACCLO, ACCHI];174}175 176def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll">;177def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl">;178def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh">;179def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh">;180 181class MULS_AD<bits<4> oper1, string instrAsm>182 : RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),183 instrAsm#"\t$s, $y", []>, Requires<[HasMAC16]> {184 bits<2> y;185 186 let r = 0;187 let t{3} = 0;188 let t{2} = y{0};189 let t{1-0} = 0;190 191 let Uses = [ACCLO, ACCHI];192 let Defs = [M1, M2, ACCLO, ACCHI];193}194 195def MULS_AD_LL : MULS_AD<0x0C, "muls.ad.ll">;196def MULS_AD_HL : MULS_AD<0x0D, "muls.ad.hl">;197def MULS_AD_LH : MULS_AD<0x0E, "muls.ad.lh">;198def MULS_AD_HH : MULS_AD<0x0F, "muls.ad.hh">;199 200class MULS_DA<bits<4> oper1, string instrAsm>201 : RRR_Inst<0x04, oper1, 0x06, (outs), (ins MR01:$x, AR:$t),202 instrAsm#"\t$x, $t", []>, Requires<[HasMAC16]> {203 bits<2> x;204 205 let r{3} = 0;206 let r{2} = x{0};207 let r{1-0} = 0;208 let s = 0;209 210 let Uses = [ACCLO, ACCHI];211 let Defs = [M1, M2, ACCLO, ACCHI];212}213 214def MULS_DA_LL : MULS_DA<0x0C, "muls.da.ll">;215def MULS_DA_HL : MULS_DA<0x0D, "muls.da.hl">;216def MULS_DA_LH : MULS_DA<0x0E, "muls.da.lh">;217def MULS_DA_HH : MULS_DA<0x0F, "muls.da.hh">;218 219class MULS_DD<bits<4> oper1, string instrAsm>220 : RRR_Inst<0x04, oper1, 0x02, (outs), (ins MR01:$x, MR23:$y),221 instrAsm#"\t$x, $y", []>, Requires<[HasMAC16]> {222 bits<2> x;223 bits<2> y;224 225 let r{3} = 0;226 let r{2} = x{0};227 let r{1-0} = 0;228 let s = 0;229 let t{3} = 0;230 let t{2} = y{0};231 let t{1-0} = 0;232 233 let Uses = [ACCLO, ACCHI];234 let Defs = [M1, M2, ACCLO, ACCHI];235}236 237def MULS_DD_LL : MULS_DD<0x0C, "muls.dd.ll">;238def MULS_DD_HL : MULS_DD<0x0D, "muls.dd.hl">;239def MULS_DD_LH : MULS_DD<0x0E, "muls.dd.lh">;240def MULS_DD_HH : MULS_DD<0x0F, "muls.dd.hh">;241 242//===----------------------------------------------------------------------===//243// Multiply-accumulate with load244 245class MULA_DA_LDDEC<bits<4> oper1, string instrAsm>246 : RRR_Inst<0x04, oper1, 0x05, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, AR:$t),247 instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> {248 bits<2> x;249 bits<2> w;250 251 let Constraints = "$s = $d";252 let mayLoad = 1;253 let r{3} = 0;254 let r{2} = x{0};255 let r{1-0} = w{1-0};256 let Uses = [ACCLO, ACCHI];257 let Defs = [M1, M2, ACCLO, ACCHI];258}259 260def MULA_DA_LL_LDDEC : MULA_DA_LDDEC<0x08, "mula.da.ll.lddec">;261def MULA_DA_HL_LDDEC : MULA_DA_LDDEC<0x09, "mula.da.hl.lddec">;262def MULA_DA_LH_LDDEC : MULA_DA_LDDEC<0x0A, "mula.da.lh.lddec">;263def MULA_DA_HH_LDDEC : MULA_DA_LDDEC<0x0B, "mula.da.hh.lddec">;264 265class MULA_DA_LDINC<bits<4> oper1, string instrAsm>266 : RRR_Inst<0x04, oper1, 0x04, (outs MR:$w, AR:$d), (ins AR:$s, MR:$x, AR:$t),267 instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> {268 bits<1> x;269 bits<2> w;270 271 let Constraints = "$s = $d";272 let mayLoad = 1;273 let r{3} = 0;274 let r{2} = x{0};275 let r{1-0} = w{1-0};276 let Uses = [ACCLO, ACCHI];277 let Defs = [M1, M2, ACCLO, ACCHI];278}279 280def MULA_DA_LL_LDINC: MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">;281def MULA_DA_HL_LDINC: MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">;282def MULA_DA_LH_LDINC: MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">;283def MULA_DA_HH_LDINC: MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">;284 285class MULA_DD_LDDEC<bits<4> oper1, string instrAsm>286 : RRR_Inst<0x04, oper1, 0x01, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),287 instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> {288 bits<2> x;289 bits<2> y;290 bits<2> w;291 292 let Constraints = "$s = $d";293 let mayLoad = 1;294 let r{3} = 0;295 let r{2} = x{0};296 let r{1-0} = w{1-0};297 let t{3} = 0;298 let t{2} = y{0};299 let t{1-0} = 0;300 let Uses = [ACCLO, ACCHI];301 let Defs = [M1, M2, ACCLO, ACCHI];302}303 304def MULA_DD_LL_LDDEC : MULA_DD_LDDEC<0x08, "mula.dd.ll.lddec">;305def MULA_DD_HL_LDDEC : MULA_DD_LDDEC<0x09, "mula.dd.hl.lddec">;306def MULA_DD_LH_LDDEC : MULA_DD_LDDEC<0x0A, "mula.dd.lh.lddec">;307def MULA_DD_HH_LDDEC : MULA_DD_LDDEC<0x0B, "mula.dd.hh.lddec">;308 309class MULA_DD_LDINC<bits<4> oper1, string instrAsm>310 : RRR_Inst<0x04, oper1, 0x00, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),311 instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> {312 bits<2> x;313 bits<2> y;314 bits<2> w;315 316 let Constraints = "$s = $d";317 let mayLoad = 1;318 let r{3} = 0;319 let r{2} = x{0};320 let r{1-0} = w{1-0};321 let t{3} = 0;322 let t{2} = y{0};323 let t{1-0} = 0;324 let Uses = [ACCLO, ACCHI];325 let Defs = [M1, M2, ACCLO, ACCHI];326}327 328def MULA_DD_LL_LDINC : MULA_DD_LDINC<0x08, "mula.dd.ll.ldinc">;329def MULA_DD_HL_LDINC : MULA_DD_LDINC<0x09, "mula.dd.hl.ldinc">;330def MULA_DD_LH_LDINC : MULA_DD_LDINC<0x0A, "mula.dd.lh.ldinc">;331def MULA_DD_HH_LDINC : MULA_DD_LDINC<0x0B, "mula.dd.hh.ldinc">;332 333def LDDEC : RRR_Inst<0x04, 0x00, 0x09, (outs MR:$w, AR:$d), (ins AR:$s),334 "lddec\t $w, $s", []>, Requires<[HasMAC16]> {335 bits<2> w;336 337 let Constraints = "$s = $d";338 let mayLoad = 1;339 let r{3-2} = 0;340 let r{1-0} = w{1-0};341 let t = 0x00;342}343 344def LDINC : RRR_Inst<0x04, 0x00, 0x08, (outs MR:$w, AR:$d), (ins AR:$s),345 "ldinc\t $w, $s", []>, Requires<[HasMAC16]> {346 bits<2> w;347 348 let Constraints = "$s = $d";349 let mayLoad = 1;350 let r{3-2} = 0;351 let r{1-0} = w{1-0};352 let t = 0;353}354