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1//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the interfaces that Xtensa uses to lower LLVM code into a10// selection DAG.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H15#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H16 17#include "llvm/CodeGen/CallingConvLower.h"18#include "llvm/CodeGen/SelectionDAG.h"19#include "llvm/CodeGen/TargetLowering.h"20 21namespace llvm {22 23class XtensaSubtarget;24 25class XtensaTargetLowering : public TargetLowering {26public:27 explicit XtensaTargetLowering(const TargetMachine &TM,28 const XtensaSubtarget &STI);29 30 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {31 return LHSTy.getSizeInBits() <= 32 ? MVT::i32 : MVT::i64;32 }33 34 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,35 EVT VT) const override;36 37 EVT getSetCCResultType(const DataLayout &, LLVMContext &,38 EVT VT) const override {39 if (!VT.isVector())40 return MVT::i32;41 return VT.changeVectorElementTypeToInteger();42 }43 44 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;45 46 bool isFPImmLegal(const APFloat &Imm, EVT VT,47 bool ForCodeSize) const override;48 49 std::pair<unsigned, const TargetRegisterClass *>50 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,51 StringRef Constraint, MVT VT) const override;52 53 TargetLowering::ConstraintType54 getConstraintType(StringRef Constraint) const override;55 56 TargetLowering::ConstraintWeight57 getSingleConstraintMatchWeight(AsmOperandInfo &Info,58 const char *Constraint) const override;59 60 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,61 std::vector<SDValue> &Ops,62 SelectionDAG &DAG) const override;63 64 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;65 66 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,67 bool isVarArg,68 const SmallVectorImpl<ISD::InputArg> &Ins,69 const SDLoc &DL, SelectionDAG &DAG,70 SmallVectorImpl<SDValue> &InVals) const override;71 72 SDValue LowerCall(CallLoweringInfo &CLI,73 SmallVectorImpl<SDValue> &InVals) const override;74 75 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,76 bool isVarArg,77 const SmallVectorImpl<ISD::OutputArg> &Outs,78 LLVMContext &Context, const Type *RetTy) const override;79 80 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,81 const SmallVectorImpl<ISD::OutputArg> &Outs,82 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,83 SelectionDAG &DAG) const override;84 85 bool shouldInsertFencesForAtomic(const Instruction *I) const override {86 return true;87 }88 89 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;90 91 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,92 SDValue C) const override;93 94 const XtensaSubtarget &getSubtarget() const { return Subtarget; }95 96 MachineBasicBlock *97 EmitInstrWithCustomInserter(MachineInstr &MI,98 MachineBasicBlock *BB) const override;99 100private:101 const XtensaSubtarget &Subtarget;102 103 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;104 105 SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;106 107 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;108 109 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;110 111 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;112 113 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;114 115 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;116 117 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;118 119 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;120 121 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;122 123 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;124 125 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;126 127 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;128 129 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;130 131 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;132 133 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;134 135 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;136 137 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;138 139 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;140 141 SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const;142 143 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;144 145 MachineBasicBlock *emitSelectCC(MachineInstr &MI,146 MachineBasicBlock *BB) const;147};148 149} // end namespace llvm150 151#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H */152