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1//===- XtensaInstrFormats.td - Xtensa Instruction Formats --*- tablegen -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10 11// Base class for Xtensa 16 & 24 bit Formats12class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,13 InstrItinClass itin = NoItinerary>14 : Instruction {15 let Namespace = "Xtensa";16 17 let Size = size;18 19 let OutOperandList = outs;20 let InOperandList = ins;21 22 let AsmString = asmstr;23 let Pattern = pattern;24 let Itinerary = itin;25 26}27 28// Base class for Xtensa 24 bit Format29class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,30 InstrItinClass itin = NoItinerary>31 : XtensaInst<3, outs, ins, asmstr, pattern, itin> {32 field bits<24> Inst;33}34 35// Base class for Xtensa 16 bit Format36class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,37 InstrItinClass itin = NoItinerary>38 : XtensaInst<2, outs, ins, asmstr, pattern, itin> {39 field bits<16> Inst;40 let Predicates = [HasDensity];41}42 43class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,44 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>45 : XtensaInst24<outs, ins, asmstr, pattern, itin> {46 bits<4> r;47 bits<4> s;48 bits<4> t;49 50 let Inst{23-20} = op2;51 let Inst{19-16} = op1;52 let Inst{15-12} = r;53 let Inst{11-8} = s;54 let Inst{7-4} = t;55 let Inst{3-0} = op0;56}57 58class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,59 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>60 : XtensaInst24<outs, ins, asmstr, pattern, itin> {61 bits<4> r;62 bits<4> s;63 bits<4> t;64 bits<4> imm4;65 66 let Inst{23-20} = imm4;67 let Inst{19-16} = op1;68 let Inst{15-12} = r;69 let Inst{11-8} = s;70 let Inst{7-4} = t;71 let Inst{3-0} = op0;72}73 74class RRI8_Inst<bits<4> op0, dag outs, dag ins,75 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>76 : XtensaInst24<outs, ins, asmstr, pattern, itin> {77 bits<4> r;78 bits<4> s;79 bits<4> t;80 bits<8> imm8;81 82 let Inst{23-16} = imm8;83 let Inst{15-12} = r;84 let Inst{11-8} = s;85 let Inst{7-4} = t;86 let Inst{3-0} = op0;87}88 89class RI16_Inst<bits<4> op0, dag outs, dag ins,90 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>91 : XtensaInst24<outs, ins, asmstr, pattern, itin> {92 bits<4> t;93 bits<16> imm16;94 95 let Inst{23-8} = imm16;96 let Inst{7-4} = t;97 let Inst{3-0} = op0;98}99 100class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,101 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>102 : XtensaInst24<outs, ins, asmstr, pattern, itin> {103 bits<8> sr;104 bits<4> t;105 106 let Inst{23-20} = op2;107 let Inst{19-16} = op1;108 let Inst{15-8} = sr;109 let Inst{7-4} = t;110 let Inst{3-0} = op0;111}112 113class CALL_Inst<bits<4> op0, dag outs, dag ins,114 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>115 : XtensaInst24<outs, ins, asmstr, pattern, itin> {116 bits<18> offset;117 bits<2> n;118 119 let Inst{23-6} = offset;120 let Inst{5-4} = n;121 let Inst{3-0} = op0;122}123 124class CALLX_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,125 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>126 : XtensaInst24<outs, ins, asmstr, pattern, itin> {127 bits<4> r;128 bits<4> s;129 bits<2> m;130 bits<2> n;131 132 let Inst{23-20} = op2;133 let Inst{19-16} = op1;134 let Inst{15-12} = r;135 let Inst{11-8} = s;136 let Inst{7-6} = m;137 let Inst{5-4} = n;138 let Inst{3-0} = op0;139}140 141class BRI8_Inst<bits<4> op0, dag outs, dag ins,142 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>143 : XtensaInst24<outs, ins, asmstr, pattern, itin> {144 bits<8> imm8;145 bits<4> r;146 bits<4> s;147 bits<2> m;148 bits<2> n;149 150 let Inst{23-16} = imm8;151 let Inst{15-12} = r;152 let Inst{11-8} = s;153 let Inst{7-6} = m;154 let Inst{5-4} = n;155 let Inst{3-0} = op0;156}157 158class BRI12_Inst<bits<4> op0, bits<2> n, bits<2> m, dag outs, dag ins,159 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>160 : XtensaInst24<outs, ins, asmstr, pattern, itin> {161 bits<12> imm12;162 bits<4> s;163 164 let Inst{23-12} = imm12;165 let Inst{11-8} = s;166 let Inst{7-6} = m;167 let Inst{5-4} = n;168 let Inst{3-0} = op0;169}170 171class RRRN_Inst<bits<4> op0, dag outs, dag ins,172 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>173 : XtensaInst16<outs, ins, asmstr, pattern, itin> {174 bits<4> r;175 bits<4> s;176 bits<4> t;177 178 let Inst{15-12} = r;179 let Inst{11-8} = s;180 let Inst{7-4} = t;181 let Inst{3-0} = op0;182}183 184class RI7_Inst<bits<4> op0, bits<1> i, dag outs, dag ins,185 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>186 : XtensaInst16<outs, ins, asmstr, pattern, itin> {187 bits<7> imm7;188 bits<4> s;189 190 let Inst{15-12} = imm7{3-0};191 let Inst{11-8} = s;192 let Inst{7} = i;193 let Inst{6-4} = imm7{6-4};194 let Inst{3-0} = op0;195}196 197class RI6_Inst<bits<4> op0, bits<1> i, bits<1> z, dag outs, dag ins,198 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>199 : XtensaInst16<outs, ins, asmstr, pattern, itin> {200 bits<6> imm6;201 bits<4> s;202 203 let Inst{15-12} = imm6{3-0};204 let Inst{11-8} = s;205 let Inst{7} = i;206 let Inst{6} = z;207 let Inst{5-4} = imm6{5-4};208 let Inst{3-0} = op0;209}210 211// Pseudo instructions212class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>213 : XtensaInst<2, outs, ins, asmstr, pattern> {214 let isPseudo = 1;215 let isCodeGenOnly = 1;216}217