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1//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file contains the Xtensa implementation of the TargetInstrInfo class.12//13//===----------------------------------------------------------------------===//14 15#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H16#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H17 18#include "Xtensa.h"19#include "XtensaRegisterInfo.h"20#include "llvm/CodeGen/TargetInstrInfo.h"21#include "llvm/CodeGen/TargetRegisterInfo.h"22 23#define GET_INSTRINFO_HEADER24 25#include "XtensaGenInstrInfo.inc"26 27namespace llvm {28 29class XtensaTargetMachine;30class XtensaSubtarget;31class XtensaInstrInfo : public XtensaGenInstrInfo {32 const XtensaRegisterInfo RI;33 const XtensaSubtarget &STI;34 35public:36 XtensaInstrInfo(const XtensaSubtarget &STI);37 38 void adjustStackPtr(MCRegister SP, int64_t Amount, MachineBasicBlock &MBB,39 MachineBasicBlock::iterator I) const;40 41 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;42 43 // Return the XtensaRegisterInfo, which this class owns.44 const XtensaRegisterInfo &getRegisterInfo() const { return RI; }45 46 Register isLoadFromStackSlot(const MachineInstr &MI,47 int &FrameIndex) const override;48 49 Register isStoreToStackSlot(const MachineInstr &MI,50 int &FrameIndex) const override;51 52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,53 const DebugLoc &DL, Register DestReg, Register SrcReg,54 bool KillSrc, bool RenamableDest = false,55 bool RenamableSrc = false) const override;56 57 void storeRegToStackSlot(58 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,59 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,60 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;61 62 void loadRegFromStackSlot(63 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,64 Register DestReg, int FrameIdx, const TargetRegisterClass *RC,65 Register VReg,66 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;67 68 // Get the load and store opcodes for a given register class and offset.69 void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,70 unsigned &StoreOpcode, int64_t offset) const;71 72 // Emit code before MBBI in MI to move immediate value Value into73 // physical register Reg.74 void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,75 MCRegister *Reg, int64_t Value) const;76 77 bool78 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;79 80 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;81 82 bool isBranchOffsetInRange(unsigned BranchOpc,83 int64_t BrOffset) const override;84 85 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,86 MachineBasicBlock *&FBB,87 SmallVectorImpl<MachineOperand> &Cond,88 bool AllowModify) const override;89 90 unsigned removeBranch(MachineBasicBlock &MBB,91 int *BytesRemoved = nullptr) const override;92 93 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,94 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,95 const DebugLoc &DL,96 int *BytesAdded = nullptr) const override;97 98 void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB,99 MachineBasicBlock &RestoreBB, const DebugLoc &DL,100 int64_t BrOffset = 0,101 RegScavenger *RS = nullptr) const override;102 103 unsigned insertBranchAtInst(MachineBasicBlock &MBB,104 MachineBasicBlock::iterator I,105 MachineBasicBlock *TBB,106 ArrayRef<MachineOperand> Cond, const DebugLoc &DL,107 int *BytesAdded) const;108 109 unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I,110 int64_t offset,111 ArrayRef<MachineOperand> Cond, DebugLoc DL,112 int *BytesAdded) const;113 114 // Return true if MI is a conditional or unconditional branch.115 // When returning true, set Cond to the mask of condition-code116 // values on which the instruction will branch, and set Target117 // to the operand that contains the branch target. This target118 // can be a register or a basic block.119 bool isBranch(const MachineBasicBlock::iterator &MI,120 SmallVectorImpl<MachineOperand> &Cond,121 const MachineOperand *&Target) const;122 123 const XtensaSubtarget &getSubtarget() const { return STI; }124};125} // end namespace llvm126 127#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */128