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1//===- XtensaInstrInfo.td - Target Description for Xtensa -*- tablegen -*--===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file describes the Xtensa instructions in TableGen format.12//13//===----------------------------------------------------------------------===//14 15include "XtensaInstrFormats.td"16include "XtensaOperands.td"17include "XtensaOperators.td"18 19//===----------------------------------------------------------------------===//20// Arithmetic & Logical instructions21//===----------------------------------------------------------------------===//22 23class ArithLogic_RRR<bits<4> oper2, bits<4> oper1, string instrAsm,24 SDPatternOperator opNode, bit isComm = 0>25 : RRR_Inst<0x00, oper1, oper2, (outs AR:$r), (ins AR:$s, AR:$t),26 instrAsm#"\t$r, $s, $t",27 [(set AR:$r, (opNode AR:$s, AR:$t))]> {28 let isCommutable = isComm;29 let isReMaterializable = 0;30}31 32def ADD : ArithLogic_RRR<0x08, 0x00, "add", add, 1>;33def SUB : ArithLogic_RRR<0x0C, 0x00, "sub", sub>;34def AND : ArithLogic_RRR<0x01, 0x00, "and", and, 1>;35def OR : ArithLogic_RRR<0x02, 0x00, "or", or, 1>;36def XOR : ArithLogic_RRR<0x03, 0x00, "xor", xor, 1>;37 38class ADDX<bits<4> oper, string instrAsm, list<dag> pattern>39 : RRR_Inst<0x00, 0x00, oper, (outs AR:$r), (ins AR:$s, AR:$t),40 instrAsm#"\t$r, $s, $t", pattern>;41 42def ADDX2 : ADDX<0x09, "addx2", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 1))))]>;43def ADDX4 : ADDX<0x0A, "addx4", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 2))))]>;44def ADDX8 : ADDX<0x0B, "addx8", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 3))))]>;45 46class SUBX<bits<4> oper, string instrAsm, list<dag> pattern>47 : RRR_Inst<0x00, 0x00, oper, (outs AR:$r), (ins AR:$s, AR:$t),48 instrAsm#"\t$r, $s, $t", pattern>;49 50def SUBX2 : SUBX<0x0D, "subx2", [(set AR:$r, (sub (shl AR:$s, (i32 1)), AR:$t))]>;51def SUBX4 : SUBX<0x0E, "subx4", [(set AR:$r, (sub (shl AR:$s, (i32 2)), AR:$t))]>;52def SUBX8 : SUBX<0x0F, "subx8", [(set AR:$r, (sub (shl AR:$s, (i32 3)), AR:$t))]>;53 54def ABS : RRR_Inst<0x00, 0x00, 0x06, (outs AR:$r), (ins AR:$t),55 "abs\t$r, $t", []> {56 let s = 0x1;57}58 59def ADDI : RRI8_Inst<0x02, (outs AR:$t), (ins AR:$s, imm8:$imm8),60 "addi\t$t, $s, $imm8",61 [(set AR:$t, (add AR:$s, imm8:$imm8))]> {62 let r = 0x0C;63}64 65def ADDMI : RRI8_Inst<0x02, (outs AR:$t), (ins AR:$s, imm8_sh8:$imm_sh8),66 "addmi\t$t, $s, $imm_sh8",67 [(set AR:$t, (add AR:$s, imm8_sh8:$imm_sh8))]> {68 bits<16> imm_sh8;69 70 let r = 0x0D;71 let imm8 = imm_sh8{15-8};72}73 74def NEG : RRR_Inst<0x00, 0x00, 0x06, (outs AR:$r), (ins AR:$t),75 "neg\t$r, $t",76 [(set AR:$r, (ineg AR:$t))]> {77 let s = 0x00;78}79 80//===----------------------------------------------------------------------===//81// Move instructions82//===----------------------------------------------------------------------===//83def MOVI : RRI8_Inst<0x02, (outs AR:$t), (ins imm12m:$imm),84 "movi\t$t, $imm",85 [(set AR:$t, imm12m:$imm)]> {86 bits<12> imm;87 88 let imm8{7-0} = imm{7-0};89 let s{3-0} = imm{11-8};90 let r = 0xa;91}92 93def MOVEQZ : RRR_Inst<0x00, 0x03, 0x08, (outs AR:$r), (ins AR:$s, AR:$t),94 "moveqz\t$r, $s, $t", []>;95def MOVNEZ : RRR_Inst<0x00, 0x03, 0x09, (outs AR:$r), (ins AR:$s, AR:$t),96 "movnez\t$r, $s, $t", []>;97def MOVLTZ : RRR_Inst<0x00, 0x03, 0x0A, (outs AR:$r), (ins AR:$s, AR:$t),98 "movltz\t$r, $s, $t", []>;99def MOVGEZ : RRR_Inst<0x00, 0x03, 0x0B, (outs AR:$r), (ins AR:$s, AR:$t),100 "movgez\t$r, $s, $t", []>;101 102//===----------------------------------------------------------------------===//103// Shift instructions104//===----------------------------------------------------------------------===//105 106let Uses = [SAR] in {107 def SLL : RRR_Inst<0x00, 0x01, 0x0A, (outs AR:$r), (ins AR:$s),108 "sll\t$r, $s", []> {109 let t = 0x00;110 }111 112 def SRA : RRR_Inst<0x00, 0x01, 0x0B, (outs AR:$r), (ins AR:$t),113 "sra\t$r, $t", []> {114 let s = 0x00;115 }116 117 def SRC : RRR_Inst<0x00, 0x01, 0x08, (outs AR:$r), (ins AR:$s, AR:$t),118 "src\t$r, $s, $t", []>;119 120 def SRL : RRR_Inst<0x00, 0x01, 0x09, (outs AR:$r), (ins AR:$t),121 "srl\t$r, $t", []> {122 let s = 0x00;123 }124}125 126let Defs = [SAR] in {127 def SSL : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$s),128 "ssl\t$s", []> {129 let r = 0x01;130 let t = 0x00;131 }132 133 def SSR : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$s),134 "ssr\t$s", []> {135 let r = 0x00;136 let t = 0x00;137 }138}139 140def EXTUI : RRR_Inst<0x00, 0x04, 0x00, (outs AR:$r), (ins AR:$t, uimm5:$imm1, imm1_16:$imm2),141 "extui\t$r, $t, $imm1, $imm2",142 [(set AR:$r, (Xtensa_extui AR:$t, uimm5:$imm1, imm1_16:$imm2))]> {143 bits<5> imm1;144 bits<4> imm2;145 146 let s = imm1{3-0};147 let Inst{16} = imm1{4};148 let Inst{23-20} = imm2;149}150 151def SRAI : RRR_Inst<0x00, 0x01, 0x02, (outs AR:$r), (ins AR:$t, uimm5:$sa),152 "srai\t$r, $t, $sa",153 [(set AR:$r, (sra AR:$t, uimm5:$sa))]> {154 bits<5> sa;155 156 let Inst{20} = sa{4};157 let s = sa{3-0};158}159 160def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),161 "srli\t$r, $t, $sa",162 [(set AR:$r, (srl AR:$t, uimm4:$sa))]> {163 bits<4> sa;164 165 let s = sa;166}167 168def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa),169 "slli\t$r, $s, $sa",170 [(set AR:$r, (shl AR:$s, shimm1_31:$sa))]> {171 bits<5> sa;172 173 let Inst{20} = sa{4};174 let t = sa{3-0};175}176 177def SSA8L : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins AR:$s),178 "ssa8l\t$s", []> {179 let r = 0x2;180 let t = 0x0;181}182 183def SSAI : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins uimm5:$imm),184 "ssai\t$imm", []> {185 bits<5> imm;186 187 let r = 0x04;188 let s = imm{3-0};189 let t{3-1} = 0;190 let t{0} = imm{4};191}192 193//===----------------------------------------------------------------------===//194// Load and store instructions195//===----------------------------------------------------------------------===//196 197// Load instructions198let mayLoad = 1, usesCustomInserter = 1 in {199 200 class Load_RRI8<bits<4> oper, string instrAsm, SDPatternOperator opNode,201 ComplexPattern addrOp, Operand memOp>202 : RRI8_Inst<0x02, (outs AR:$t), (ins memOp:$addr),203 instrAsm#"\t$t, $addr",204 [(set AR:$t, (opNode addrOp:$addr))]> {205 bits<12> addr;206 207 let r = oper;208 let imm8{7-0} = addr{11-4};209 let s{3-0} = addr{3-0};210 }211}212 213def L8UI : Load_RRI8<0x00, "l8ui", zextloadi8, addr_ish1, mem8>;214def L16SI : Load_RRI8<0x09, "l16si", sextloadi16, addr_ish2, mem16>;215def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>;216def L32I : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>;217 218// Store instructions219let mayStore = 1, usesCustomInserter = 1 in {220 class Store_II8<bits<4> oper, string instrAsm, SDPatternOperator opNode,221 ComplexPattern addrOp, Operand memOp>222 : RRI8_Inst<0x02, (outs), (ins AR:$t, memOp:$addr),223 instrAsm#"\t$t, $addr",224 [(opNode AR:$t, addrOp:$addr)]> {225 bits<12> addr;226 227 let r = oper;228 let imm8{7-0} = addr{11-4};229 let s{3-0} = addr{3-0};230 }231}232 233def S8I : Store_II8<0x04, "s8i", truncstorei8, addr_ish1, mem8>;234def S16I : Store_II8<0x05, "s16i", truncstorei16, addr_ish2, mem16>;235def S32I : Store_II8<0x06, "s32i", store, addr_ish4, mem32>;236 237let AddedComplexity = 10 in238def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label),239 "l32r\t$t, $label", [(set AR:$t, (load (Xtensa_pcrel_wrapper tconstpool:$label)))]> {240 bits<16> label;241 let imm16 = label;242}243 244// FrameIndexes are legalized when they are operands from load/store245// instructions. The same not happens for stack address copies, so an246// add op with mem ComplexPattern is used and the stack address copy247// can be matched.248// Setting of attribute mayLoad is trick to process instruction operands249// in function XtensaRegisterInfo::eliminateFI250 251let isCodeGenOnly = 1, mayLoad = 1 in {252 253 def LEA_ADD : RRI8_Inst<0x02, (outs AR:$t), (ins mem32:$addr),254 "addi\t$t, $addr",255 [(set AR:$t, addr_ish4:$addr)]> {256 bits<12> addr;257 258 let r = 0x0C;259 let imm8{7-0} = addr{11-4};260 let s{3-0} = addr{3-0};261 }262}263 264//extending loads265def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;266def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;267def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;268 269//===----------------------------------------------------------------------===//270// Conditional branch instructions271//===----------------------------------------------------------------------===//272let isBranch = 1, isTerminator = 1 in {273 class Branch_RR<bits<4> oper, string instrAsm, CondCode CC>274 : RRI8_Inst<0x07, (outs),275 (ins AR:$s, AR:$t, brtarget:$target),276 instrAsm#"\t$s, $t, $target",277 [(brcc CC, AR:$s, AR:$t, bb:$target)]> {278 bits<8> target;279 280 let r = oper;281 let imm8 = target;282 }283 284 class Branch_RI<bits<4> oper, string instrAsm, CondCode CC>285 : RRI8_Inst<0x06, (outs),286 (ins AR:$s, b4const:$imm, brtarget:$target),287 instrAsm#"\t$s, $imm, $target",288 [(brcc CC, AR:$s, b4const:$imm, bb:$target)]> {289 bits<4> imm;290 bits<8> target;291 292 let t = oper;293 let r = imm;294 let imm8 = target;295 }296 297 class Branch_RIU<bits<4> oper, string instrAsm, CondCode CC>298 : RRI8_Inst<0x06, (outs),299 (ins AR:$s, b4constu:$imm, brtarget:$target),300 instrAsm#"\t$s, $imm, $target",301 [(brcc CC, AR:$s, b4constu:$imm, bb:$target)]> {302 bits<4> imm;303 bits<8> target;304 305 let t = oper;306 let r = imm;307 let imm8 = target;308 }309 310 class Branch_RZ<bits<2> n, bits<2> m, string instrAsm, CondCode CC>311 : BRI12_Inst<0x06, n, m, (outs),312 (ins AR:$s, brtarget:$target),313 instrAsm#"\t$s, $target",314 [(brcc CC, AR:$s, (i32 0), bb:$target)]> {315 bits<12> target;316 317 let imm12 = target;318 }319}320 321def BEQ : Branch_RR<0x01, "beq", SETEQ>;322def BNE : Branch_RR<0x09, "bne", SETNE>;323def BGE : Branch_RR<0x0A, "bge", SETGE>;324def BLT : Branch_RR<0x02, "blt", SETLT>;325def BGEU : Branch_RR<0x0B, "bgeu", SETUGE>;326def BLTU : Branch_RR<0x03, "bltu", SETULT>;327 328def BEQI : Branch_RI<0x02, "beqi", SETEQ>;329def BNEI : Branch_RI<0x06, "bnei", SETNE>;330def BGEI : Branch_RI<0x0E, "bgei", SETGE>;331def BLTI : Branch_RI<0x0A, "blti", SETLT>;332def BGEUI : Branch_RIU<0x0F, "bgeui", SETUGE>;333def BLTUI : Branch_RIU<0x0B, "bltui", SETULT>;334 335def BEQZ : Branch_RZ<0x01, 0x00, "beqz", SETEQ>;336def BNEZ : Branch_RZ<0x01, 0x01, "bnez", SETNE>;337def BGEZ : Branch_RZ<0x01, 0x03, "bgez", SETGE>;338def BLTZ : Branch_RZ<0x01, 0x02, "bltz", SETLT>;339 340def BALL : RRI8_Inst<0x07, (outs),341 (ins AR:$s, AR:$t, brtarget:$target),342 "ball\t$s, $t, $target", []> {343 bits<8> target;344 345 let r = 0x04;346 let imm8 = target;347}348 349def BANY : RRI8_Inst<0x07, (outs),350 (ins AR:$s, AR:$t, brtarget:$target),351 "bany\t$s, $t, $target", []> {352 bits<8> target;353 354 let r = 0x08;355 let imm8 = target;356}357 358def BBC : RRI8_Inst<0x07, (outs),359 (ins AR:$s, AR:$t, brtarget:$target),360 "bbc\t$s, $t, $target", []> {361 bits<8> target;362 363 let r = 0x05;364 let imm8 = target;365}366 367def BBS : RRI8_Inst<0x07, (outs),368 (ins AR:$s, AR:$t, brtarget:$target),369 "bbs\t$s, $t, $target", []> {370 bits<8> target;371 372 let r = 0x0d;373 let imm8 = target;374}375 376def BNALL : RRI8_Inst<0x07, (outs),377 (ins AR:$s, AR:$t, brtarget:$target),378 "bnall\t$s, $t, $target", []> {379 bits<8> target;380 381 let r = 0x0c;382 let imm8 = target;383}384 385def BNONE : RRI8_Inst<0x07, (outs),386 (ins AR:$s, AR:$t, brtarget:$target),387 "bnone\t$s, $t, $target", []> {388 bits<8> target;389 390 let r = 0x00;391 let imm8 = target;392}393 394def BBCI : RRI8_Inst<0x07, (outs),395 (ins AR:$s, uimm5:$imm, brtarget:$target),396 "bbci\t$s, $imm, $target", []> {397 bits<8> target;398 bits<5> imm;399 400 let r{3-1} = 0x3;401 let r{0} = imm{4};402 let t{3-0} = imm{3-0};403 let imm8 = target;404}405 406def BBSI : RRI8_Inst<0x07, (outs),407 (ins AR:$s, uimm5:$imm, brtarget:$target),408 "bbsi\t$s, $imm, $target", []> {409 bits<8> target;410 bits<5> imm;411 412 let r{3-1} = 0x7;413 let r{0} = imm{4};414 let t{3-0} = imm{3-0};415 let imm8 = target;416}417 418def : Pat<(brcond AR:$s, bb:$target), (BNEZ AR:$s, bb:$target)>;419//===----------------------------------------------------------------------===//420// Call and jump instructions421//===----------------------------------------------------------------------===//422 423let isBranch = 1, isTerminator = 1, isBarrier = 1 in {424 def J : CALL_Inst<0x06, (outs), (ins jumptarget:$offset),425 "j\t$offset",426 [(br bb:$offset)]> {427 let n = 0x0;428 }429 430 def JX : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),431 "jx\t$s",432 [(brind AR:$s)]> {433 let m = 0x2;434 let n = 0x2;435 let r = 0;436 let isIndirectBranch = 1;437 }438}439 440let isCall = 1, Defs = [A0] in {441 def CALL0 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),442 "call0\t$offset", []> {443 let n = 0;444 }445 446 def CALLX0 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),447 "callx0\t$s", []> {448 let m = 0x3;449 let n = 0x0;450 let r = 0;451 }452}453 454let isReturn = 1, isTerminator = 1,455 isBarrier = 1, Uses = [A0] in {456 457 def RET : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),458 "ret", [(Xtensa_ret)]> {459 let m = 0x2;460 let n = 0x0;461 let s = 0;462 let r = 0;463 }464}465 466// Call patterns467def : Pat<(Xtensa_call (i32 tglobaladdr:$dst)),468 (CALL0 tglobaladdr:$dst)>;469def : Pat<(Xtensa_call (i32 texternalsym:$dst)),470 (CALL0 texternalsym:$dst)>;471def : Pat<(Xtensa_call AR:$dst),472 (CALLX0 AR:$dst)>;473 474let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Size = 3 in {475 def BR_JT: Pseudo<(outs), (ins AR:$s, i32imm:$jt),476 "!br_jt_p, $s, $jt",477 [(Xtensa_brjt AR:$s, tjumptable:$jt)]>;478}479 480//===----------------------------------------------------------------------===//481// Mem barrier instructions482//===----------------------------------------------------------------------===//483 484def MEMW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),485 "memw", []> {486 let r = 0x2;487 let t = 0x0c;488 let s = 0x0;489}490 491def EXTW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),492 "extw", []> {493 let r = 0x2;494 let s = 0x0;495 let t = 0xd;496 let hasSideEffects = 1;497}498 499def : Pat<(atomic_fence timm, timm), (MEMW)>;500 501//===----------------------------------------------------------------------===//502// Illegal instructions503//===----------------------------------------------------------------------===//504 505def ILL : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),506 "ill", []> {507 let m = 0x0;508 let n = 0x0;509 let r = 0;510 let s = 0;511}512 513//===----------------------------------------------------------------------===//514// Processor control instructions515//===----------------------------------------------------------------------===//516 517def DSYNC : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),518 "dsync", []> {519 let r = 0x2;520 let s = 0x0;521 let t = 0x3;522 let hasSideEffects = 1;523}524 525def ISYNC : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),526 "isync", []> {527 let r = 0x2;528 let s = 0x0;529 let t = 0x0;530 let hasSideEffects = 1;531}532 533def RSYNC : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),534 "rsync", []> {535 let r = 0x2;536 let s = 0x0;537 let t = 0x1;538 let hasSideEffects = 1;539}540 541def ESYNC : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),542 "esync", []> {543 let r = 0x2;544 let s = 0x0;545 let t = 0x2;546 let hasSideEffects = 1;547}548 549def NOP : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),550 "nop", []> {551 let r = 0x02;552 let s = 0x00;553 let t = 0x0f;554}555 556def WSR : RSR_Inst<0x00, 0x03, 0x01, (outs SR:$sr), (ins AR:$t),557 "wsr\t$t, $sr", []>;558 559def RSR : RSR_Inst<0x00, 0x03, 0x00, (outs AR:$t), (ins SR:$sr),560 "rsr\t$t, $sr", []>;561 562def XSR : RSR_Inst<0x00, 0x01, 0x06, (outs AR:$ard, SR:$srd), (ins AR:$t, SR:$sr),563 "xsr\t$t, $sr", []> {564 let Constraints = "$ard = $t, $srd = $sr";565}566 567//===----------------------------------------------------------------------===//568// User Registers read/write instructions569//===----------------------------------------------------------------------===//570 571def WUR : RRR_Inst<0x00, 0x03, 0x0F, (outs UR:$ur), (ins AR:$t),572 "wur\t$t, $ur", []> {573 bits<8> ur;574 575 let r = ur{7-4};576 let s = ur{3-0};577}578 579def RUR : RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur),580 "rur\t$r, $ur", [(set AR:$r, (Xtensa_rur UR:$ur))]> {581 bits<8> ur;582 583 let s = ur{7-4};584 let t = ur{3-0};585}586 587//===----------------------------------------------------------------------===//588// Stack allocation589//===----------------------------------------------------------------------===//590 591// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into592// a stack adjustment and the codegen must know that they may modify the stack593// pointer before prolog-epilog rewriting occurs.594let Defs = [SP], Uses = [SP] in {595 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),596 "#ADJCALLSTACKDOWN",597 [(Xtensa_callseq_start timm:$amt1, timm:$amt2)]>;598 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),599 "#ADJCALLSTACKUP",600 [(Xtensa_callseq_end timm:$amt1, timm:$amt2)]>;601}602 603//===----------------------------------------------------------------------===//604// Generic select instruction605//===----------------------------------------------------------------------===//606let usesCustomInserter = 1 in {607 def SELECT : Pseudo<(outs AR:$dst), (ins AR:$lhs, AR:$rhs, AR:$t, AR:$f, i32imm:$cond),608 "!select $dst, $lhs, $rhs, $t, $f, $cond",609 [(set i32:$dst, (Xtensa_select_cc i32:$lhs, i32:$rhs, i32:$t, i32:$f, imm:$cond))]>;610}611 612//===----------------------------------------------------------------------===//613// Code Density instructions614//===----------------------------------------------------------------------===//615 616class ArithLogic_RRRN<bits<4> oper0, string instrAsm,617 SDPatternOperator opNode, bit isComm = 0>618 : RRRN_Inst<oper0, (outs AR:$r), (ins AR:$s, AR:$t),619 instrAsm#"\t$r, $s, $t",620 [(set AR:$r, (opNode AR:$s, AR:$t))]>, Requires<[HasDensity]> {621 let isCommutable = isComm;622 let isReMaterializable = 0;623}624 625def ADD_N : ArithLogic_RRRN<0x0a, "add.n", add, 1>;626 627def ADDI_N : RRRN_Inst<0x0B, (outs AR:$r), (ins AR:$s, imm1n_15:$imm),628 "addi.n\t$r, $s, $imm",629 [(set AR:$r, (add AR:$s, imm1n_15:$imm))]>, Requires<[HasDensity]> {630 bits<4> imm;631 632 let t = imm;633}634 635// Conditional branch instructions.636let isBranch = 1, isTerminator = 1 in {637 def BEQZ_N : RI6_Inst<0xC, 0x1, 0x0, (outs), (ins AR:$s, brtarget:$target),638 "beqz.n\t$s, $target", []>, Requires<[HasDensity]> {639 bits<6> target;640 641 let imm6 = target;642 }643 644 def BNEZ_N : RI6_Inst<0xC, 0x1, 0x1, (outs), (ins AR:$s, brtarget:$target),645 "bnez.n\t$s, $target", []>, Requires<[HasDensity]> {646 bits<6> target;647 648 let imm6 = target;649 }650}651 652def ILL_N : RRRN_Inst<0x0D, (outs), (ins),653 "ill.n", []>, Requires<[HasDensity]> {654 let r = 0xF;655 let s = 0x0;656 let t = 0x6;657}658 659def MOV_N : RRRN_Inst<0x0D, (outs AR:$t), (ins AR:$s),660 "mov.n\t$t, $s", []>, Requires<[HasDensity]> {661 let r = 0;662}663 664def : InstAlias<"mov\t $t, $s", (OR AR:$t, AR:$s, AR:$s)>;665 666def MOVI_N : RI7_Inst<0xc, 0x0, (outs AR:$s), (ins imm32n_95:$imm7),667 "movi.n\t$s, $imm7",668 [(set AR:$s, imm32n_95:$imm7)]>, Requires<[HasDensity]>;669 670def : InstAlias<"_movi.n\t$s, $imm7", (MOVI_N AR:$s, imm32n_95:$imm7)>;671 672def NOP_N : RRRN_Inst<0x0D, (outs), (ins),673 "nop.n", []>, Requires<[HasDensity]> {674 let r = 0xF;675 let s = 0x0;676 let t = 0x3;677}678 679// Load instruction680let mayLoad = 1, usesCustomInserter = 1 in {681 def L32I_N : RRRN_Inst<0x8, (outs AR:$t), (ins mem32n:$addr),682 "l32i.n\t$t, $addr", []>, Requires<[HasDensity]> {683 bits<8> addr;684 685 let r{3-0} = addr{7-4};686 let s{3-0} = addr{3-0};687 }688}689 690// Store instruction691let mayStore = 1, usesCustomInserter = 1 in {692 def S32I_N : RRRN_Inst<0x9, (outs), (ins AR:$t, mem32n:$addr),693 "s32i.n\t$t, $addr", []>, Requires<[HasDensity]> {694 bits<8> addr;695 696 let r{3-0} = addr{7-4};697 let s{3-0} = addr{3-0};698 }699}700 701//Return instruction702let isReturn = 1, isTerminator = 1,703 isBarrier = 1, Uses = [A0] in {704 def RET_N : RRRN_Inst<0x0D, (outs), (ins),705 "ret.n", [(Xtensa_ret)]>,706 Requires<[HasDensity]> {707 let r = 0x0F;708 let s = 0;709 let t = 0;710 }711}712 713//===----------------------------------------------------------------------===//714// Windowed instructions715//===----------------------------------------------------------------------===//716 717def ENTRY : BRI12_Inst<0x06, 0x3, 0x0, (outs), (ins AR:$s, entry_imm12:$imm),718 "entry\t$s, $imm", []>, Requires<[HasWindowed]> {719 bits<15> imm;720 721 let imm12{11-0} = imm{14-3};722 let Defs = [SP];723}724 725let isCall = 1, Defs = [A0] in {726 foreach i = {1,2,3} in {727 defvar I = !mul(4, i);728 729 def CALL#I# : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),730 "call"#I#"\t$offset", []>, Requires<[HasWindowed]> {731 let n = i;732 }733 734 def CALLX#I# : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),735 "callx"#I#"\t$s", []>, Requires<[HasWindowed]> {736 let m = 0x3;737 let n = i;738 let r = 0;739 }740 }741}742 743// Windowed call patterns. Currently rotation744// window by 8 is implemented.745def : Pat<(Xtensa_callw8 (i32 tglobaladdr:$dst)),746 (CALL8 tglobaladdr:$dst)>;747def : Pat<(Xtensa_callw8 (i32 texternalsym:$dst)),748 (CALL8 texternalsym:$dst)>;749def : Pat<(Xtensa_callw8 AR:$dst),750 (CALLX8 AR:$dst)>;751 752def MOVSP : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins AR:$s),753 "movsp\t$t, $s", []>, Requires<[HasWindowed]> {754 let r = 0x01;755}756 757// Use this pseudo operation instead of getCopyToReg function to758// update SP register.759let usesCustomInserter = 1, Defs = [SP], Predicates = [HasWindowed] in {760 def MOVSP_P : Pseudo<(outs), (ins AR:$s),761 "!movsp_p\tsp, $s", [(Xtensa_movsp AR:$s)]>;762}763 764let isReturn = 1, isTerminator = 1,765 isBarrier = 1, Uses = [A0] in {766 def RETW_N : RRRN_Inst<0x0D, (outs), (ins),767 "retw.n", [(Xtensa_retw)]>,768 Requires<[HasWindowed, HasDensity]> {769 let r = 0x0F;770 let s = 0;771 let t = 1;772 }773 774 def RETW : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),775 "retw", [(Xtensa_retw)]>,776 Requires<[HasWindowed]> {777 let m = 0x2;778 let n = 0x1;779 let s = 0;780 let r = 0;781 }782}783 784def : InstAlias<"_retw", (RETW)>;785def : InstAlias<"_retw.n", (RETW_N)>;786 787def S32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm),788 "s32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> {789 bits<6> imm;790 791 let r = imm{5-2};792 let imm4 = 0x4;793 let mayStore = 1;794}795 796def L32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm),797 "l32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> {798 bits<6> imm;799 800 let r = imm{5-2};801 let imm4 = 0x0;802 let mayLoad = 1;803}804 805def RFWU : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),806 "rfwu", []>, Requires<[HasWindowed]> {807 bits<4> imm;808 809 let r = 0x3;810 let s = 0x5;811 let t = 0x0;812}813 814def RFWO : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),815 "rfwo", []>, Requires<[HasWindowed]> {816 bits<4> imm;817 818 let r = 0x3;819 let s = 0x4;820 let t = 0x0;821}822 823def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm),824 "rotw\t$imm", []>, Requires<[HasWindowed]> {825 bits<4> imm;826 827 let r = 0x8;828 let s = 0x0;829 let t = imm{3-0};830}831 832//===----------------------------------------------------------------------===//833// Boolean Instructions834//===----------------------------------------------------------------------===//835 836def ALL4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),837 "all4\t$t, $s", []>, Requires<[HasBoolean]> {838 let r = 0x9;839}840 841def ALL8 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),842 "all8\t$t, $s", []>, Requires<[HasBoolean]> {843 let r = 0xB;844}845 846def ANDB : RRR_Inst<0x00, 0x02, 0x00, (outs BR:$r), (ins BR:$s, BR:$t),847 "andb\t$r, $s, $t", []>, Requires<[HasBoolean]>;848def ANDBC : RRR_Inst<0x00, 0x02, 0x01, (outs BR:$r), (ins BR:$s, BR:$t),849 "andbc\t$r, $s, $t", []>, Requires<[HasBoolean]>;850def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t),851 "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>;852def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t),853 "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>;854def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t),855 "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>;856 857def ANY4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),858 "any4\t$t, $s", []>, Requires<[HasBoolean]> {859 let r = 0x8;860}861 862def ANY8 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),863 "any8\t$t, $s", []>, Requires<[HasBoolean]> {864 let r = 0xA;865}866 867let isBranch = 1, isTerminator = 1, Predicates = [HasBoolean] in {868 def BT : RRI8_Inst<0x06, (outs), (ins BR:$b, brtarget:$target),869 "bt\t$b, $target", []> {870 bits<8> target;871 bits<4> b;872 873 let r = 0x1;874 let s = b;875 let t = 0x7;876 let imm8 = target;877 }878 879 def BF : RRI8_Inst<0x06, (outs), (ins BR:$b, brtarget:$target),880 "bf\t$b, $target", []> {881 bits<8> target;882 bits<4> b;883 884 let r = 0x0;885 let s = b;886 let t = 0x7;887 let imm8 = target;888 }889}890 891def : InstAlias<"_BT\t$b, $target", (BT BR:$b, brtarget:$target)>;892def : InstAlias<"_BF\t$b, $target", (BF BR:$b, brtarget:$target)>;893 894let Constraints = "$dr = $r,@earlyclobber $dr" in {895 def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t),896 "movf\t$r, $s, $t", []>, Requires<[HasBoolean]>;897 898 def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t),899 "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>;900}901 902//===----------------------------------------------------------------------===//903// SEXT Instruction904//===----------------------------------------------------------------------===//905 906def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm),907 "sext\t$r, $s, $imm", []>, Requires<[HasSEXT]> {908 bits<4> imm;909 910 let t = imm;911}912 913def : Pat<(i32 (sext_inreg AR:$s, i8)), (SEXT AR:$s, (i32 7))>;914def : Pat<(i32 (sext_inreg AR:$s, i16)), (SEXT AR:$s, (i32 15))>;915 916//===----------------------------------------------------------------------===//917// CLAMPS Instruction918//===----------------------------------------------------------------------===//919 920def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm),921 "clamps\t$r, $s, $imm", []>, Requires<[HasCLAMPS]> {922 bits<4> imm;923 924 let t = imm;925}926 927//===----------------------------------------------------------------------===//928// NSA Instructions929//===----------------------------------------------------------------------===//930 931def NSA : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s),932 "nsa\t$t, $s", []>, Requires<[HasNSA]> {933 let r = 0xE;934}935 936def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s),937 "nsau\t$t, $s",938 [(set AR:$t, (ctlz AR:$s))]>, Requires<[HasNSA]> {939 let r = 0xF;940}941 942//===----------------------------------------------------------------------===//943// MINMAX Instructions944//===----------------------------------------------------------------------===//945 946let Predicates = [HasMINMAX] in {947 def MIN : ArithLogic_RRR<0x04, 0x03, "min", smin, 1>;948 def MAX : ArithLogic_RRR<0x05, 0x03, "max", smax, 1>;949 def MINU : ArithLogic_RRR<0x06, 0x03, "minu", umin, 1>;950 def MAXU : ArithLogic_RRR<0x07, 0x03, "maxu", umax, 1>;951}952 953//===----------------------------------------------------------------------===//954// Loop Instructions955//===----------------------------------------------------------------------===//956 957def LOOP : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target),958 "loop\t$s, $target", []>, Requires<[HasLoop]> {959 bits<8> target;960 961 let r = 0x08;962 let t = 0x07;963 let imm8 = target;964}965 966def : InstAlias<"_loop\t$s, $target", (LOOP AR:$s, ltarget:$target)>;967 968def LOOPGTZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target),969 "loopgtz\t$s, $target", []>, Requires<[HasLoop]> {970 bits<8> target;971 972 let r = 0x0A;973 let t = 0x07;974 let imm8 = target;975}976 977def : InstAlias<"_loopgtz\t$s, $target", (LOOPGTZ AR:$s, ltarget:$target)>;978 979def LOOPNEZ : RRI8_Inst<0x06, (outs), (ins AR:$s, ltarget:$target),980 "loopnez\t$s, $target", []>, Requires<[HasLoop]> {981 bits<8> target;982 983 let r = 0x09;984 let t = 0x07;985 let imm8 = target;986}987 988def : InstAlias<"_loopnez\t$s, $target", (LOOPNEZ AR:$s, ltarget:$target)>;989 990//===----------------------------------------------------------------------===//991// Mul16 Instructions992//===----------------------------------------------------------------------===//993 994let Predicates = [HasMul16] in {995 def MUL16S : RRR_Inst<0x00, 0x01, 0x0D, (outs AR:$r), (ins AR:$s, AR:$t),996 "mul16s\t$r, $s, $t", []>;997 def MUL16U : RRR_Inst<0x00, 0x01, 0x0C, (outs AR:$r), (ins AR:$s, AR:$t),998 "mul16u\t$r, $s, $t", []>;999}1000 1001//===----------------------------------------------------------------------===//1002// Mul32 Instructions1003//===----------------------------------------------------------------------===//1004 1005def MULL : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>;1006def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>;1007def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>;1008 1009//===----------------------------------------------------------------------===//1010// Div32 Instructions1011//===----------------------------------------------------------------------===//1012 1013let Predicates = [HasDiv32] in {1014 def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>;1015 def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>;1016 def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>;1017 def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;1018}1019 1020//===----------------------------------------------------------------------===//1021// Floating-Point Instructions1022//===----------------------------------------------------------------------===//1023 1024class FPArith_RRR<bits<4> oper2, bits<4> oper1, string instrAsm,1025 SDPatternOperator opNode, bit isComm = 0>1026 : RRR_Inst<0x00, oper1, oper2, (outs FPR:$r), (ins FPR:$s, FPR:$t),1027 instrAsm#"\t$r, $s, $t",1028 [(set FPR:$r, (opNode FPR:$s, FPR:$t))]> {1029 let isCommutable = isComm;1030 let isReMaterializable = 0;1031 let Predicates = [HasSingleFloat];1032}1033 1034def ADD_S : FPArith_RRR<0x00, 0x0A, "add.s", fadd, 1>;1035def SUB_S : FPArith_RRR<0x01, 0x0A, "sub.s", fsub>;1036def MUL_S : FPArith_RRR<0x02, 0x0A, "mul.s", fmul, 1>;1037 1038// FP load instructions1039let mayLoad = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in {1040 def LSI : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr),1041 "lsi\t$t, $addr", []> {1042 bits<12> addr;1043 1044 let r = 0x00;1045 let imm8{7-0} = addr{11-4};1046 let s{3-0} = addr{3-0};1047 }1048 1049 def LSIP : RRI8_Inst<0x03, (outs FPR:$t), (ins mem32:$addr),1050 "lsip\t$t, $addr", []> {1051 bits<12> addr;1052 1053 let r = 0x08;1054 let imm8{7-0} = addr{11-4};1055 let s{3-0} = addr{3-0};1056 }1057 1058 def LSX : RRR_Inst<0x00, 0x08, 0x00, (outs), (ins FPR:$r, AR:$s, AR:$t),1059 "lsx\t$r, $s, $t", []>;1060 1061 def LSXP : RRR_Inst<0x00, 0x08, 0x01, (outs), (ins FPR:$r, AR:$s, AR:$t),1062 "lsxp\t$r, $s, $t", []>;1063}1064 1065def : Pat<(f32 (load addr_ish4:$addr)), (f32 (LSI mem32:$addr))>;1066 1067// FP store instructions1068let mayStore = 1, usesCustomInserter = 1, Predicates = [HasSingleFloat] in {1069 def SSI : RRI8_Inst<0x03, (outs), (ins FPR:$t, mem32:$addr),1070 "ssi\t$t, $addr", []> {1071 bits<12> addr;1072 1073 let r = 0x04;1074 let imm8{7-0} = addr{11-4};1075 let s{3-0} = addr{3-0};1076 }1077 1078 def SSIP : RRI8_Inst<0x03, (outs), (ins FPR:$t, mem32:$addr),1079 "ssip\t$t, $addr", []> {1080 bits<12> addr;1081 1082 let r = 0x0C;1083 let imm8{7-0} = addr{11-4};1084 let s{3-0} = addr{3-0};1085 }1086 1087 def SSX: RRR_Inst<0x00, 0x08, 0x04, (outs), (ins FPR:$r, AR:$s, AR:$t),1088 "ssx\t$r, $s, $t", []>;1089 1090 def SSXP: RRR_Inst<0x00, 0x08, 0x05, (outs), (ins FPR:$r, AR:$s, AR:$t),1091 "ssxp\t$r, $s, $t", []>;1092}1093 1094def : Pat<(store FPR:$t, addr_ish4:$addr), (SSI FPR:$t, mem32:$addr)>;1095 1096// FP compare instructions1097let isCompare = 1, Predicates = [HasSingleFloat] in {1098 class FCompare <bits<4> oper2, bits<4> oper1, string instrAsm,1099 SDPatternOperator opNode, bit isComm = 0>1100 : RRR_Inst<0x00, oper1, oper2, (outs BR:$r), (ins FPR:$s, FPR:$t),1101 instrAsm#"\t$r, $s, $t",1102 [(set BR:$r, (opNode FPR:$s, FPR:$t))]> {1103 let isCommutable = isComm;1104 let isReMaterializable = 0;1105 let Predicates = [HasSingleFloat];1106 }1107}1108 1109def OEQ_S : FCompare<0x02, 0x0b, "oeq.s", Xtensa_cmpoeq, 1>;1110def OLT_S : FCompare<0x04, 0x0b, "olt.s", Xtensa_cmpolt, 0>;1111def OLE_S : FCompare<0x06, 0x0b, "ole.s", Xtensa_cmpole, 0>;1112 1113def UEQ_S : FCompare<0x03, 0x0b, "ueq.s", Xtensa_cmpueq, 1>;1114def ULT_S : FCompare<0x05, 0x0b, "ult.s", Xtensa_cmpult, 0>;1115def ULE_S : FCompare<0x07, 0x0b, "ule.s", Xtensa_cmpule, 0>;1116def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>;1117 1118def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1119 "abs.s\t$r, $s",1120 [(set FPR:$r, (fabs FPR:$s))]>, Requires<[HasSingleFloat]> {1121 let t = 0x01;1122}1123 1124def : Pat<(fabs FPR:$s), (ABS_S $s)>;1125 1126def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1127 "addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1128 let t = 0x0E;1129}1130 1131def ADDEXPM_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1132 "addexpm.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1133 let t = 0x0F;1134}1135 1136def CEIL_S : RRR_Inst<0x00, 0x0A, 0x0B, (outs AR:$r), (ins FPR:$s, uimm4:$imm),1137 "ceil.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1138 bits<4> imm;1139 1140 let t = imm;1141}1142 1143def CONST_S : RRR_Inst<0x00, 0x0a, 0x0f, (outs FPR:$r), (ins uimm4:$imm),1144 "const.s\t$r, $imm", []>, Requires<[HasSingleFloat]> {1145 bits<4> imm;1146 1147 let t = 0x03;1148 let s = imm{3-0};1149}1150 1151def DIV0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1152 "div0.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1153 let t = 0x7;1154}1155 1156def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t),1157 "divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;1158 1159def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm),1160 "float.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1161 bits<4> imm;1162 1163 let t = imm;1164}1165 1166def : Pat<(f32 (sint_to_fp AR:$s)), (FLOAT_S AR:$s, 0)>;1167 1168def FLOOR_S : RRR_Inst<0x00, 0x0A, 0x0A, (outs AR:$r), (ins FPR:$s, uimm4:$imm),1169 "floor.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1170 bits<4> imm;1171 1172 let t = imm;1173}1174 1175def MADDN_S : RRR_Inst<0x00, 0x0A, 0x06, (outs FPR:$r), (ins FPR:$s, FPR:$t),1176 "maddn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]> {1177 let isCommutable = 0;1178}1179 1180// FP multipy-add1181def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t),1182 "madd.s\t$r, $s, $t",1183 [(set FPR:$r, (Xtensa_madd FPR:$a, FPR:$s, FPR:$t))]>,1184 Requires<[HasSingleFloat]> {1185 let isCommutable = 0;1186 let isReMaterializable = 0;1187 let Constraints = "$r = $a";1188}1189 1190// fmadd: r1 * r2 + r31191def : Pat<(fma FPR:$r1, FPR:$r2, FPR:$r3),1192 (MADD_S $r3, $r1, $r2)>;1193 1194def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1195 "mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1196 let t = 0x0D;1197}1198 1199def MKSADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1200 "mksadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1201 let t = 0x0C;1202}1203 1204// FP move instructions1205def MOV_S : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins FPR:$s),1206 "mov.s\t$r, $s",1207 [(set FPR:$r, (Xtensa_movs FPR:$s))]>, Requires<[HasSingleFloat]> {1208 let t = 0x00;1209}1210 1211def MOVEQZ_S : RRR_Inst<0x00, 0x0B, 0x08, (outs FPR:$r), (ins FPR:$s, AR:$t),1212 "moveqz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;1213 1214def MOVF_S : RRR_Inst<0x00, 0x0B, 0x0C, (outs FPR:$r), (ins FPR:$s, BR:$t),1215 "movf.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>;1216 1217def MOVGEZ_S : RRR_Inst<0x00, 0x0B, 0x0B, (outs FPR:$r), (ins FPR:$s, AR:$t),1218 "movgez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;1219 1220def MOVLTZ_S : RRR_Inst<0x00, 0x0B, 0x0A, (outs FPR:$r), (ins FPR:$s, AR:$t),1221 "movltz.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;1222 1223def MOVNEZ_S : RRR_Inst<0x00, 0x0B, 0x09, (outs FPR:$r), (ins FPR:$s, AR:$t),1224 "movnez.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;1225 1226def MOVT_S : RRR_Inst<0x00, 0x0B, 0x0D, (outs FPR:$r), (ins FPR:$s, BR:$t),1227 "movt.s\t$r, $s, $t", []>, Requires<[HasBoolean, HasSingleFloat]>;1228 1229// FP multipy-sub1230def MSUB_S : RRR_Inst<0x00, 0x0A, 0x05, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:$t),1231 "msub.s\t$r, $s, $t",1232 [(set FPR:$r, (Xtensa_msub FPR:$a, FPR:$s, FPR:$t))]>, Requires<[HasSingleFloat]> {1233 let isCommutable = 0;1234 let isReMaterializable = 0;1235 let Constraints = "$r = $a";1236}1237 1238def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1239 "nexp01.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1240 let t = 0x0B;1241}1242 1243def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1244 "neg.s\t$r, $s",1245 [(set FPR:$r, (fneg FPR:$s))]>, Requires<[HasSingleFloat]> {1246 let t = 0x06;1247}1248 1249def RECIP0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1250 "recip0.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1251 let t = 0x08;1252}1253 1254def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s),1255 "rfr\t$r, $s",1256 [(set AR:$r, (bitconvert FPR:$s))]>, Requires<[HasSingleFloat]> {1257 let t = 0x04;1258}1259 1260def ROUND_S : RRR_Inst<0x00, 0x0A, 0x08, (outs AR:$r), (ins FPR:$s, uimm4:$imm),1261 "round.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1262 bits<4> imm;1263 1264 let t = imm;1265}1266 1267def RSQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1268 "rsqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1269 let t = 0x0A;1270}1271 1272def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),1273 "sqrt0.s\t$r, $s", []>, Requires<[HasSingleFloat]> {1274 let t = 0x09;1275}1276 1277def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s, uimm4:$imm),1278 "trunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1279 bits<4> imm;1280 1281 let t = imm;1282}1283 1284def : Pat<(i32 (fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>;1285 1286def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm),1287 "ufloat.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1288 bits<4> imm;1289 1290 let t = imm;1291}1292 1293def : Pat<(f32 (uint_to_fp AR:$s)), (UFLOAT_S AR:$s, 0)>;1294 1295def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm),1296 "utrunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {1297 bits<4> imm;1298 1299 let t = imm;1300}1301 1302def : Pat<(i32 (fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>;1303 1304def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s),1305 "wfr\t$r, $s",1306 [(set FPR:$r, (bitconvert AR:$s))]>, Requires<[HasSingleFloat]> {1307 let t = 0x05;1308}1309 1310let AddedComplexity = 10 in1311def : Pat<(f32 (load (Xtensa_pcrel_wrapper tconstpool:$in))),1312 (WFR (L32R tconstpool:$in))>;1313 1314//===----------------------------------------------------------------------===//1315// SelectCC and BranchCC instructions with FP operands1316//===----------------------------------------------------------------------===//1317 1318let usesCustomInserter = 1, Predicates = [HasSingleFloat] in {1319 def SELECT_CC_INT_FP : Pseudo<(outs FPR:$dst), (ins AR:$lhs, AR:$rhs, FPR:$t, FPR:$f, i32imm:$cond),1320 "!select_cc_int_fp $dst, $lhs, $rhs, $t, $f, $cond",1321 [(set FPR:$dst, (Xtensa_select_cc AR:$lhs, AR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>;1322 def SELECT_CC_FP_INT : Pseudo<(outs AR:$dst), (ins FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, i32imm:$cond, i32imm:$brkind),1323 "!select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond, $brkind",1324 [(set AR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, imm:$cond, imm:$brkind))]>;1325 def SELECT_CC_FP_FP : Pseudo<(outs FPR:$dst), (ins FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, i32imm:$cond, i32imm:$brkind),1326 "!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond, $brkind",1327 [(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond, imm:$brkind))]>;1328}1329 1330let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1, Predicates = [HasSingleFloat] in {1331 def BRCC_FP : Pseudo<(outs), (ins i32imm:$cond, FPR:$lhs, FPR:$rhs, brtarget:$target),1332 "!brcc_fp $cond, $lhs, $rhs, $target", []>;1333}1334 1335def cond_as_i32imm : SDNodeXForm<cond, [{1336 return CurDAG->getTargetConstant(N->get(), SDLoc(N), MVT::i32);1337}]>;1338 1339def : Pat<(brcc cond:$cond, FPR:$s, FPR:$t, bb:$target),1340 (BRCC_FP (cond_as_i32imm $cond), FPR:$s, FPR:$t, bb:$target)>;1341 1342//===----------------------------------------------------------------------===//1343// Region Protection feature instructions1344//===----------------------------------------------------------------------===//1345 1346let Predicates = [HasRegionProtection] in {1347 def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),1348 "idtlb\t$s", []> {1349 let r = 0xC;1350 let t = 0x0;1351 }1352 1353 def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),1354 "iitlb\t$s", []> {1355 let r = 0x4;1356 let t = 0x0;1357 }1358 1359 def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1360 "pdtlb\t$t, $s", []> {1361 let r = 0xD;1362 }1363 1364 def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1365 "pitlb\t$t, $s", []> {1366 let r = 0x5;1367 }1368 1369 def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1370 "rdtlb0\t$t, $s", []> {1371 let r = 0xB;1372 }1373 1374 def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1375 "rdtlb1\t$t, $s", []> {1376 let r = 0xF;1377 }1378 1379 def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1380 "ritlb0\t$t, $s", []> {1381 let r = 0x3;1382 }1383 1384 def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1385 "ritlb1\t$t, $s", []> {1386 let r = 0x7;1387 }1388 1389 def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1390 "wdtlb\t$t, $s", []> {1391 let r = 0xE;1392 }1393 1394 def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),1395 "witlb\t$t, $s", []> {1396 let r = 0x6;1397 }1398}1399 1400//===----------------------------------------------------------------------===//1401// Debug instructions1402//===----------------------------------------------------------------------===//1403 1404let isBarrier = 1, isTerminator = 1 in {1405 def BREAK : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$s, uimm4:$t),1406 "break\t$s, $t", []>, Requires<[HasDebug]> {1407 let r = 0x04;1408 }1409 1410 def BREAK_N : RRRN_Inst<0x0D, (outs), (ins uimm4:$imm),1411 "break.n\t$imm", []>, Requires<[HasDensity, HasDebug]> {1412 bits<4> imm;1413 1414 let r = 0xf;1415 let s = imm;1416 let t = 0x2;1417 }1418}1419 1420def : InstAlias<"_break.n\t$imm", (BREAK_N uimm4:$imm)>;1421 1422def : Pat<(trap), (BREAK (i32 1), (i32 15))>;1423 1424// Load instruction1425def LDDR32P : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$s), (ins),1426 "lddr32.p\t$s", []>, Requires<[HasDebug]> {1427 let r = 0x7;1428 let t = 0xe;1429 let mayLoad = 1;1430}1431 1432// Store instruction1433def SDDR32P : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),1434 "sddr32.p\t$s", []>, Requires<[HasDebug]> {1435 let r = 0x7;1436 let t = 0xf;1437 let mayStore = 1;1438}1439 1440//===----------------------------------------------------------------------===//1441// Exception feature instructions1442//===----------------------------------------------------------------------===//1443 1444def EXCW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),1445 "excw", []>, Requires<[HasException]> {1446 let r = 0x2;1447 let s = 0x0;1448 let t = 0x8;1449}1450 1451def RFDE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),1452 "rfde", []>, Requires<[HasException]> {1453 let r = 0x3;1454 let s = 0x2;1455 let t = 0x0;1456}1457 1458 1459def RFE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),1460 "rfe", []>, Requires<[HasException]> {1461 let r = 0x3;1462 let s = 0x0;1463 let t = 0x0;1464}1465 1466def SYSCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),1467 "syscall", []>, Requires<[HasException]> {1468 let r = 0x5;1469 let s = 0x0;1470 let t = 0x0;1471}1472 1473//===----------------------------------------------------------------------===//1474// Interrupt feature instructions1475//===----------------------------------------------------------------------===//1476 1477def RSIL : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins uimm4:$imm),1478 "rsil\t$t, $imm", []>, Requires<[HasInterrupt]> {1479 bits<4> imm;1480 1481 let r = 0x6;1482 let s = imm{3-0};1483}1484 1485def WAITI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm),1486 "waiti\t$imm", []>, Requires<[HasInterrupt]> {1487 bits<4> imm;1488 1489 let r = 0x7;1490 let s = imm{3-0};1491 let t = 0;1492}1493 1494def RFI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm),1495 "rfi\t$imm", []>, Requires<[HasHighPriInterrupts]> {1496 bits<4> imm;1497 1498 let r = 0x3;1499 let s = imm{3-0};1500 let t = 0x1;1501}1502 1503//===----------------------------------------------------------------------===//1504// S32C1I1505//===----------------------------------------------------------------------===//1506 1507let mayStore = 1, mayLoad = 1, Predicates = [HasS32C1I] in {1508 def S32C1I : RRI8_Inst<0x02, (outs AR:$a), (ins AR:$t, mem32:$addr),1509 "s32c1i\t$t, $addr", []> {1510 bits<12> addr;1511 1512 let r = 0x0e;1513 let Uses = [SCOMPARE1];1514 let Constraints = "$a = $t";1515 let imm8{7-0} = addr{11-4};1516 let s{3-0} = addr{3-0};1517 }1518}1519 1520//===----------------------------------------------------------------------===//1521// Atomic patterns1522//===----------------------------------------------------------------------===//1523 1524// Atomic load/store are available under both +s32c1i and +force-atomics.1525// Fences will be inserted for atomic load/stores according to the logic in1526// XtensaTargetLowering.1527let Predicates = [HasAtomicLdSt] in {1528 def : Pat<(i32 (atomic_load_8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;1529 def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;1530 def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;1531 1532 def : Pat<(atomic_store_8 AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;1533 def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;1534 def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;1535}1536 1537let usesCustomInserter = 1, Predicates = [HasS32C1I] in {1538 def ATOMIC_CMP_SWAP_32_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap),1539 "!atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap",1540 [(set AR:$dst, (atomic_cmp_swap_i32 AR:$ptr, AR:$cmp, AR:$swap))]>;1541}1542 1543//===----------------------------------------------------------------------===//1544// DSP Instructions1545//===----------------------------------------------------------------------===//1546include "XtensaDSPInstrInfo.td"1547