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1//===- XtensaRegisterInfo.td - Xtensa Register defs --------*- tablegen -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10 11//===----------------------------------------------------------------------===//12// Class definitions.13//===----------------------------------------------------------------------===//14 15class XtensaReg<string n> : Register<n> {16 let Namespace = "Xtensa";17}18 19class XtensaRegWithSubRegs<string n, list<Register> subregs>20 : RegisterWithSubRegs<n, subregs> {21 let Namespace = "Xtensa";22}23 24//===----------------------------------------------------------------------===//25// General-purpose registers26//===----------------------------------------------------------------------===//27 28// Xtensa general purpose regs29class ARReg<bits<4> num, string n, list<string> alt = []> : XtensaReg<n> {30 let HWEncoding{3-0} = num;31 let AltNames = alt;32}33 34// Return Address35def A0 : ARReg<0, "a0">, DwarfRegNum<[0]>;36 37// Stack Pointer (callee-saved)38def SP : ARReg<1, "a1", ["sp"]>, DwarfRegNum<[1]>;39 40// Function Arguments41def A2 : ARReg<2, "a2">, DwarfRegNum<[2]>;42def A3 : ARReg<3, "a3">, DwarfRegNum<[3]>;43def A4 : ARReg<4, "a4">, DwarfRegNum<[4]>;44def A5 : ARReg<5, "a5">, DwarfRegNum<[5]>;45def A6 : ARReg<6, "a6">, DwarfRegNum<[6]>;46def A7 : ARReg<7, "a7">, DwarfRegNum<[7]>;47 48// Static Chain49def A8 : ARReg<8, "a8">, DwarfRegNum<[8]>;50 51def A9 : ARReg<9, "a9">, DwarfRegNum<[9]>;52def A10 : ARReg<10, "a10">, DwarfRegNum<[10]>;53def A11 : ARReg<11, "a11">, DwarfRegNum<[11]>;54 55// Callee-saved56def A12 : ARReg<12, "a12">, DwarfRegNum<[12]>;57def A13 : ARReg<13, "a13">, DwarfRegNum<[13]>;58def A14 : ARReg<14, "a14">, DwarfRegNum<[14]>;59 60// Stack-Frame Pointer (optional) - Callee-Saved61def A15 : ARReg<15, "a15">, DwarfRegNum<[15]>;62 63// Register class with allocation order64def AR : RegisterClass<"Xtensa", [i32], 32, (add65 A8, A9, A10, A11, A12, A13, A14, A15,66 A7, A6, A5, A4, A3, A2, A0, SP)>;67 68//===----------------------------------------------------------------------===//69// Special-purpose registers70//===----------------------------------------------------------------------===//71class SRReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {72 let HWEncoding{7-0} = num;73 let AltNames = alt;74}75 76// Loop Option Registers77def LBEG : SRReg<0, "lbeg", ["LBEG", "0"]>;78def LEND : SRReg<1, "lend", ["LEND", "1"]>;79def LCOUNT : SRReg<2, "lcount", ["LCOUNT", "2"]>;80 81// Shift Amount Register82def SAR : SRReg<3, "sar", ["SAR","3"]>;83 84// Boolean Register85def BREG : SRReg<4, "br", ["BR","4"]>;86 87// Expected data value for S32C1I operation88def SCOMPARE1 : SRReg<12, "scompare1", ["SCOMPARE1", "12"]>;89 90// Literal base91def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;92 93// Windowed Register Option registers94def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;95def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;96 97// Instuction breakpoint enable register98def IBREAKENABLE : SRReg<96, "ibreakenable", ["IBREAKENABLE", "96"]>;99 100// Memory Control Register101def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;102 103// Atomic Operation Control104def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>;105 106def DDR : SRReg<104, "ddr", ["DDR", "104"]>;107 108// Instuction break address register 0109def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0", "128"]>;110 111// Instuction break address register 1112def IBREAKA1 : SRReg<129, "ibreaka1", ["IBREAKA1", "129"]>;113 114// Data break address register 0115def DBREAKA0 : SRReg<144, "dbreaka0", ["DBREAKA0", "144"]>;116 117// Data break address register 1118def DBREAKA1 : SRReg<145, "dbreaka1", ["DBREAKA1", "145"]>;119 120// Data breakpoint control register 0121def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0", "160"]>;122 123// Data breakpoint control register 1124def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1", "161"]>;125 126def CONFIGID0 : SRReg<176, "configid0", ["CONFIGID0", "176"]>;127 128// Exception PC1129def EPC1 : SRReg<177, "epc1", ["EPC1", "177"]>;130 131// Exception PC2132def EPC2 : SRReg<178, "epc2", ["EPC2", "178"]>;133 134// Exception PC3135def EPC3 : SRReg<179, "epc3", ["EPC3", "179"]>;136 137// Exception PC4138def EPC4 : SRReg<180, "epc4", ["EPC4", "180"]>;139 140// Exception PC5141def EPC5 : SRReg<181, "epc5", ["EPC5", "181"]>;142 143// Exception PC6144def EPC6 : SRReg<182, "epc6", ["EPC6", "182"]>;145 146// Exception PC7147def EPC7 : SRReg<183, "epc7", ["EPC7", "183"]>;148 149def DEPC : SRReg<192, "depc", ["DEPC", "192"]>;150def EPS2 : SRReg<194, "eps2", ["EPS2", "194"]>;151def EPS3 : SRReg<195, "eps3", ["EPS3", "195"]>;152def EPS4 : SRReg<196, "eps4", ["EPS4", "196"]>;153def EPS5 : SRReg<197, "eps5", ["EPS5", "197"]>;154def EPS6 : SRReg<198, "eps6", ["EPS6", "198"]>;155def EPS7 : SRReg<199, "eps7", ["EPS7", "199"]>;156 157def CONFIGID1 : SRReg<208, "configid1", ["CONFIGID1", "208"]>;158 159def EXCSAVE1 : SRReg<209, "excsave1", ["EXCSAVE1", "209"]>;160def EXCSAVE2 : SRReg<210, "excsave2", ["EXCSAVE2", "210"]>;161def EXCSAVE3 : SRReg<211, "excsave3", ["EXCSAVE3", "211"]>;162def EXCSAVE4 : SRReg<212, "excsave4", ["EXCSAVE4", "212"]>;163def EXCSAVE5 : SRReg<213, "excsave5", ["EXCSAVE5", "213"]>;164def EXCSAVE6 : SRReg<214, "excsave6", ["EXCSAVE6", "214"]>;165def EXCSAVE7 : SRReg<215, "excsave7", ["EXCSAVE7", "215"]>;166 167def CPENABLE : SRReg<224, "cpenable", ["CPENABLE", "224"]>;168 169// Interrupt enable mask register170def INTERRUPT : SRReg<226, "interrupt", ["INTERRUPT", "226"]>;171 172def INTSET : SRReg<226, "intset", ["INTSET"]>;173 174def INTCLEAR : SRReg<227, "intclear", ["INTCLEAR", "227"]>;175 176def INTENABLE : SRReg<228, "intenable", ["INTENABLE", "228"]>;177 178// Processor State179def PS : SRReg<230, "ps", ["PS", "230"]>;180 181def EXCCAUSE : SRReg<232, "exccause", ["EXCCAUSE", "232"]>;182 183// Cause of last debug exception register184def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE", "233"]>;185 186// Processor Clock Count Register187def CCOUNT : SRReg<234, "ccount", ["CCOUNT", "234"]>;188 189// Processor ID Register190def PRID : SRReg<235, "prid", ["PRID", "235"]>;191 192def ICOUNT : SRReg<236, "icount", ["ICOUNT", "236"]>;193def ICOUNTLEVEL : SRReg<237, "icountlevel", ["ICOUNTLEVEL", "237"]>;194def EXCVADDR : SRReg<238, "excvaddr", ["EXCVADDR", "238"]>;195 196// Cycle number to interrupt register 0197def CCOMPARE0 : SRReg<240, "ccompare0", ["CCOMPARE0", "240"]>;198 199// Cycle number to interrupt register 1200def CCOMPARE1 : SRReg<241, "ccompare1", ["CCOMPARE1", "241"]>;201 202// Cycle number to interrupt register 2203def CCOMPARE2 : SRReg<242, "ccompare2", ["CCOMPARE2", "242"]>;204 205// Vector base register206def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;207 208// Xtensa Miscellaneous SR209def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;210def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;211def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;212def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;213 214// MAC16 Option registers215def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;216def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;217def M0 : SRReg<32, "m0", ["M0", "32"]>;218def M1 : SRReg<33, "m1", ["M1", "33"]>;219def M2 : SRReg<34, "m2", ["M2", "34"]>;220def M3 : SRReg<35, "m3", ["M3", "35"]>;221 222def MR01 : RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>;223def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;224def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;225 226def SR : RegisterClass<"Xtensa", [i32], 32, (add227 LBEG, LEND, LCOUNT, SAR, BREG, SCOMPARE1, LITBASE, ACCLO, ACCHI, MR,228 WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1,229 DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5,230 EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2,231 EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTERRUPT, INTSET, INTCLEAR, INTENABLE,232 PS, VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0,233 CCOMPARE1, CCOMPARE2, MISC0, MISC1, MISC2, MISC3)>;234 235//===----------------------------------------------------------------------===//236// USER registers237//===----------------------------------------------------------------------===//238class URReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {239 let HWEncoding{7-0} = num;240 let AltNames = alt;241}242 243// Thread Pointer register244def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>;245 246def FCR : URReg<232, "fcr", ["FCR"]>;247def FSR : URReg<233, "fsr", ["FSR"]>;248 249// DFPAccel registers250def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>;251def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>;252def F64S : URReg<236, "f64s", ["F64S"]>;253 254def UR : RegisterClass<"Xtensa", [i32], 32, (add255 THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S)>;256 257//===----------------------------------------------------------------------===//258// Floating-Point registers259//===----------------------------------------------------------------------===//260 261// Xtensa Floating-Point regs262class FPReg<bits<4> num, string n> : XtensaReg<n> {263 let HWEncoding{3-0} = num;264}265 266def F0 : FPReg<0, "f0">, DwarfRegNum<[19]>;267def F1 : FPReg<1, "f1">, DwarfRegNum<[20]>;268def F2 : FPReg<2, "f2">, DwarfRegNum<[21]>;269def F3 : FPReg<3, "f3">, DwarfRegNum<[22]>;270def F4 : FPReg<4, "f4">, DwarfRegNum<[23]>;271def F5 : FPReg<5, "f5">, DwarfRegNum<[24]>;272def F6 : FPReg<6, "f6">, DwarfRegNum<[25]>;273def F7 : FPReg<7, "f7">, DwarfRegNum<[26]>;274def F8 : FPReg<8, "f8">, DwarfRegNum<[27]>;275def F9 : FPReg<9, "f9">, DwarfRegNum<[28]>;276def F10 : FPReg<10, "f10">, DwarfRegNum<[29]>;277def F11 : FPReg<11, "f11">, DwarfRegNum<[30]>;278def F12 : FPReg<12, "f12">, DwarfRegNum<[31]>;279def F13 : FPReg<13, "f13">, DwarfRegNum<[32]>;280def F14 : FPReg<14, "f14">, DwarfRegNum<[33]>;281def F15 : FPReg<15, "f15">, DwarfRegNum<[34]>;282 283// Floating-Point register class with allocation order284def FPR : RegisterClass<"Xtensa", [f32], 32, (add285 F8, F9, F10, F11, F12, F13, F14, F15,286 F7, F6, F5, F4, F3, F2, F1, F0)>;287 288//===----------------------------------------------------------------------===//289// Boolean registers290//===----------------------------------------------------------------------===//291class BReg<bits<4> num, string n> : XtensaReg<n> {292 let HWEncoding{3-0} = num;293}294 295foreach i = 0-15 in {296 def B#i : BReg<i, "b"#i>;297}298 299// Boolean register class300def BR : RegisterClass<"Xtensa", [v1i1], 8, (add B0, B1,301 B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15)> {302 let Size = 8;303}304