122 lines · cpp
1//===- XtensaTargetMachine.cpp - Define TargetMachine for Xtensa ----------===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// Implements the info about Xtensa target spec.12//13//===----------------------------------------------------------------------===//14 15#include "XtensaTargetMachine.h"16#include "TargetInfo/XtensaTargetInfo.h"17#include "XtensaMachineFunctionInfo.h"18#include "llvm/CodeGen/Passes.h"19#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"20#include "llvm/CodeGen/TargetPassConfig.h"21#include "llvm/MC/TargetRegistry.h"22#include "llvm/PassRegistry.h"23#include "llvm/Transforms/Scalar.h"24#include <optional>25 26using namespace llvm;27 28extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() {29 // Register the target.30 RegisterTargetMachine<XtensaTargetMachine> A(getTheXtensaTarget());31 PassRegistry &PR = *PassRegistry::getPassRegistry();32 initializeXtensaAsmPrinterPass(PR);33}34 35static Reloc::Model getEffectiveRelocModel(bool JIT,36 std::optional<Reloc::Model> RM) {37 if (!RM || JIT)38 return Reloc::Static;39 return *RM;40}41 42XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,43 StringRef CPU, StringRef FS,44 const TargetOptions &Options,45 std::optional<Reloc::Model> RM,46 std::optional<CodeModel::Model> CM,47 CodeGenOptLevel OL, bool JIT,48 bool IsLittle)49 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,50 getEffectiveRelocModel(JIT, RM),51 getEffectiveCodeModel(CM, CodeModel::Small), OL),52 TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {53 initAsmInfo();54}55 56XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,57 StringRef CPU, StringRef FS,58 const TargetOptions &Options,59 std::optional<Reloc::Model> RM,60 std::optional<CodeModel::Model> CM,61 CodeGenOptLevel OL, bool JIT)62 : XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}63 64const XtensaSubtarget *65XtensaTargetMachine::getSubtargetImpl(const Function &F) const {66 Attribute CPUAttr = F.getFnAttribute("target-cpu");67 Attribute FSAttr = F.getFnAttribute("target-features");68 69 auto CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;70 auto FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;71 72 auto &I = SubtargetMap[CPU + FS];73 if (!I) {74 // This needs to be done before we create a new subtarget since any75 // creation will depend on the TM and the code generation flags on the76 // function that reside in TargetOptions.77 resetTargetOptions(F);78 I = std::make_unique<XtensaSubtarget>(TargetTriple, CPU, FS, *this);79 }80 return I.get();81}82 83MachineFunctionInfo *XtensaTargetMachine::createMachineFunctionInfo(84 BumpPtrAllocator &Allocator, const Function &F,85 const TargetSubtargetInfo *STI) const {86 return XtensaMachineFunctionInfo::create<XtensaMachineFunctionInfo>(Allocator,87 F, STI);88}89 90namespace {91/// Xtensa Code Generator Pass Configuration Options.92class XtensaPassConfig : public TargetPassConfig {93public:94 XtensaPassConfig(XtensaTargetMachine &TM, PassManagerBase &PM)95 : TargetPassConfig(TM, PM) {}96 97 XtensaTargetMachine &getXtensaTargetMachine() const {98 return getTM<XtensaTargetMachine>();99 }100 101 bool addInstSelector() override;102 void addIRPasses() override;103 void addPreEmitPass() override;104};105} // end anonymous namespace106 107bool XtensaPassConfig::addInstSelector() {108 addPass(createXtensaISelDag(getXtensaTargetMachine(), getOptLevel()));109 return false;110}111 112void XtensaPassConfig::addIRPasses() {113 addPass(createAtomicExpandLegacyPass());114 TargetPassConfig::addIRPasses();115}116 117void XtensaPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }118 119TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {120 return new XtensaPassConfig(*this, PM);121}122