634 lines · cpp
1//===--- TargetDataLayout.cpp - Map Triple to LLVM data layout string -----===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "llvm/ADT/StringRef.h"10#include "llvm/Support/CommandLine.h"11#include "llvm/TargetParser/ARMTargetParser.h"12#include "llvm/TargetParser/Triple.h"13#include <cstring>14using namespace llvm;15 16static StringRef getManglingComponent(const Triple &T) {17 if (T.isOSBinFormatGOFF())18 return "-m:l";19 if (T.isOSBinFormatMachO())20 return "-m:o";21 if ((T.isOSWindows() || T.isUEFI()) && T.isOSBinFormatCOFF())22 return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";23 if (T.isOSBinFormatXCOFF())24 return "-m:a";25 return "-m:e";26}27 28static std::string computeARMDataLayout(const Triple &TT, StringRef ABIName) {29 auto ABI = ARM::computeTargetABI(TT, ABIName);30 std::string Ret;31 32 if (TT.isLittleEndian())33 // Little endian.34 Ret += "e";35 else36 // Big endian.37 Ret += "E";38 39 Ret += getManglingComponent(TT);40 41 // Pointers are 32 bits and aligned to 32 bits.42 Ret += "-p:32:32";43 44 // Function pointers are aligned to 8 bits (because the LSB stores the45 // ARM/Thumb state).46 Ret += "-Fi8";47 48 // ABIs other than APCS have 64 bit integers with natural alignment.49 if (ABI != ARM::ARM_ABI_APCS)50 Ret += "-i64:64";51 52 // We have 64 bits floats. The APCS ABI requires them to be aligned to 3253 // bits, others to 64 bits. We always try to align to 64 bits.54 if (ABI == ARM::ARM_ABI_APCS)55 Ret += "-f64:32:64";56 57 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others58 // to 64. We always ty to give them natural alignment.59 if (ABI == ARM::ARM_ABI_APCS)60 Ret += "-v64:32:64-v128:32:128";61 else if (ABI != ARM::ARM_ABI_AAPCS16)62 Ret += "-v128:64:128";63 64 // Try to align aggregates to 32 bits (the default is 64 bits, which has no65 // particular hardware support on 32-bit ARM).66 Ret += "-a:0:32";67 68 // Integer registers are 32 bits.69 Ret += "-n32";70 71 // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.72 if (ABI == ARM::ARM_ABI_AAPCS16)73 Ret += "-S128";74 else if (ABI == ARM::ARM_ABI_AAPCS)75 Ret += "-S64";76 else77 Ret += "-S32";78 79 return Ret;80}81 82// Helper function to build a DataLayout string83static std::string computeAArch64DataLayout(const Triple &TT) {84 if (TT.isOSBinFormatMachO()) {85 if (TT.getArch() == Triple::aarch64_32)86 return "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-"87 "n32:64-S128-Fn32";88 return "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-"89 "Fn32";90 }91 if (TT.isOSBinFormatCOFF())92 return "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-i64:64-i128:"93 "128-n32:64-S128-Fn32";94 std::string Endian = TT.isLittleEndian() ? "e" : "E";95 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";96 return Endian + "-m:e" + Ptr32 +97 "-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-"98 "n32:64-S128-Fn32";99}100 101// DataLayout: little or big endian102static std::string computeBPFDataLayout(const Triple &TT) {103 if (TT.getArch() == Triple::bpfeb)104 return "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128";105 else106 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";107}108 109static std::string computeCSKYDataLayout(const Triple &TT) {110 // CSKY is always 32-bit target with the CSKYv2 ABI as prefer now.111 // It's a 4-byte aligned stack with ELF mangling only.112 // Only support little endian for now.113 // TODO: Add support for big endian.114 return "e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32"115 "-v128:32:32-a:0:32-Fi32-n32";116}117 118static std::string computeLoongArchDataLayout(const Triple &TT) {119 if (TT.isLoongArch64())120 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";121 assert(TT.isLoongArch32() && "only LA32 and LA64 are currently supported");122 return "e-m:e-p:32:32-i64:64-n32-S128";123}124 125static std::string computeM68kDataLayout(const Triple &TT) {126 std::string Ret = "";127 // M68k is Big Endian128 Ret += "E";129 130 // FIXME how to wire it with the used object format?131 Ret += "-m:e";132 133 // M68k pointers are always 32 bit wide even for 16-bit CPUs.134 // The ABI only specifies 16-bit alignment.135 // On at least the 68020+ with a 32-bit bus, there is a performance benefit136 // to having 32-bit alignment.137 Ret += "-p:32:16:32";138 139 // Bytes do not require special alignment, words are word aligned and140 // long words are word aligned at minimum.141 Ret += "-i8:8:8-i16:16:16-i32:16:32";142 143 // FIXME no floats at the moment144 145 // The registers can hold 8, 16, 32 bits146 Ret += "-n8:16:32";147 148 Ret += "-a:0:16-S16";149 150 return Ret;151}152 153namespace {154enum class MipsABI { Unknown, O32, N32, N64 };155}156 157// FIXME: This duplicates MipsABIInfo::computeTargetABI, but duplicating this is158// preferable to violating layering rules. Ideally that information should live159// in LLVM TargetParser, but for now we just duplicate some ABI name string160// logic for simplicity.161static MipsABI getMipsABI(const Triple &TT, StringRef ABIName) {162 if (ABIName.starts_with("o32"))163 return MipsABI::O32;164 if (ABIName.starts_with("n32"))165 return MipsABI::N32;166 if (ABIName.starts_with("n64"))167 return MipsABI::N64;168 if (TT.isABIN32())169 return MipsABI::N32;170 assert(ABIName.empty() && "Unknown ABI option for MIPS");171 172 if (TT.isMIPS64())173 return MipsABI::N64;174 return MipsABI::O32;175}176 177static std::string computeMipsDataLayout(const Triple &TT, StringRef ABIName) {178 std::string Ret;179 MipsABI ABI = getMipsABI(TT, ABIName);180 181 // There are both little and big endian mips.182 if (TT.isLittleEndian())183 Ret += "e";184 else185 Ret += "E";186 187 if (ABI == MipsABI::O32)188 Ret += "-m:m";189 else190 Ret += "-m:e";191 192 // Pointers are 32 bit on some ABIs.193 if (ABI != MipsABI::N64)194 Ret += "-p:32:32";195 196 // 8 and 16 bit integers only need to have natural alignment, but try to197 // align them to 32 bits. 64 bit integers have natural alignment.198 Ret += "-i8:8:32-i16:16:32-i64:64";199 200 // 32 bit registers are always available and the stack is at least 64 bit201 // aligned. On N64 64 bit registers are also available and the stack is202 // 128 bit aligned.203 if (ABI == MipsABI::N64 || ABI == MipsABI::N32)204 Ret += "-i128:128-n32:64-S128";205 else206 Ret += "-n32-S64";207 208 return Ret;209}210 211static std::string computePowerDataLayout(const Triple &T, StringRef ABIName) {212 bool is64Bit = T.isPPC64();213 std::string Ret;214 215 // Most PPC* platforms are big endian, PPC(64)LE is little endian.216 if (T.isLittleEndian())217 Ret = "e";218 else219 Ret = "E";220 221 Ret += getManglingComponent(T);222 223 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit224 // pointers.225 if (!is64Bit || T.getOS() == Triple::Lv2)226 Ret += "-p:32:32";227 228 // If the target ABI uses function descriptors, then the alignment of function229 // pointers depends on the alignment used to emit the descriptor. Otherwise,230 // function pointers are aligned to 32 bits because the instructions must be.231 if ((T.getArch() == Triple::ppc64 &&232 (!T.isPPC64ELFv2ABI() && ABIName != "elfv2"))) {233 Ret += "-Fi64";234 } else if (T.isOSAIX()) {235 Ret += is64Bit ? "-Fi64" : "-Fi32";236 } else {237 Ret += "-Fn32";238 }239 240 // Note, the alignment values for f64 and i64 on ppc64 in Darwin241 // documentation are wrong; these are correct (i.e. "what gcc does").242 Ret += "-i64:64";243 244 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.245 if (is64Bit)246 Ret += "-i128:128-n32:64";247 else248 Ret += "-n32";249 250 // Specify the vector alignment explicitly. For v256i1 and v512i1, the251 // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),252 // which is 256 and 512 bytes - way over aligned.253 if (is64Bit && (T.isOSAIX() || T.isOSLinux()))254 Ret += "-S128-v256:256:256-v512:512:512";255 256 return Ret;257}258 259static std::string computeAMDDataLayout(const Triple &TT) {260 if (TT.getArch() == Triple::r600) {261 // 32-bit pointers.262 return "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"263 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";264 }265 266 // 32-bit private, local, and region pointers. 64-bit global, constant and267 // flat. 160-bit non-integral fat buffer pointers that include a 128-bit268 // buffer descriptor and a 32-bit offset, which are indexed by 32-bit values269 // (address space 7), and 128-bit non-integral buffer resourcees (address270 // space 8) which cannot be non-trivilally accessed by LLVM memory operations271 // like getelementptr.272 return "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"273 "-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-"274 "v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-"275 "v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";276}277 278static std::string computeRISCVDataLayout(const Triple &TT, StringRef ABIName) {279 std::string Ret;280 281 if (TT.isLittleEndian())282 Ret += "e";283 else284 Ret += "E";285 286 Ret += "-m:e";287 288 // Pointer and integer sizes.289 if (TT.isRISCV64()) {290 Ret += "-p:64:64-i64:64-i128:128";291 Ret += "-n32:64";292 } else {293 assert(TT.isRISCV32() && "only RV32 and RV64 are currently supported");294 Ret += "-p:32:32-i64:64";295 Ret += "-n32";296 }297 298 // Stack alignment based on ABI.299 StringRef ABI = ABIName;300 if (ABI == "ilp32e")301 Ret += "-S32";302 else if (ABI == "lp64e")303 Ret += "-S64";304 else305 Ret += "-S128";306 307 return Ret;308}309 310static std::string computeSparcDataLayout(const Triple &T) {311 const bool Is64Bit = T.isSPARC64();312 313 // Sparc is typically big endian, but some are little.314 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";315 Ret += "-m:e";316 317 // Some ABIs have 32bit pointers.318 if (!Is64Bit)319 Ret += "-p:32:32";320 321 // Alignments for 64 bit integers.322 Ret += "-i64:64";323 324 // Alignments for 128 bit integers.325 // This is not specified in the ABI document but is the de facto standard.326 Ret += "-i128:128";327 328 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.329 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.330 if (Is64Bit)331 Ret += "-n32:64";332 else333 Ret += "-f128:64-n32";334 335 if (Is64Bit)336 Ret += "-S128";337 else338 Ret += "-S64";339 340 return Ret;341}342 343static std::string computeSystemZDataLayout(const Triple &TT) {344 std::string Ret;345 346 // Big endian.347 Ret += "E";348 349 // Data mangling.350 Ret += getManglingComponent(TT);351 352 // Special features for z/OS.353 if (TT.isOSzOS()) {354 // Custom address space for ptr32.355 Ret += "-p1:32:32";356 }357 358 // Make sure that global data has at least 16 bits of alignment by359 // default, so that we can refer to it using LARL. We don't have any360 // special requirements for stack variables though.361 Ret += "-i1:8:16-i8:8:16";362 363 // 64-bit integers are naturally aligned.364 Ret += "-i64:64";365 366 // 128-bit floats are aligned only to 64 bits.367 Ret += "-f128:64";368 369 // The DataLayout string always holds a vector alignment of 64 bits, see370 // comment in clang/lib/Basic/Targets/SystemZ.h.371 Ret += "-v128:64";372 373 // We prefer 16 bits of aligned for all globals; see above.374 Ret += "-a:8:16";375 376 // Integer registers are 32 or 64 bits.377 Ret += "-n32:64";378 379 return Ret;380}381 382static std::string computeX86DataLayout(const Triple &TT) {383 bool Is64Bit = TT.isX86_64();384 385 // X86 is little endian386 std::string Ret = "e";387 388 Ret += getManglingComponent(TT);389 // X86 and x32 have 32 bit pointers.390 if (!Is64Bit || TT.isX32())391 Ret += "-p:32:32";392 393 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.394 Ret += "-p270:32:32-p271:32:32-p272:64:64";395 396 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.397 // 128 bit integers are not specified in the 32-bit ABIs but are used398 // internally for lowering f128, so we match the alignment to that.399 if (Is64Bit || TT.isOSWindows())400 Ret += "-i64:64-i128:128";401 else if (TT.isOSIAMCU())402 Ret += "-i64:32-f64:32";403 else404 Ret += "-i128:128-f64:32:64";405 406 // Some ABIs align long double to 128 bits, others to 32.407 if (TT.isOSIAMCU())408 ; // No f80409 else if (Is64Bit || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())410 Ret += "-f80:128";411 else412 Ret += "-f80:32";413 414 if (TT.isOSIAMCU())415 Ret += "-f128:32";416 417 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.418 if (Is64Bit)419 Ret += "-n8:16:32:64";420 else421 Ret += "-n8:16:32";422 423 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.424 if ((!Is64Bit && TT.isOSWindows()) || TT.isOSIAMCU())425 Ret += "-a:0:32-S32";426 else427 Ret += "-S128";428 429 return Ret;430}431 432static std::string computeNVPTXDataLayout(const Triple &T, StringRef ABIName) {433 bool Is64Bit = T.getArch() == Triple::nvptx64;434 std::string Ret = "e";435 436 // Tensor Memory (addrspace:6) is always 32-bits.437 // Distributed Shared Memory (addrspace:7) follows shared memory438 // (addrspace:3).439 if (!Is64Bit)440 Ret += "-p:32:32-p6:32:32-p7:32:32";441 else if (ABIName == "shortptr")442 Ret += "-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32";443 else444 Ret += "-p6:32:32";445 446 Ret += "-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64";447 448 return Ret;449}450 451static std::string computeSPIRVDataLayout(const Triple &TT) {452 const auto Arch = TT.getArch();453 // TODO: this probably needs to be revisited:454 // Logical SPIR-V has no pointer size, so any fixed pointer size would be455 // wrong. The choice to default to 32 or 64 is just motivated by another456 // memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't457 // mean anything.458 if (Arch == Triple::spirv32)459 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"460 "v256:256-v512:512-v1024:1024-n8:16:32:64-G1";461 if (Arch == Triple::spirv)462 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"463 "v512:512-v1024:1024-n8:16:32:64-G10";464 if (TT.getVendor() == Triple::VendorType::AMD &&465 TT.getOS() == Triple::OSType::AMDHSA)466 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"467 "v512:512-v1024:1024-n32:64-S32-G1-P4-A0";468 if (TT.getVendor() == Triple::VendorType::Intel)469 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"470 "v512:512-v1024:1024-n8:16:32:64-G1-P9-A0";471 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"472 "v512:512-v1024:1024-n8:16:32:64-G1";473}474 475static std::string computeLanaiDataLayout() {476 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)477 return "E" // Big endian478 "-m:e" // ELF name manging479 "-p:32:32" // 32-bit pointers, 32 bit aligned480 "-i64:64" // 64 bit integers, 64 bit aligned481 "-a:0:32" // 32 bit alignment of objects of aggregate type482 "-n32" // 32 bit native integer width483 "-S64"; // 64 bit natural stack alignment484}485 486static std::string computeWebAssemblyDataLayout(const Triple &TT) {487 return TT.getArch() == Triple::wasm64488 ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"489 "i128:128-f128:64-n32:64-S128-ni:1:10:20"490 : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"491 "i128:128-n32:64-S128-ni:1:10:20")492 : (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"493 "i128:128-f128:64-n32:64-S128-ni:1:10:20"494 : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"495 "i128:128-n32:64-S128-ni:1:10:20");496}497 498static std::string computeVEDataLayout(const Triple &T) {499 // Aurora VE is little endian500 std::string Ret = "e";501 502 // Use ELF mangling503 Ret += "-m:e";504 505 // Alignments for 64 bit integers.506 Ret += "-i64:64";507 508 // VE supports 32 bit and 64 bits integer on registers509 Ret += "-n32:64";510 511 // Stack alignment is 128 bits512 Ret += "-S128";513 514 // Vector alignments are 64 bits515 // Need to define all of them. Otherwise, each alignment becomes516 // the size of each data by default.517 Ret += "-v64:64:64"; // for v2f32518 Ret += "-v128:64:64";519 Ret += "-v256:64:64";520 Ret += "-v512:64:64";521 Ret += "-v1024:64:64";522 Ret += "-v2048:64:64";523 Ret += "-v4096:64:64";524 Ret += "-v8192:64:64";525 Ret += "-v16384:64:64"; // for v256f64526 527 return Ret;528}529 530std::string Triple::computeDataLayout(StringRef ABIName) const {531 switch (getArch()) {532 case Triple::arm:533 case Triple::armeb:534 case Triple::thumb:535 case Triple::thumbeb:536 return computeARMDataLayout(*this, ABIName);537 case Triple::aarch64:538 case Triple::aarch64_be:539 case Triple::aarch64_32:540 return computeAArch64DataLayout(*this);541 case Triple::arc:542 return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"543 "f32:32:32-i64:32-f64:32-a:0:32-n32";544 case Triple::avr:545 return "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8:16-a:8";546 case Triple::bpfel:547 case Triple::bpfeb:548 return computeBPFDataLayout(*this);549 case Triple::csky:550 return computeCSKYDataLayout(*this);551 case Triple::dxil:552 // TODO: We need to align vectors on the element size generally, but for now553 // we hard code this for 3-element 32- and 64-bit vectors as a workaround.554 // See https://github.com/llvm/llvm-project/issues/123968555 return "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"556 "f32:32-f64:64-n8:16:32:64-v48:16:16-v96:32:32-v192:64:64";557 case Triple::hexagon:558 return "e-m:e-p:32:32:32-a:0-n16:32-"559 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"560 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048";561 case Triple::loongarch32:562 case Triple::loongarch64:563 return computeLoongArchDataLayout(*this);564 case Triple::m68k:565 return computeM68kDataLayout(*this);566 case Triple::mips:567 case Triple::mipsel:568 case Triple::mips64:569 case Triple::mips64el:570 return computeMipsDataLayout(*this, ABIName);571 case Triple::msp430:572 return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";573 case Triple::ppc:574 case Triple::ppcle:575 case Triple::ppc64:576 case Triple::ppc64le:577 return computePowerDataLayout(*this, ABIName);578 case Triple::r600:579 case Triple::amdgcn:580 return computeAMDDataLayout(*this);581 case Triple::riscv32:582 case Triple::riscv64:583 case Triple::riscv32be:584 case Triple::riscv64be:585 return computeRISCVDataLayout(*this, ABIName);586 case Triple::sparc:587 case Triple::sparcv9:588 case Triple::sparcel:589 return computeSparcDataLayout(*this);590 case Triple::systemz:591 return computeSystemZDataLayout(*this);592 case Triple::tce:593 case Triple::tcele:594 case Triple::x86:595 case Triple::x86_64:596 return computeX86DataLayout(*this);597 case Triple::xcore:598 case Triple::xtensa:599 return "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";600 case Triple::nvptx:601 case Triple::nvptx64:602 return computeNVPTXDataLayout(*this, ABIName);603 case Triple::spir:604 case Triple::spir64:605 case Triple::spirv:606 case Triple::spirv32:607 case Triple::spirv64:608 return computeSPIRVDataLayout(*this);609 case Triple::lanai:610 return computeLanaiDataLayout();611 case Triple::wasm32:612 case Triple::wasm64:613 return computeWebAssemblyDataLayout(*this);614 case Triple::ve:615 return computeVEDataLayout(*this);616 617 case Triple::amdil:618 case Triple::amdil64:619 case Triple::hsail:620 case Triple::hsail64:621 case Triple::kalimba:622 case Triple::shave:623 case Triple::renderscript32:624 case Triple::renderscript64:625 // These are all virtual ISAs with no LLVM backend, and therefore no fixed626 // LLVM data layout.627 return "";628 629 case Triple::UnknownArch:630 return "";631 }632 llvm_unreachable("Invalid arch");633}634