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1; RUN: opt %s -O2 -S | FileCheck %s2 3; Check that llvm.x86.avx2.gather.d.ps.256 intrinsic is not eliminated as gather and store memory accesses are based on arr.ptr4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-unknown-linux-gnu"6 7; Function Attrs: nounwind readonly8declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, ptr, <8 x i32>, <8 x float>, i8) #09 10; Function Attrs: nounwind11define <8 x float> @foo1(ptr noalias %arr.ptr, ptr noalias readonly %vix.ptr, ptr noalias %t2.ptr) #1 {12allocas:13 %vix = load <8 x i32>, ptr %vix.ptr, align 414 %t1.ptr = getelementptr i8, ptr %arr.ptr, i8 415 16 %v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #217 store i8 1, ptr %t1.ptr, align 418 19 %v2 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #220 %res = fadd <8 x float> %v1, %v221 22 ret <8 x float> %res23}24; CHECK: foo125; CHECK: llvm.x86.avx2.gather.d.ps.25626; CHECK: store27; CHECK: llvm.x86.avx2.gather.d.ps.25628 29; Check that second gather is eliminated as gather and store memory accesses are based on different no-aliasing pointers30 31; Function Attrs: nounwind32define <8 x float> @foo2(ptr noalias readonly %arr.ptr, ptr noalias readonly %vix.ptr, ptr noalias %t2.ptr) #1 {33allocas:34 %vix = load <8 x i32>, ptr %vix.ptr, align 435 %t1.ptr = getelementptr i8, ptr %arr.ptr, i8 436 37 %v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #238 store i8 1, ptr %t2.ptr, align 439 40 %v2 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #241 %res = fadd <8 x float> %v1, %v242 43 ret <8 x float> %res44}45; CHECK: foo246; CHECK: llvm.x86.avx2.gather.d.ps.25647; CHECK: store48; CHECK-NOT: llvm.x86.avx2.gather.d.ps.25649 50attributes #0 = { nounwind readonly }51attributes #1 = { nounwind "target-cpu"="corei7-avx" "target-features"="+avx2,+popcnt,+cmov,+f16c,+rdrnd,+fma" }52attributes #2 = { nounwind }53 54