81 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py2; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=aarch64-unknown | FileCheck %s3; RUN: opt < %s -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=aarch64-unknown -mattr=slow-misaligned-128store | FileCheck %s --check-prefix=SLOW_MISALIGNED_128_STORE4 5target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-v256:32:256-a0:0:32-n32-S32"6 7; If FeatureSlowMisaligned128Store is set, we penalize 128-bit stores.8; The unlegalized 256-bit stores are further penalized when legalized down9; to 128-bit stores.10 11define void @getMemoryOpCost() {12; CHECK-LABEL: 'getMemoryOpCost'13; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <4 x i64> undef, ptr undef, align 414; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <8 x i32> undef, ptr undef, align 415; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <16 x i16> undef, ptr undef, align 416; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <32 x i8> undef, ptr undef, align 417; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <4 x double> undef, ptr undef, align 418; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <8 x float> undef, ptr undef, align 419; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:1 SizeLat:2 for: store <16 x half> undef, ptr undef, align 420; CHECK-NEXT: Cost Model: Found costs of 1 for: store <2 x i64> undef, ptr undef, align 421; CHECK-NEXT: Cost Model: Found costs of 1 for: store <4 x i32> undef, ptr undef, align 422; CHECK-NEXT: Cost Model: Found costs of 1 for: store <8 x i16> undef, ptr undef, align 423; CHECK-NEXT: Cost Model: Found costs of 1 for: store <16 x i8> undef, ptr undef, align 424; CHECK-NEXT: Cost Model: Found costs of 1 for: store <2 x double> undef, ptr undef, align 425; CHECK-NEXT: Cost Model: Found costs of 1 for: store <4 x float> undef, ptr undef, align 426; CHECK-NEXT: Cost Model: Found costs of 1 for: store <8 x half> undef, ptr undef, align 427; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 228; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i8> undef, ptr undef, align 429; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load <2 x i8>, ptr undef, align 230; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load <4 x i8>, ptr undef, align 431; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void32;33; SLOW_MISALIGNED_128_STORE-LABEL: 'getMemoryOpCost'34; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <4 x i64> undef, ptr undef, align 435; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <8 x i32> undef, ptr undef, align 436; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <16 x i16> undef, ptr undef, align 437; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <32 x i8> undef, ptr undef, align 438; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <4 x double> undef, ptr undef, align 439; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <8 x float> undef, ptr undef, align 440; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:2 Lat:1 SizeLat:2 for: store <16 x half> undef, ptr undef, align 441; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i64> undef, ptr undef, align 442; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i32> undef, ptr undef, align 443; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x i16> undef, ptr undef, align 444; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <16 x i8> undef, ptr undef, align 445; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x double> undef, ptr undef, align 446; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x float> undef, ptr undef, align 447; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:1 SizeLat:1 for: store <8 x half> undef, ptr undef, align 448; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: store <2 x i8> undef, ptr undef, align 249; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: store <4 x i8> undef, ptr undef, align 450; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:1 for: %1 = load <2 x i8>, ptr undef, align 251; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %2 = load <4 x i8>, ptr undef, align 452; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void53;54 store <4 x i64> undef, ptr undef55 store <8 x i32> undef, ptr undef56 store <16 x i16> undef, ptr undef57 store <32 x i8> undef, ptr undef58 59 store <4 x double> undef, ptr undef60 store <8 x float> undef, ptr undef61 store <16 x half> undef, ptr undef62 63 store <2 x i64> undef, ptr undef64 store <4 x i32> undef, ptr undef65 store <8 x i16> undef, ptr undef66 store <16 x i8> undef, ptr undef67 68 store <2 x double> undef, ptr undef69 store <4 x float> undef, ptr undef70 store <8 x half> undef, ptr undef71 72 ; We scalarize the loads/stores because there is no vector register name for73 ; these types (they get extended to v.4h/v.2s).74 store <2 x i8> undef, ptr undef75 store <4 x i8> undef, ptr undef76 load <2 x i8> , ptr undef77 load <4 x i8> , ptr undef78 79 ret void80}81