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1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py2; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 6define void @test_urem_srem_expand() {7; CHECK-LABEL: 'test_urem_srem_expand'8; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef9; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef10; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef11; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef12; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef13; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef14; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef15; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef16; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef17; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef18; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef19; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef20; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef21; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef22; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef23; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef24; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef25; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef26; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef27; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef28; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef29; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef30; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef31; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef32; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void33;34entry:35 %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef36 %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef37 %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef38 %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef39 %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef40 %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef41 %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef42 %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef43 44 %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef45 %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef46 %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef47 %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef48 %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef49 %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef50 %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef51 %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef52 53 %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef54 %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef55 %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef56 %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef57 %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef58 %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef59 %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef60 %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef61 62 ret void63}64