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1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py2; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FAST64 %s3; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOW64 %s4; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FAST64-SIZE %s5; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOW64-SIZE %s6; END.7 8define amdgpu_kernel void @shl() #0 {9; FAST64-LABEL: 'shl'10; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef11; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef12; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef13; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef14; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef15; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef16; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shl <2 x i16> undef, undef17; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = shl <3 x i16> undef, undef18; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shl <4 x i16> undef, undef19; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = shl <5 x i16> undef, undef20; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef21; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef22; FAST64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef23; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef24; FAST64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef25; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef26; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef27; FAST64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef28; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef29; FAST64-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef30; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void31;32; SLOW64-LABEL: 'shl'33; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef34; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef35; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef36; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef37; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef38; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef39; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = shl <2 x i16> undef, undef40; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = shl <3 x i16> undef, undef41; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = shl <4 x i16> undef, undef42; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = shl <5 x i16> undef, undef43; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef44; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef45; SLOW64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef46; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef47; SLOW64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef48; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i64 = shl i64 undef, undef49; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = shl <2 x i64> undef, undef50; SLOW64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = shl <3 x i64> undef, undef51; SLOW64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = shl <4 x i64> undef, undef52; SLOW64-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = shl <5 x i64> undef, undef53; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void54;55; FAST64-SIZE-LABEL: 'shl'56; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef57; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef58; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef59; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef60; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef61; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef62; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shl <2 x i16> undef, undef63; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = shl <3 x i16> undef, undef64; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shl <4 x i16> undef, undef65; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = shl <5 x i16> undef, undef66; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef67; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef68; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef69; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef70; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef71; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef72; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef73; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef74; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef75; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef76; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void77;78; SLOW64-SIZE-LABEL: 'shl'79; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef80; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef81; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef82; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef83; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef84; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef85; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = shl <2 x i16> undef, undef86; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = shl <3 x i16> undef, undef87; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = shl <4 x i16> undef, undef88; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = shl <5 x i16> undef, undef89; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef90; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef91; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef92; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef93; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef94; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef95; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef96; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef97; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef98; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef99; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void100;101 %i8 = shl i8 undef, undef102 %v2i8 = shl <2 x i8> undef, undef103 %v3i8 = shl <3 x i8> undef, undef104 %v4i8 = shl <4 x i8> undef, undef105 %v5i8 = shl <5 x i8> undef, undef106 %i16 = shl i16 undef, undef107 %v2i16 = shl <2 x i16> undef, undef108 %v3i16 = shl <3 x i16> undef, undef109 %v4i16 = shl <4 x i16> undef, undef110 %v5i16 = shl <5 x i16> undef, undef111 %i32 = shl i32 undef, undef112 %v2i32 = shl <2 x i32> undef, undef113 %v3i32 = shl <3 x i32> undef, undef114 %v4i32 = shl <4 x i32> undef, undef115 %v5i32 = shl <5 x i32> undef, undef116 %i64 = shl i64 undef, undef117 %v2i64 = shl <2 x i64> undef, undef118 %v3i64 = shl <3 x i64> undef, undef119 %v4i64 = shl <4 x i64> undef, undef120 %v5i64 = shl <5 x i64> undef, undef121 ret void122}123 124define amdgpu_kernel void @lshr() #0 {125; FAST64-LABEL: 'lshr'126; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef127; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef128; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef129; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef130; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef131; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef132; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = lshr <2 x i16> undef, undef133; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = lshr <3 x i16> undef, undef134; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = lshr <4 x i16> undef, undef135; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = lshr <5 x i16> undef, undef136; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef137; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef138; FAST64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef139; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef140; FAST64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef141; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef142; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef143; FAST64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef144; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef145; FAST64-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef146; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void147;148; SLOW64-LABEL: 'lshr'149; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef150; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef151; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef152; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef153; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef154; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef155; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = lshr <2 x i16> undef, undef156; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = lshr <3 x i16> undef, undef157; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = lshr <4 x i16> undef, undef158; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = lshr <5 x i16> undef, undef159; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef160; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef161; SLOW64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef162; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef163; SLOW64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef164; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i64 = lshr i64 undef, undef165; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = lshr <2 x i64> undef, undef166; SLOW64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = lshr <3 x i64> undef, undef167; SLOW64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = lshr <4 x i64> undef, undef168; SLOW64-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = lshr <5 x i64> undef, undef169; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void170;171; FAST64-SIZE-LABEL: 'lshr'172; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef173; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef174; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef175; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef176; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef177; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef178; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = lshr <2 x i16> undef, undef179; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = lshr <3 x i16> undef, undef180; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = lshr <4 x i16> undef, undef181; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = lshr <5 x i16> undef, undef182; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef183; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef184; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef185; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef186; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef187; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef188; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef189; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef190; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef191; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef192; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void193;194; SLOW64-SIZE-LABEL: 'lshr'195; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef196; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef197; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef198; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef199; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef200; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef201; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = lshr <2 x i16> undef, undef202; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = lshr <3 x i16> undef, undef203; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = lshr <4 x i16> undef, undef204; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = lshr <5 x i16> undef, undef205; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef206; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef207; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef208; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef209; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef210; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef211; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef212; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef213; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef214; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef215; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void216;217 %i8 = lshr i8 undef, undef218 %v2i8 = lshr <2 x i8> undef, undef219 %v3i8 = lshr <3 x i8> undef, undef220 %v4i8 = lshr <4 x i8> undef, undef221 %v5i8 = lshr <5 x i8> undef, undef222 %i16 = lshr i16 undef, undef223 %v2i16 = lshr <2 x i16> undef, undef224 %v3i16 = lshr <3 x i16> undef, undef225 %v4i16 = lshr <4 x i16> undef, undef226 %v5i16 = lshr <5 x i16> undef, undef227 %i32 = lshr i32 undef, undef228 %v2i32 = lshr <2 x i32> undef, undef229 %v3i32 = lshr <3 x i32> undef, undef230 %v4i32 = lshr <4 x i32> undef, undef231 %v5i32 = lshr <5 x i32> undef, undef232 %i64 = lshr i64 undef, undef233 %v2i64 = lshr <2 x i64> undef, undef234 %v3i64 = lshr <3 x i64> undef, undef235 %v4i64 = lshr <4 x i64> undef, undef236 %v5i64 = lshr <5 x i64> undef, undef237 ret void238}239 240define amdgpu_kernel void @ashr() #0 {241; FAST64-LABEL: 'ashr'242; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef243; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef244; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef245; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef246; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef247; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef248; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = ashr <2 x i16> undef, undef249; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = ashr <3 x i16> undef, undef250; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = ashr <4 x i16> undef, undef251; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = ashr <5 x i16> undef, undef252; FAST64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef253; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef254; FAST64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef255; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef256; FAST64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef257; FAST64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef258; FAST64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef259; FAST64-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef260; FAST64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef261; FAST64-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef262; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void263;264; SLOW64-LABEL: 'ashr'265; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef266; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef267; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef268; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef269; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef270; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef271; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = ashr <2 x i16> undef, undef272; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = ashr <3 x i16> undef, undef273; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = ashr <4 x i16> undef, undef274; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = ashr <5 x i16> undef, undef275; SLOW64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef276; SLOW64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef277; SLOW64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef278; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef279; SLOW64-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef280; SLOW64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i64 = ashr i64 undef, undef281; SLOW64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = ashr <2 x i64> undef, undef282; SLOW64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = ashr <3 x i64> undef, undef283; SLOW64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = ashr <4 x i64> undef, undef284; SLOW64-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = ashr <5 x i64> undef, undef285; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void286;287; FAST64-SIZE-LABEL: 'ashr'288; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef289; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef290; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef291; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef292; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef293; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef294; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = ashr <2 x i16> undef, undef295; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = ashr <3 x i16> undef, undef296; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = ashr <4 x i16> undef, undef297; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = ashr <5 x i16> undef, undef298; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef299; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef300; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef301; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef302; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef303; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef304; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef305; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef306; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef307; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef308; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void309;310; SLOW64-SIZE-LABEL: 'ashr'311; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef312; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef313; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef314; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef315; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef316; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef317; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = ashr <2 x i16> undef, undef318; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = ashr <3 x i16> undef, undef319; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = ashr <4 x i16> undef, undef320; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = ashr <5 x i16> undef, undef321; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef322; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef323; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef324; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef325; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef326; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef327; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef328; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef329; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef330; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef331; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void332;333 %i8 = ashr i8 undef, undef334 %v2i8 = ashr <2 x i8> undef, undef335 %v3i8 = ashr <3 x i8> undef, undef336 %v4i8 = ashr <4 x i8> undef, undef337 %v5i8 = ashr <5 x i8> undef, undef338 %i16 = ashr i16 undef, undef339 %v2i16 = ashr <2 x i16> undef, undef340 %v3i16 = ashr <3 x i16> undef, undef341 %v4i16 = ashr <4 x i16> undef, undef342 %v5i16 = ashr <5 x i16> undef, undef343 %i32 = ashr i32 undef, undef344 %v2i32 = ashr <2 x i32> undef, undef345 %v3i32 = ashr <3 x i32> undef, undef346 %v4i32 = ashr <4 x i32> undef, undef347 %v5i32 = ashr <5 x i32> undef, undef348 %i64 = ashr i64 undef, undef349 %v2i64 = ashr <2 x i64> undef, undef350 %v3i64 = ashr <3 x i64> undef, undef351 %v4i64 = ashr <4 x i64> undef, undef352 %v5i64 = ashr <5 x i64> undef, undef353 ret void354}355 356attributes #0 = { nounwind }357