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1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 62; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s3 4target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"5target triple = "thumbv7-apple-ios6.0.0"6 7; Multiple insert elements from loads into d subregisters are expensive on swift8; due to renaming constraints.9%T_i8v = type <8 x i8>10%T_i8 = type i811define void @insertelement_i8(ptr %saddr, ptr %vaddr) {12; CHECK-LABEL: 'insertelement_i8'13; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <8 x i8>, ptr %vaddr, align 414; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %saddr, align 115; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <8 x i8> %v0, i8 %v1, i32 116; CHECK-NEXT: Cost Model: Found costs of 1 for: store <8 x i8> %v2, ptr %vaddr, align 417; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void18;19 %v0 = load %T_i8v, ptr %vaddr20 %v1 = load %T_i8, ptr %saddr21 %v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 122 store %T_i8v %v2, ptr %vaddr23 ret void24}25 26 27%T_i16v = type <4 x i16>28%T_i16 = type i1629define void @insertelement_i16(ptr %saddr, ptr %vaddr) {30; CHECK-LABEL: 'insertelement_i16'31; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %vaddr, align 432; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i16, ptr %saddr, align 233; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <4 x i16> %v0, i16 %v1, i32 134; CHECK-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %v2, ptr %vaddr, align 435; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void36;37 %v0 = load %T_i16v, ptr %vaddr38 %v1 = load %T_i16, ptr %saddr39 %v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 140 store %T_i16v %v2, ptr %vaddr41 ret void42}43 44%T_i32v = type <2 x i32>45%T_i32 = type i3246define void @insertelement_i32(ptr %saddr, ptr %vaddr) {47; CHECK-LABEL: 'insertelement_i32'48; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %vaddr, align 449; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i32, ptr %saddr, align 450; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <2 x i32> %v0, i32 %v1, i32 151; CHECK-NEXT: Cost Model: Found costs of 1 for: store <2 x i32> %v2, ptr %vaddr, align 452; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void53;54 %v0 = load %T_i32v, ptr %vaddr55 %v1 = load %T_i32, ptr %saddr56 %v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 157 store %T_i32v %v2, ptr %vaddr58 ret void59}60