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1; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 -disable-ppc-unaligned | FileCheck %s2target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"3target triple = "powerpc64-unknown-linux-gnu"4 5define i32 @stores(i32 %arg) {6 7 ; CHECK: cost of 1 {{.*}} store8 store i8 undef, ptr undef, align 49 ; CHECK: cost of 1 {{.*}} store10 store i16 undef, ptr undef, align 411 ; CHECK: cost of 1 {{.*}} store12 store i32 undef, ptr undef, align 413 ; CHECK: cost of 2 {{.*}} store14 store i64 undef, ptr undef, align 415 ; CHECK: cost of 4 {{.*}} store16 store i128 undef, ptr undef, align 417 18 ret i32 undef19}20define i32 @loads(i32 %arg) {21 ; CHECK: cost of 1 {{.*}} load22 load i8, ptr undef, align 423 ; CHECK: cost of 1 {{.*}} load24 load i16, ptr undef, align 425 ; CHECK: cost of 1 {{.*}} load26 load i32, ptr undef, align 427 ; CHECK: cost of 2 {{.*}} load28 load i64, ptr undef, align 429 ; CHECK: cost of 4 {{.*}} load30 load i128, ptr undef, align 431 32 ; FIXME: There actually are sub-vector Altivec loads, and so we could handle33 ; this with a small expense, but we don't currently.34 ; CHECK: cost of 42 {{.*}} load35 load <4 x i16>, ptr undef, align 236 37 ; CHECK: cost of 2 {{.*}} load38 load <4 x i32>, ptr undef, align 439 40 ; CHECK: cost of 46 {{.*}} load41 load <3 x float>, ptr undef, align 142 43 ret i32 undef44}45 46define i32 @partialvector32(i32 %arg) #0 {47 48 ; CHECK: cost of 1 {{.*}} store49 store <4 x i8> undef, ptr undef, align 1650 51 ret i32 undef52}53 54define i32 @partialvector64(i32 %arg) #1 {55 56 ; CHECK: cost of 1 {{.*}} store57 store <4 x i16> undef, ptr undef, align 1658 59 ret i32 undef60}61 62attributes #0 = { "target-features"="+power8-vector,+vsx" }63 64attributes #1 = { "target-features"="+vsx" }65