332 lines · plain
1; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s2target datalayout = "E-m:e-i64:64-n32:64"3target triple = "powerpc64-unknown-linux-gnu"4 5define <16 x i8> @test_l_v16i8(ptr %p) #0 {6entry:7 %r = load <16 x i8>, ptr %p, align 18 ret <16 x i8> %r9 10; CHECK-LABEL: test_l_v16i811; CHECK: cost of 2 for instruction: %r = load <16 x i8>, ptr %p, align 112}13 14define <32 x i8> @test_l_v32i8(ptr %p) #0 {15entry:16 %r = load <32 x i8>, ptr %p, align 117 ret <32 x i8> %r18 19; CHECK-LABEL: test_l_v32i820; CHECK: cost of 4 for instruction: %r = load <32 x i8>, ptr %p, align 121}22 23define <8 x i16> @test_l_v8i16(ptr %p) #0 {24entry:25 %r = load <8 x i16>, ptr %p, align 226 ret <8 x i16> %r27 28; CHECK-LABEL: test_l_v8i1629; CHECK: cost of 2 for instruction: %r = load <8 x i16>, ptr %p, align 230}31 32define <16 x i16> @test_l_v16i16(ptr %p) #0 {33entry:34 %r = load <16 x i16>, ptr %p, align 235 ret <16 x i16> %r36 37; CHECK-LABEL: test_l_v16i1638; CHECK: cost of 4 for instruction: %r = load <16 x i16>, ptr %p, align 239}40 41define <4 x i32> @test_l_v4i32(ptr %p) #0 {42entry:43 %r = load <4 x i32>, ptr %p, align 444 ret <4 x i32> %r45 46; CHECK-LABEL: test_l_v4i3247; CHECK: cost of 2 for instruction: %r = load <4 x i32>, ptr %p, align 448}49 50define <8 x i32> @test_l_v8i32(ptr %p) #0 {51entry:52 %r = load <8 x i32>, ptr %p, align 453 ret <8 x i32> %r54 55; CHECK-LABEL: test_l_v8i3256; CHECK: cost of 4 for instruction: %r = load <8 x i32>, ptr %p, align 457}58 59define <2 x i64> @test_l_v2i64(ptr %p) #0 {60entry:61 %r = load <2 x i64>, ptr %p, align 862 ret <2 x i64> %r63 64; CHECK-LABEL: test_l_v2i6465; CHECK: cost of 1 for instruction: %r = load <2 x i64>, ptr %p, align 866}67 68define <4 x i64> @test_l_v4i64(ptr %p) #0 {69entry:70 %r = load <4 x i64>, ptr %p, align 871 ret <4 x i64> %r72 73; CHECK-LABEL: test_l_v4i6474; CHECK: cost of 2 for instruction: %r = load <4 x i64>, ptr %p, align 875}76 77define <4 x float> @test_l_v4float(ptr %p) #0 {78entry:79 %r = load <4 x float>, ptr %p, align 480 ret <4 x float> %r81 82; CHECK-LABEL: test_l_v4float83; CHECK: cost of 2 for instruction: %r = load <4 x float>, ptr %p, align 484}85 86define <8 x float> @test_l_v8float(ptr %p) #0 {87entry:88 %r = load <8 x float>, ptr %p, align 489 ret <8 x float> %r90 91; CHECK-LABEL: test_l_v8float92; CHECK: cost of 4 for instruction: %r = load <8 x float>, ptr %p, align 493}94 95define <2 x double> @test_l_v2double(ptr %p) #0 {96entry:97 %r = load <2 x double>, ptr %p, align 898 ret <2 x double> %r99 100; CHECK-LABEL: test_l_v2double101; CHECK: cost of 1 for instruction: %r = load <2 x double>, ptr %p, align 8102}103 104define <4 x double> @test_l_v4double(ptr %p) #0 {105entry:106 %r = load <4 x double>, ptr %p, align 8107 ret <4 x double> %r108 109; CHECK-LABEL: test_l_v4double110; CHECK: cost of 2 for instruction: %r = load <4 x double>, ptr %p, align 8111}112 113define <16 x i8> @test_l_p8v16i8(ptr %p) #2 {114entry:115 %r = load <16 x i8>, ptr %p, align 1116 ret <16 x i8> %r117 118; CHECK-LABEL: test_l_p8v16i8119; CHECK: cost of 1 for instruction: %r = load <16 x i8>, ptr %p, align 1120}121 122define <32 x i8> @test_l_p8v32i8(ptr %p) #2 {123entry:124 %r = load <32 x i8>, ptr %p, align 1125 ret <32 x i8> %r126 127; CHECK-LABEL: test_l_p8v32i8128; CHECK: cost of 2 for instruction: %r = load <32 x i8>, ptr %p, align 1129}130 131define <8 x i16> @test_l_p8v8i16(ptr %p) #2 {132entry:133 %r = load <8 x i16>, ptr %p, align 2134 ret <8 x i16> %r135 136; CHECK-LABEL: test_l_p8v8i16137; CHECK: cost of 1 for instruction: %r = load <8 x i16>, ptr %p, align 2138}139 140define <16 x i16> @test_l_p8v16i16(ptr %p) #2 {141entry:142 %r = load <16 x i16>, ptr %p, align 2143 ret <16 x i16> %r144 145; CHECK-LABEL: test_l_p8v16i16146; CHECK: cost of 2 for instruction: %r = load <16 x i16>, ptr %p, align 2147}148 149define <4 x i32> @test_l_p8v4i32(ptr %p) #2 {150entry:151 %r = load <4 x i32>, ptr %p, align 4152 ret <4 x i32> %r153 154; CHECK-LABEL: test_l_p8v4i32155; CHECK: cost of 1 for instruction: %r = load <4 x i32>, ptr %p, align 4156}157 158define <8 x i32> @test_l_p8v8i32(ptr %p) #2 {159entry:160 %r = load <8 x i32>, ptr %p, align 4161 ret <8 x i32> %r162 163; CHECK-LABEL: test_l_p8v8i32164; CHECK: cost of 2 for instruction: %r = load <8 x i32>, ptr %p, align 4165}166 167define <2 x i64> @test_l_p8v2i64(ptr %p) #2 {168entry:169 %r = load <2 x i64>, ptr %p, align 8170 ret <2 x i64> %r171 172; CHECK-LABEL: test_l_p8v2i64173; CHECK: cost of 1 for instruction: %r = load <2 x i64>, ptr %p, align 8174}175 176define <4 x i64> @test_l_p8v4i64(ptr %p) #2 {177entry:178 %r = load <4 x i64>, ptr %p, align 8179 ret <4 x i64> %r180 181; CHECK-LABEL: test_l_p8v4i64182; CHECK: cost of 2 for instruction: %r = load <4 x i64>, ptr %p, align 8183}184 185define <4 x float> @test_l_p8v4float(ptr %p) #2 {186entry:187 %r = load <4 x float>, ptr %p, align 4188 ret <4 x float> %r189 190; CHECK-LABEL: test_l_p8v4float191; CHECK: cost of 1 for instruction: %r = load <4 x float>, ptr %p, align 4192}193 194define <8 x float> @test_l_p8v8float(ptr %p) #2 {195entry:196 %r = load <8 x float>, ptr %p, align 4197 ret <8 x float> %r198 199; CHECK-LABEL: test_l_p8v8float200; CHECK: cost of 2 for instruction: %r = load <8 x float>, ptr %p, align 4201}202 203define <2 x double> @test_l_p8v2double(ptr %p) #2 {204entry:205 %r = load <2 x double>, ptr %p, align 8206 ret <2 x double> %r207 208; CHECK-LABEL: test_l_p8v2double209; CHECK: cost of 1 for instruction: %r = load <2 x double>, ptr %p, align 8210}211 212define <4 x double> @test_l_p8v4double(ptr %p) #2 {213entry:214 %r = load <4 x double>, ptr %p, align 8215 ret <4 x double> %r216 217; CHECK-LABEL: test_l_p8v4double218; CHECK: cost of 2 for instruction: %r = load <4 x double>, ptr %p, align 8219}220 221define void @test_s_v16i8(ptr %p, <16 x i8> %v) #0 {222entry:223 store <16 x i8> %v, ptr %p, align 1224 ret void225 226; CHECK-LABEL: test_s_v16i8227; CHECK: cost of 1 for instruction: store <16 x i8> %v, ptr %p, align 1228}229 230define void @test_s_v32i8(ptr %p, <32 x i8> %v) #0 {231entry:232 store <32 x i8> %v, ptr %p, align 1233 ret void234 235; CHECK-LABEL: test_s_v32i8236; CHECK: cost of 2 for instruction: store <32 x i8> %v, ptr %p, align 1237}238 239define void @test_s_v8i16(ptr %p, <8 x i16> %v) #0 {240entry:241 store <8 x i16> %v, ptr %p, align 2242 ret void243 244; CHECK-LABEL: test_s_v8i16245; CHECK: cost of 1 for instruction: store <8 x i16> %v, ptr %p, align 2246}247 248define void @test_s_v16i16(ptr %p, <16 x i16> %v) #0 {249entry:250 store <16 x i16> %v, ptr %p, align 2251 ret void252 253; CHECK-LABEL: test_s_v16i16254; CHECK: cost of 2 for instruction: store <16 x i16> %v, ptr %p, align 2255}256 257define void @test_s_v4i32(ptr %p, <4 x i32> %v) #0 {258entry:259 store <4 x i32> %v, ptr %p, align 4260 ret void261 262; CHECK-LABEL: test_s_v4i32263; CHECK: cost of 1 for instruction: store <4 x i32> %v, ptr %p, align 4264}265 266define void @test_s_v8i32(ptr %p, <8 x i32> %v) #0 {267entry:268 store <8 x i32> %v, ptr %p, align 4269 ret void270 271; CHECK-LABEL: test_s_v8i32272; CHECK: cost of 2 for instruction: store <8 x i32> %v, ptr %p, align 4273}274 275define void @test_s_v2i64(ptr %p, <2 x i64> %v) #0 {276entry:277 store <2 x i64> %v, ptr %p, align 8278 ret void279 280; CHECK-LABEL: test_s_v2i64281; CHECK: cost of 1 for instruction: store <2 x i64> %v, ptr %p, align 8282}283 284define void @test_s_v4i64(ptr %p, <4 x i64> %v) #0 {285entry:286 store <4 x i64> %v, ptr %p, align 8287 ret void288 289; CHECK-LABEL: test_s_v4i64290; CHECK: cost of 2 for instruction: store <4 x i64> %v, ptr %p, align 8291}292 293define void @test_s_v4float(ptr %p, <4 x float> %v) #0 {294entry:295 store <4 x float> %v, ptr %p, align 4296 ret void297 298; CHECK-LABEL: test_s_v4float299; CHECK: cost of 1 for instruction: store <4 x float> %v, ptr %p, align 4300}301 302define void @test_s_v8float(ptr %p, <8 x float> %v) #0 {303entry:304 store <8 x float> %v, ptr %p, align 4305 ret void306 307; CHECK-LABEL: test_s_v8float308; CHECK: cost of 2 for instruction: store <8 x float> %v, ptr %p, align 4309}310 311define void @test_s_v2double(ptr %p, <2 x double> %v) #0 {312entry:313 store <2 x double> %v, ptr %p, align 8314 ret void315 316; CHECK-LABEL: test_s_v2double317; CHECK: cost of 1 for instruction: store <2 x double> %v, ptr %p, align 8318}319 320define void @test_s_v4double(ptr %p, <4 x double> %v) #0 {321entry:322 store <4 x double> %v, ptr %p, align 8323 ret void324 325; CHECK-LABEL: test_s_v4double326; CHECK: cost of 2 for instruction: store <4 x double> %v, ptr %p, align 8327}328 329attributes #0 = { nounwind "target-cpu"="pwr7" }330attributes #2 = { nounwind "target-cpu"="pwr8" }331 332