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1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py2; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+sse2 | FileCheck %s --check-prefixes=SSE23; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE34; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE415; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE426; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+avx | FileCheck %s --check-prefixes=AVX17; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+avx2 | FileCheck %s --check-prefixes=AVX28; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+avx512f | FileCheck %s --check-prefixes=AVX5129; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX51210; RUN: opt < %s -passes="print<cost-model>" -mtriple=x86_64-apple-darwin 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=AVX51211 12define void @reduce_f64(double %arg) {13; SSE2-LABEL: 'reduce_f64'14; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)15; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)16; SSE2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:6 Lat:22 SizeLat:6 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)17; SSE2-NEXT: Cost Model: Found costs of RThru:20 CodeSize:12 Lat:44 SizeLat:12 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)18; SSE2-NEXT: Cost Model: Found costs of RThru:40 CodeSize:24 Lat:88 SizeLat:24 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)19; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void20;21; SSSE3-LABEL: 'reduce_f64'22; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)23; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)24; SSSE3-NEXT: Cost Model: Found costs of RThru:10 CodeSize:6 Lat:22 SizeLat:6 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)25; SSSE3-NEXT: Cost Model: Found costs of RThru:20 CodeSize:12 Lat:44 SizeLat:12 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)26; SSSE3-NEXT: Cost Model: Found costs of RThru:40 CodeSize:24 Lat:88 SizeLat:24 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)27; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void28;29; SSE41-LABEL: 'reduce_f64'30; SSE41-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)31; SSE41-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)32; SSE41-NEXT: Cost Model: Found costs of RThru:10 CodeSize:6 Lat:22 SizeLat:6 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)33; SSE41-NEXT: Cost Model: Found costs of RThru:20 CodeSize:12 Lat:44 SizeLat:12 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)34; SSE41-NEXT: Cost Model: Found costs of RThru:40 CodeSize:24 Lat:88 SizeLat:24 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)35; SSE41-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void36;37; SSE42-LABEL: 'reduce_f64'38; SSE42-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)39; SSE42-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)40; SSE42-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:22 SizeLat:6 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)41; SSE42-NEXT: Cost Model: Found costs of RThru:12 CodeSize:12 Lat:44 SizeLat:12 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)42; SSE42-NEXT: Cost Model: Found costs of RThru:24 CodeSize:24 Lat:88 SizeLat:24 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)43; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void44;45; AVX1-LABEL: 'reduce_f64'46; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)47; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)48; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)49; AVX1-NEXT: Cost Model: Found costs of RThru:22 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)50; AVX1-NEXT: Cost Model: Found costs of RThru:44 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)51; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void52;53; AVX2-LABEL: 'reduce_f64'54; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)55; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)56; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)57; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)58; AVX2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)59; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void60;61; AVX512-LABEL: 'reduce_f64'62; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)63; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:9 SizeLat:3 for: %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)64; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:19 SizeLat:7 for: %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)65; AVX512-NEXT: Cost Model: Found costs of RThru:15 CodeSize:15 Lat:39 SizeLat:15 for: %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)66; AVX512-NEXT: Cost Model: Found costs of RThru:30 CodeSize:30 Lat:78 SizeLat:30 for: %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)67; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void68;69 %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)70 %V2 = call double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)71 %V4 = call double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)72 %V8 = call double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)73 %V16 = call double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)74 ret void75}76 77define void @reduce_f32(float %arg) {78; SSE2-LABEL: 'reduce_f32'79; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)80; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)81; SSE2-NEXT: Cost Model: Found costs of RThru:11 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)82; SSE2-NEXT: Cost Model: Found costs of RThru:22 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)83; SSE2-NEXT: Cost Model: Found costs of RThru:44 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)84; SSE2-NEXT: Cost Model: Found costs of RThru:88 CodeSize:56 Lat:184 SizeLat:56 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)85; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void86;87; SSSE3-LABEL: 'reduce_f32'88; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)89; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)90; SSSE3-NEXT: Cost Model: Found costs of RThru:11 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)91; SSSE3-NEXT: Cost Model: Found costs of RThru:22 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)92; SSSE3-NEXT: Cost Model: Found costs of RThru:44 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)93; SSSE3-NEXT: Cost Model: Found costs of RThru:88 CodeSize:56 Lat:184 SizeLat:56 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)94; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void95;96; SSE41-LABEL: 'reduce_f32'97; SSE41-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)98; SSE41-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)99; SSE41-NEXT: Cost Model: Found costs of RThru:11 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)100; SSE41-NEXT: Cost Model: Found costs of RThru:22 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)101; SSE41-NEXT: Cost Model: Found costs of RThru:44 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)102; SSE41-NEXT: Cost Model: Found costs of RThru:88 CodeSize:56 Lat:184 SizeLat:56 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)103; SSE41-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void104;105; SSE42-LABEL: 'reduce_f32'106; SSE42-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)107; SSE42-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)108; SSE42-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)109; SSE42-NEXT: Cost Model: Found costs of RThru:14 CodeSize:14 Lat:46 SizeLat:14 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)110; SSE42-NEXT: Cost Model: Found costs of RThru:28 CodeSize:28 Lat:92 SizeLat:28 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)111; SSE42-NEXT: Cost Model: Found costs of RThru:56 CodeSize:56 Lat:184 SizeLat:56 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)112; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void113;114; AVX1-LABEL: 'reduce_f32'115; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)116; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)117; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)118; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:15 Lat:47 SizeLat:15 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)119; AVX1-NEXT: Cost Model: Found costs of RThru:30 CodeSize:30 Lat:94 SizeLat:30 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)120; AVX1-NEXT: Cost Model: Found costs of RThru:60 CodeSize:60 Lat:188 SizeLat:60 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)121; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void122;123; AVX2-LABEL: 'reduce_f32'124; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:5 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)125; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)126; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:23 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)127; AVX2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:15 Lat:47 SizeLat:15 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)128; AVX2-NEXT: Cost Model: Found costs of RThru:30 CodeSize:30 Lat:94 SizeLat:30 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)129; AVX2-NEXT: Cost Model: Found costs of RThru:60 CodeSize:60 Lat:188 SizeLat:60 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)130; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void131;132; AVX512-LABEL: 'reduce_f32'133; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)134; AVX512-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:9 SizeLat:3 for: %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)135; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:19 SizeLat:7 for: %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)136; AVX512-NEXT: Cost Model: Found costs of RThru:15 CodeSize:15 Lat:39 SizeLat:15 for: %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)137; AVX512-NEXT: Cost Model: Found costs of RThru:31 CodeSize:31 Lat:79 SizeLat:31 for: %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)138; AVX512-NEXT: Cost Model: Found costs of RThru:62 CodeSize:62 Lat:158 SizeLat:62 for: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)139; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void140;141 %V1 = call float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)142 %V2 = call float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)143 %V4 = call float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)144 %V8 = call float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)145 %V16 = call float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)146 %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)147 ret void148}149 150; Fast Reductions151 152define void @reduce_f64_fast(double %arg) {153; SSE2-LABEL: 'reduce_f64_fast'154; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)155; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)156; SSE2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)157; SSE2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:5 Lat:21 SizeLat:5 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)158; SSE2-NEXT: Cost Model: Found costs of RThru:17 CodeSize:9 Lat:41 SizeLat:9 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)159; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void160;161; SSSE3-LABEL: 'reduce_f64_fast'162; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)163; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)164; SSSE3-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)165; SSSE3-NEXT: Cost Model: Found costs of RThru:9 CodeSize:5 Lat:21 SizeLat:5 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)166; SSSE3-NEXT: Cost Model: Found costs of RThru:17 CodeSize:9 Lat:41 SizeLat:9 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)167; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void168;169; SSE41-LABEL: 'reduce_f64_fast'170; SSE41-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)171; SSE41-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)172; SSE41-NEXT: Cost Model: Found costs of RThru:5 CodeSize:3 Lat:11 SizeLat:3 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)173; SSE41-NEXT: Cost Model: Found costs of RThru:9 CodeSize:5 Lat:21 SizeLat:5 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)174; SSE41-NEXT: Cost Model: Found costs of RThru:17 CodeSize:9 Lat:41 SizeLat:9 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)175; SSE41-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void176;177; SSE42-LABEL: 'reduce_f64_fast'178; SSE42-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)179; SSE42-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)180; SSE42-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:11 SizeLat:3 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)181; SSE42-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:21 SizeLat:5 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)182; SSE42-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:41 SizeLat:9 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)183; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void184;185; AVX1-LABEL: 'reduce_f64_fast'186; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)187; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)188; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)189; AVX1-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:17 SizeLat:6 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)190; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:7 Lat:27 SizeLat:10 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)191; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void192;193; AVX2-LABEL: 'reduce_f64_fast'194; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)195; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)196; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)197; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:17 SizeLat:6 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)198; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:27 SizeLat:10 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)199; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void200;201; AVX512-LABEL: 'reduce_f64_fast'202; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)203; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:7 SizeLat:2 for: %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)204; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)205; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:17 SizeLat:6 for: %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)206; AVX512-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:21 SizeLat:7 for: %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)207; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void208;209 %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)210 %V2 = call fast double @llvm.vector.reduce.fmul.v2f64(double %arg, <2 x double> undef)211 %V4 = call fast double @llvm.vector.reduce.fmul.v4f64(double %arg, <4 x double> undef)212 %V8 = call fast double @llvm.vector.reduce.fmul.v8f64(double %arg, <8 x double> undef)213 %V16 = call fast double @llvm.vector.reduce.fmul.v16f64(double %arg, <16 x double> undef)214 ret void215}216 217define void @reduce_f32_fast(float %arg) {218; SSE2-LABEL: 'reduce_f32_fast'219; SSE2-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)220; SSE2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)221; SSE2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)222; SSE2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:5 Lat:17 SizeLat:5 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)223; SSE2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:7 Lat:27 SizeLat:7 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)224; SSE2-NEXT: Cost Model: Found costs of RThru:20 CodeSize:11 Lat:47 SizeLat:11 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)225; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void226;227; SSSE3-LABEL: 'reduce_f32_fast'228; SSSE3-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)229; SSSE3-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)230; SSSE3-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)231; SSSE3-NEXT: Cost Model: Found costs of RThru:8 CodeSize:5 Lat:17 SizeLat:5 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)232; SSSE3-NEXT: Cost Model: Found costs of RThru:12 CodeSize:7 Lat:27 SizeLat:7 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)233; SSSE3-NEXT: Cost Model: Found costs of RThru:20 CodeSize:11 Lat:47 SizeLat:11 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)234; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void235;236; SSE41-LABEL: 'reduce_f32_fast'237; SSE41-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)238; SSE41-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)239; SSE41-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)240; SSE41-NEXT: Cost Model: Found costs of RThru:8 CodeSize:5 Lat:17 SizeLat:5 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)241; SSE41-NEXT: Cost Model: Found costs of RThru:12 CodeSize:7 Lat:27 SizeLat:7 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)242; SSE41-NEXT: Cost Model: Found costs of RThru:20 CodeSize:11 Lat:47 SizeLat:11 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)243; SSE41-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void244;245; SSE42-LABEL: 'reduce_f32_fast'246; SSE42-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)247; SSE42-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)248; SSE42-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)249; SSE42-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:17 SizeLat:5 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)250; SSE42-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:27 SizeLat:7 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)251; SSE42-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:47 SizeLat:11 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)252; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void253;254; AVX1-LABEL: 'reduce_f32_fast'255; AVX1-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)256; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)257; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)258; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:18 SizeLat:6 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)259; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:23 SizeLat:8 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)260; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:9 Lat:33 SizeLat:12 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)261; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void262;263; AVX2-LABEL: 'reduce_f32_fast'264; AVX2-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)265; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:6 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)266; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:12 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)267; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:18 SizeLat:6 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)268; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:7 Lat:23 SizeLat:8 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)269; AVX2-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:33 SizeLat:12 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)270; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void271;272; AVX512-LABEL: 'reduce_f32_fast'273; AVX512-NEXT: Cost Model: Found costs of 0 for: %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)274; AVX512-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:7 SizeLat:2 for: %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)275; AVX512-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:14 SizeLat:4 for: %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)276; AVX512-NEXT: Cost Model: Found costs of RThru:6 CodeSize:6 Lat:19 SizeLat:6 for: %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)277; AVX512-NEXT: Cost Model: Found costs of RThru:8 CodeSize:8 Lat:24 SizeLat:8 for: %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)278; AVX512-NEXT: Cost Model: Found costs of RThru:9 CodeSize:9 Lat:28 SizeLat:9 for: %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)279; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void280;281 %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float %arg, <1 x float> undef)282 %V2 = call fast float @llvm.vector.reduce.fmul.v2f32(float %arg, <2 x float> undef)283 %V4 = call fast float @llvm.vector.reduce.fmul.v4f32(float %arg, <4 x float> undef)284 %V8 = call fast float @llvm.vector.reduce.fmul.v8f32(float %arg, <8 x float> undef)285 %V16 = call fast float @llvm.vector.reduce.fmul.v16f32(float %arg, <16 x float> undef)286 %V32 = call fast float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)287 ret void288}289 290declare double @llvm.vector.reduce.fmul.v1f64(double, <1 x double>)291declare double @llvm.vector.reduce.fmul.v2f64(double, <2 x double>)292declare double @llvm.vector.reduce.fmul.v4f64(double, <4 x double>)293declare double @llvm.vector.reduce.fmul.v8f64(double, <8 x double>)294declare double @llvm.vector.reduce.fmul.v16f64(double, <16 x double>)295 296declare float @llvm.vector.reduce.fmul.v1f32(float, <1 x float>)297declare float @llvm.vector.reduce.fmul.v2f32(float, <2 x float>)298declare float @llvm.vector.reduce.fmul.v4f32(float, <4 x float>)299declare float @llvm.vector.reduce.fmul.v8f32(float, <8 x float>)300declare float @llvm.vector.reduce.fmul.v16f32(float, <16 x float>)301declare float @llvm.vector.reduce.fmul.v32f32(float, <32 x float>)302