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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=gvn < %s | FileCheck %s3 4@u = global i32 5, align 45@w = global i32 10, align 46 7define i32 @test_load() {8; CHECK-LABEL: @test_load(9; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 410; CHECK-NEXT: ret i32 [[LV]]11;12 %l1 = load atomic i32, ptr @w unordered, align 413 %lv = load volatile i32, ptr @u, align 414 %l2 = load atomic i32, ptr @w unordered, align 415 %res.1 = sub i32 %l1, %l216 %res = add i32 %res.1, %lv17 ret i32 %res18}19 20define i32 @test_load_with_acquire_load() {21; CHECK-LABEL: @test_load_with_acquire_load(22; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w acquire, align 423; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 424; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w acquire, align 425; CHECK-NEXT: [[RES_1:%.*]] = sub i32 [[L1]], [[L2]]26; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES_1]], [[LV]]27; CHECK-NEXT: ret i32 [[RES]]28;29 %l1 = load atomic i32, ptr @w acquire, align 430 %lv = load volatile i32, ptr @u, align 431 %l2 = load atomic i32, ptr @w acquire, align 432 %res.1 = sub i32 %l1, %l233 %res = add i32 %res.1, %lv34 ret i32 %res35}36 37define i32 @test_load_with_seq_cst_load() {38; CHECK-LABEL: @test_load_with_seq_cst_load(39; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w seq_cst, align 440; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 441; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w seq_cst, align 442; CHECK-NEXT: [[RES_1:%.*]] = sub i32 [[L1]], [[L2]]43; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES_1]], [[LV]]44; CHECK-NEXT: ret i32 [[RES]]45;46 %l1 = load atomic i32, ptr @w seq_cst, align 447 %lv = load volatile i32, ptr @u, align 448 %l2 = load atomic i32, ptr @w seq_cst, align 449 %res.1 = sub i32 %l1, %l250 %res = add i32 %res.1, %lv51 ret i32 %res52}53 54define i32 @test_store(i32 %x) {55; CHECK-LABEL: @test_store(56; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 457; CHECK-NEXT: ret i32 058;59 %l1 = load atomic i32, ptr @w unordered, align 460 store volatile i32 %x, ptr @u, align 461 %l2 = load atomic i32, ptr @w unordered, align 462 %res = sub i32 %l1, %l263 ret i32 %res64}65 66define i32 @test_store_with_acquire_load(i32 %x) {67; CHECK-LABEL: @test_store_with_acquire_load(68; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w acquire, align 469; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 470; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w acquire, align 471; CHECK-NEXT: [[RES:%.*]] = sub i32 [[L1]], [[L2]]72; CHECK-NEXT: ret i32 [[RES]]73;74 %l1 = load atomic i32, ptr @w acquire, align 475 store volatile i32 %x, ptr @u, align 476 %l2 = load atomic i32, ptr @w acquire, align 477 %res = sub i32 %l1, %l278 ret i32 %res79}80 81define i32 @test_store_with_seq_cst_load(i32 %x) {82; CHECK-LABEL: @test_store_with_seq_cst_load(83; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w seq_cst, align 484; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 485; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w seq_cst, align 486; CHECK-NEXT: [[RES:%.*]] = sub i32 [[L1]], [[L2]]87; CHECK-NEXT: ret i32 [[RES]]88;89 %l1 = load atomic i32, ptr @w seq_cst, align 490 store volatile i32 %x, ptr @u, align 491 %l2 = load atomic i32, ptr @w seq_cst, align 492 %res = sub i32 %l1, %l293 ret i32 %res94}95