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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -loop-reduce -S < %s | FileCheck %s3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"5target triple = "x86_64-unknown-linux-gnu"6 7define void @test() {8; CHECK-LABEL: define void @test() {9; CHECK-NEXT: bb:10; CHECK-NEXT: br label [[BB3:%.*]]11; CHECK: bb3:12; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB7:%.*]] ], [ 0, [[BB:%.*]] ]13; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB7]] ], [ 16, [[BB]] ]14; CHECK-NEXT: br label [[BB4:%.*]]15; CHECK: bb4:16; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[BB6:%.*]] ], [ [[LSR_IV1]], [[BB3]] ]17; CHECK-NEXT: br i1 true, label [[BB7]], label [[BB6]]18; CHECK: bb6:19; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], 26843545620; CHECK-NEXT: br label [[BB4]]21; CHECK: bb7:22; CHECK-NEXT: [[MUL9:%.*]] = mul i32 [[LSR_IV3]], [[LSR_IV3]]23; CHECK-NEXT: [[MUL10:%.*]] = mul i32 [[MUL9]], [[LSR_IV3]]24; CHECK-NEXT: call void @foo(i32 [[MUL10]])25; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[MUL10]] to i6426; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 3227; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], [[LSR_IV]]28; CHECK-NEXT: br label [[BB3]]29;30bb:31 br label %bb332 33bb3: ; preds = %bb7, %bb34 %phi = phi i64 [ 0, %bb ], [ %add11, %bb7 ]35 br label %bb436 37bb4: ; preds = %bb6, %bb338 %phi5 = phi i32 [ 0, %bb3 ], [ %add, %bb6 ]39 br i1 true, label %bb7, label %bb640 41bb6: ; preds = %bb442 %add = add i32 %phi5, 843 br label %bb444 45bb7: ; preds = %bb446 %shl = shl i32 %phi5, 2547 %mul = mul i64 %phi, %phi48 %trunc = trunc i64 %mul to i3249 %add8 = add i32 %shl, %trunc50 %mul9 = mul i32 %add8, %add851 %mul10 = mul i32 %mul9, %add852 call void @foo(i32 %mul10)53 %sext = sext i32 %mul10 to i6454 %add11 = add i64 %phi, 455 br label %bb356}57 58declare void @foo(i32)59 60