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1# NOTE: This file is Generic MIR translation of test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll test file2# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s3# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s4---5name: readfirstlane6body: |7 bb.1:8 ; CHECK-LABEL: MachineUniformityInfo for function: @readfirstlane9 ; CHECK: DIVERGENT: %{{[0-9]+}}10 ; CHECK-SAME:llvm.amdgcn.workitem.id.x11 ; CHECK-NOT: DIVERGENT: {{.*}}llvm.amdgcn.readfirstlane12 %6:_(p1) = G_IMPLICIT_DEF13 %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)14 %5:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %4(s32)15 G_STORE %5(s32), %6(p1) :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)16 S_ENDPGM 017...18---19name: icmp20body: |21 bb.1:22 liveins: $sgpr4_sgpr523 ; CHECK-LABEL: MachineUniformityInfo for function: @icmp24 ; CHECK-NEXT: ALL VALUES UNIFORM25 26 %3:_(p4) = COPY $sgpr4_sgpr527 %13:_(s32) = G_CONSTANT i32 028 %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)29 %8:_(s32) = G_LOAD %7(p4) :: (dereferenceable invariant load (s32), align 16, addrspace 4)30 %9:_(s64) = G_CONSTANT i64 831 %10:_(p4) = G_PTR_ADD %7, %9(s64)32 %11:_(p1) = G_LOAD %10(p4) :: (dereferenceable invariant load (p1), addrspace 4)33 %12:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %8(s32), %13(s32), 3334 G_STORE %12(s64), %11(p1) :: (volatile store (s64) , addrspace 1)35 S_ENDPGM 036 37...38---39name: fcmp40body: |41 bb.1:42 liveins: $sgpr4_sgpr543 ; CHECK-LABEL: MachineUniformityInfo for function: @fcmp44 ; CHECK-NEXT: ALL VALUES UNIFORM45 46 %3:_(p4) = COPY $sgpr4_sgpr547 %10:_(s32) = G_CONSTANT i32 048 %12:_(s32) = G_CONSTANT i32 149 %16:_(p1) = G_IMPLICIT_DEF50 %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)51 %8:_(<2 x s32>) = G_LOAD %7(p4) :: (dereferenceable invariant load (<2 x s32>) , align 16, addrspace 4)52 %9:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %10(s32)53 %11:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %12(s32)54 %13:_(s64) = G_CONSTANT i64 455 %14:_(p4) = G_PTR_ADD %7, %13(s64)56 %15:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %9(s32), %11(s32), 3357 G_STORE %15(s64), %16(p1) :: (volatile store (s64) into `ptr addrspace(1) undef`, addrspace 1)58 S_ENDPGM 059 60...61---62name: ballot63body: |64 bb.1:65 liveins: $sgpr4_sgpr566 ; CHECK-LABEL: MachineUniformityInfo for function: @ballot67 ; CHECK-NEXT: ALL VALUES UNIFORM68 69 %2:_(p4) = COPY $sgpr4_sgpr570 %10:_(p1) = G_IMPLICIT_DEF71 %6:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)72 %7:_(s32) = G_LOAD %6(p4) :: (dereferenceable invariant load (s32), align 16, addrspace 4)73 %8:_(s1) = G_TRUNC %7(s32)74 %9:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), %8(s1)75 G_STORE %9(s64), %10(p1) :: (volatile store (s64) into `ptr addrspace(1) undef`, addrspace 1)76 S_ENDPGM 077 78...79---80name: asm_sgpr81registers:82 - { id: 0, class: _, preferred-register: '' }83 - { id: 1, class: sreg_32, preferred-register: '' }84 - { id: 2, class: vgpr_32, preferred-register: '' }85 - { id: 3, class: _, preferred-register: '' }86body: |87 bb.0:88 liveins: $vgpr089 ; CHECK-LABEL: MachineUniformityInfo for function: @asm_sgpr90 ; CHECK-NOT: DIVERGENT: %191 92 %0:_(s32) = COPY $vgpr093 %2:vgpr_32 = COPY %0(s32)94 INLINEASM &"; def $0, $1", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835017 /* reguse:VGPR_32 */, %295 %3:_(s32) = COPY %196 $vgpr0 = COPY %3(s32)97 SI_RETURN implicit $vgpr098 99...100 101---102name: asm_mixed_sgpr_vgpr103registers:104 - { id: 0, class: _, preferred-register: '' }105 - { id: 1, class: sreg_32, preferred-register: '' }106 - { id: 2, class: vgpr_32, preferred-register: '' }107 - { id: 3, class: vgpr_32, preferred-register: '' }108 - { id: 4, class: _, preferred-register: '' }109 - { id: 5, class: _, preferred-register: '' }110 - { id: 6, class: _, preferred-register: '' }111liveins: []112frameInfo:113body: |114 bb.0:115 liveins: $vgpr0116 ; CHECK-LABEL: MachineUniformityInfo for function: @asm_mixed_sgpr_vgpr117 ; CHECK: DIVERGENT: %0:118 ; CHECK: DIVERGENT: %3:119 ; CHECK-NOT: DIVERGENT: %1:120 ; CHECK: DIVERGENT: %2:121 ; CHECK-NOT: DIVERGENT: %4:122 ; CHECK: DIVERGENT: %5:123 %0:_(s32) = COPY $vgpr0124 %6:_(p1) = G_IMPLICIT_DEF125 %3:vgpr_32 = COPY %0(s32)126 INLINEASM &"; def $0, $1, $2", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835018 /* regdef:VGPR_32 */, def %2, 1835017 /* reguse:VGPR_32 */, %3127 %4:_(s32) = COPY %1128 %5:_(s32) = COPY %2129 G_STORE %5(s32), %6(p1) :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)130 SI_RETURN131 132...133