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1# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s2# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s3# CHECK-LABEL: MachineUniformityInfo for function: @divergent_cycle_14# CHECK-NEXT: CYCLES ASSUMED DIVERGENT:5# CHECK-NEXT: depth=1: entries(bb.3 bb.1) bb.4 bb.26# CHECK-NEXT: CYCLES WITH DIVERGENT EXIT:7# CHECK-NEXT: depth=2: entries(bb.4 bb.1) bb.28# CHECK-NEXT: depth=1: entries(bb.3 bb.1) bb.4 bb.29 10 11 12---13name: divergent_cycle_114tracksRegLiveness: true15body: |16 bb.0:17 successors: %bb.1, %bb.318 %0:_(s32) = G_CONSTANT i32 019 %1:_(s32) = G_CONSTANT i32 120 21 %2:_(s32) = G_IMPLICIT_DEF22 %3:_(s32) = G_IMPLICIT_DEF23 24 %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)25 %6:_(s1) = G_ICMP intpred(slt), %2(s32), %0(s32) ;uniform condition26 %7:_(s1) = G_ICMP intpred(eq), %4(s32), %0 ;divergent condition27 G_BRCOND %6(s1), %bb.128 G_BR %bb.329 30 bb.1:31 successors: %bb.232 33 ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.0, %{{[0-9]*}}:_(s32), %bb.434 %8:_(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.435 %9:_(s32) = G_ADD %3(s32), %1(s32)36 G_BR %bb.237 38 bb.2:39 successors: %bb.3, %bb.440 41 %13:_(s32) = G_ADD %3(s32), %1(s32)42 G_BRCOND %7(s1), %bb.443 G_BR %bb.344 45 bb.3:46 successors: %bb.447 48 %14:_(s32) = G_ADD %3(s32), %1(s32)49 G_BR %bb.450 bb.4:51 successors: %bb.5, %bb.152 53 ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.2, %{{[0-9]*}}:_(s32), %bb.354 %15:_(s32) = G_PHI %13(s32), %bb.2, %14(s32), %bb.355 %16:_(s32) = G_ADD %3(s32), %1(s32)56 G_BRCOND %6(s1), %bb.557 G_BR %bb.158 59 bb.5:60 %17:_(s32) = G_ADD %3(s32), %1(s32)61 S_ENDPGM 062...63 64# CHECK-LABEL: MachineUniformityInfo for function: @uniform_cycle_165---66name: uniform_cycle_167tracksRegLiveness: true68body: |69 bb.0:70 successors: %bb.1, %bb.571 %0:_(s32) = G_CONSTANT i32 072 %1:_(s32) = G_CONSTANT i32 173 74 %2:_(s32) = G_IMPLICIT_DEF75 %3:_(s32) = G_IMPLICIT_DEF76 77 %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)78 %6:_(s1) = G_ICMP intpred(slt), %2(s32), %0(s32) ;uniform condition79 %7:_(s1) = G_ICMP intpred(eq), %4(s32), %0 ;divergent condition80 G_BRCOND %6(s1), %bb.181 G_BR %bb.582 83 bb.1:84 successors: %bb.285 86 ; CHECK-NOT: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.0, %{{[0-9]*}}:_(s32), %bb.487 %8:_(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.588 %9:_(s32) = G_ADD %3(s32), %1(s32)89 G_BR %bb.290 91 bb.2:92 successors: %bb.3, %bb.493 94 %13:_(s32) = G_ADD %3(s32), %1(s32)95 G_BRCOND %7(s1), %bb.496 G_BR %bb.397 98 bb.3:99 successors: %bb.4100 101 %14:_(s32) = G_ADD %3(s32), %1(s32)102 G_BR %bb.4103 bb.4:104 successors: %bb.6, %bb.5105 106 ; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.2, %{{[0-9]*}}:_(s32), %bb.3107 %15:_(s32) = G_PHI %13(s32), %bb.2, %14(s32), %bb.3108 %16:_(s32) = G_ADD %3(s32), %1(s32)109 G_BRCOND %6(s1), %bb.6110 G_BR %bb.5111 112 bb.5:113 successors: %bb.1114 %18:_(s32) = G_ADD %3(s32), %1(s32)115 G_BR %bb.1116 bb.6:117 %17:_(s32) = G_ADD %3(s32), %1(s32)118 S_ENDPGM 0119...120