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1# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s2# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s3# loads from flat non uniform4---5name: flatloads6tracksRegLiveness: true7machineFunctionInfo:8 isEntryFunction: true9 10body: |11 bb.0:12 ; CHECK-LABEL: MachineUniformityInfo for function: @flatloads13 ; CHECK: DIVERGENT: %114 ; CHECK-NOT: DIVERGENT: %215 %0:vreg_64 = IMPLICIT_DEF16 %1:vgpr_32(s32) = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))17 %2:vgpr_32(s32) = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)18 %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %1(s32), implicit $exec19 S_ENDPGM 020...21 22# loads from scratch non uniform23---24name: scratchloads25tracksRegLiveness: true26machineFunctionInfo:27 isEntryFunction: true28 29body: |30 bb.0:31 ; CHECK-LABEL: MachineUniformityInfo for function: @scratchloads32 ; CHECK: DIVERGENT: %133 %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec34 %1:vgpr_32 = SCRATCH_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 5)35 S_ENDPGM 036...37 38# Global load39---40name: globalloads41tracksRegLiveness: true42machineFunctionInfo:43 isEntryFunction: true44 45body: |46 bb.0:47 ; CHECK-LABEL: MachineUniformityInfo for function: @globalloads48 ; CHECK: DIVERGENT: %249 ; CHECK-NOT: DIVERGENT: %350 %0:vreg_64 = IMPLICIT_DEF51 %1:vreg_64 = IMPLICIT_DEF52 %2:vgpr_32(s32) = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))53 %3:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, implicit $exec :: (load (s64), addrspace 1)54 %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2(s32), implicit $exec55 S_ENDPGM 056...57 58# FIXME:: ADDTID might instruction incorrectly marked uniform59---60name: dsreads61tracksRegLiveness: true62machineFunctionInfo:63 isEntryFunction: true64 65body: |66 bb.0:67 ; CHECK-LABEL: MachineUniformityInfo for function: @dsreads68 ; CHECK-NEXT: ALL VALUES UNIFORM69 %0:vreg_64 = IMPLICIT_DEF70 $m0 = S_MOV_B32 071 %1:vgpr_32 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec72 S_ENDPGM 073...74 75# copy source == $sgpr => uniform, $vgpr => divergent76---77name: sgprcopy78tracksRegLiveness: true79machineFunctionInfo:80 isEntryFunction: true81body: |82 bb.0:83 ; CHECK-LABEL: MachineUniformityInfo for function: @sgprcopy84 ; CHECK: DIVERGENT: %285 liveins: $sgpr0,$sgpr1,$vgpr086 %0:sgpr_32 = COPY $sgpr087 %1:vgpr_32 = COPY $sgpr188 %2:vgpr_32 = COPY $vgpr089 S_ENDPGM 090...91 92# writelane is not uniform93---94name: writelane95machineFunctionInfo:96 isEntryFunction: true97body: |98 bb.0:99 ; CHECK-LABEL: MachineUniformityInfo for function: @writelane100 ; CHECK: DIVERGENT: %4101 102 ; Note how %5 is the result of a vector compare, but it is reported as103 ; uniform because it is stored in an sreg.104 ; CHECK-NOT: DIVERGENT: %5105 106 %0:vgpr_32 = IMPLICIT_DEF107 %1:vgpr_32 = IMPLICIT_DEF108 %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec109 %3:sgpr_32 = V_READLANE_B32 %1, 0, implicit $exec110 $sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec111 $sgpr1 = V_READLANE_B32 $vgpr1, $sgpr0, implicit $exec112 113 %4:vgpr_32 = V_WRITELANE_B32 0, 0, %0, implicit $exec114 %5:sreg_64 = V_CMP_EQ_U32_e64 %0, %4, implicit $exec115 S_CBRANCH_VCCZ %bb.1, implicit $vcc116 117 bb.1:118 %16:vgpr_32 = IMPLICIT_DEF119 S_ENDPGM 0120...121# Directly reading physical vgpr not uniform122---123name: physicalreg124tracksRegLiveness: true125body: |126 bb.0:127 ; CHECK-LABEL: MachineUniformityInfo for function: @physicalreg128 ; CHECK: DIVERGENT: %0129 ; CHECK: DIVERGENT: %1130 ; CHECK: DIVERGENT: %2131 ; CHECK: DIVERGENT: %3132 ; CHECK: DIVERGENT: %4133 ; CHECK-NOT: DIVERGENT134 ; CHECK: DIVERGENT: %5135 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5136 %0:vgpr_32 = COPY $vgpr0137 %1:vgpr_32 = COPY $vgpr1138 %2:vgpr_32 = V_AND_B32_e32 %1, $vgpr3, implicit $exec139 %3:vgpr_32 = V_ADD_U32_e32 $vgpr2, $vgpr3, implicit $exec140 %4:vgpr_32 = V_SUB_CO_U32_e32 $vgpr2, $vgpr3, implicit $exec, implicit-def $vcc141 %5:vgpr_32 = V_AND_B32_e32 $vgpr4, $vgpr5, implicit $exec142 S_ENDPGM 0143...144# mbcnt instructions are not uniform145---146name: mbcnt_lo147machineFunctionInfo:148 isEntryFunction: true149body: |150 bb.0:151 ; CHECK-LABEL: MachineUniformityInfo for function: @mbcnt_lo152 ; CHECK: DIVERGENT: %0153 %0:vgpr_32 = V_MBCNT_LO_U32_B32_e64 -1, 0, implicit $exec154 S_ENDPGM 0155...156---157name: mbcnt_hi158machineFunctionInfo:159 isEntryFunction: true160body: |161 bb.0:162 ; CHECK-LABEL: MachineUniformityInfo for function: @mbcnt_hi163 ; CHECK: DIVERGENT: %0164 %0:vgpr_32 = V_MBCNT_HI_U32_B32_e64 -1, 0, implicit $exec165 S_ENDPGM 0166...167