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1# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s2# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s3 4---5# CHECK-LABEL: MachineUniformityInfo for function: @temporal_diverge6name: temporal_diverge7alignment: 18legalized: true9tracksRegLiveness: true10registers:11 - { id: 3, class: _ }12 - { id: 4, class: vgpr_32 }13 - { id: 5, class: sgpr_32 }14 - { id: 6, class: sgpr_32 }15liveins:16 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }17 - { reg: '$vgpr0', virtual-reg: '%4' }18 - { reg: '$sgpr2', virtual-reg: '%5' }19 - { reg: '$sgpr3', virtual-reg: '%6' }20body: |21 bb.1:22 liveins: $sgpr0_sgpr123 24 %15:_(s64) = G_CONSTANT i64 025 26 bb.2:27 successors: %bb.3, %bb.228 29 %11:_(s64) = G_PHI %12(s64), %bb.2, %15(s64), %bb.130 %18:_(s1) = G_CONSTANT i1 false31 %12:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %18(s1), %11(s64)32 ; CHECK: DIVERGENT: SI_LOOP33 SI_LOOP %12(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec34 G_BR %bb.335 36 bb.3:37 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI38 %14:_(s64) = G_PHI %12(s64), %bb.239 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s64)40 S_ENDPGM 041 42...43---44# CHECK-LABEL: MachineUniformityInfo for function: @phi_at_exit45name: phi_at_exit46alignment: 147legalized: true48tracksRegLiveness: true49registers:50 - { id: 3, class: _ }51 - { id: 4, class: vgpr_32 }52 - { id: 5, class: sgpr_32 }53 - { id: 6, class: sgpr_32 }54liveins:55 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }56 - { reg: '$vgpr0', virtual-reg: '%4' }57 - { reg: '$sgpr2', virtual-reg: '%5' }58 - { reg: '$sgpr3', virtual-reg: '%6' }59body: |60 bb.1:61 successors: %bb.2, %bb.362 liveins: $sgpr0_sgpr163 64 %3:_(p4) = COPY $sgpr0_sgpr165 %7:_(p4) = COPY %3(p4)66 %8:_(s64) = G_CONSTANT i64 4067 %9:_(p4) = G_PTR_ADD %7, %8(s64)68 %10:_(s32) = G_LOAD %9(p4) :: (load (s32), addrspace 4)69 %11:_(s32) = G_CONSTANT i32 070 %12:_(s1) = G_ICMP intpred(sge), %10(s32), %1171 G_BRCOND %12(s1), %bb.372 G_BR %bb.273 74 bb.2:75 %24:_(s64) = G_CONSTANT i64 076 %14:_(s1) = G_CONSTANT i1 false77 G_BR %bb.478 79 bb.3:80 G_BR %bb.681 82 bb.4:83 successors: %bb.5, %bb.484 85 %15:_(s64) = G_PHI %24(s64), %bb.2, %16(s64), %bb.486 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %15(s64)87 ; CHECK: DIVERGENT: SI_LOOP88 SI_LOOP %16(s64), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec89 G_BR %bb.590 91 bb.5:92 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI93 %18:_(s64) = G_PHI %16(s64), %bb.494 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64)95 G_BR %bb.396 97 bb.6:98 S_ENDPGM 099 100...101---102# CHECK-LABEL: MachineUniformityInfo for function: @phi_after_exit103name: phi_after_exit104alignment: 1105legalized: true106tracksRegLiveness: true107registers:108 - { id: 3, class: _ }109 - { id: 4, class: vgpr_32 }110 - { id: 5, class: sgpr_32 }111 - { id: 6, class: sgpr_32 }112liveins:113 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }114 - { reg: '$vgpr0', virtual-reg: '%4' }115 - { reg: '$sgpr2', virtual-reg: '%5' }116 - { reg: '$sgpr3', virtual-reg: '%6' }117body: |118 bb.1:119 successors: %bb.2, %bb.3120 liveins: $sgpr0_sgpr1121 122 %3:_(p4) = COPY $sgpr0_sgpr1123 %7:_(p4) = COPY %3(p4)124 %8:_(s64) = G_CONSTANT i64 40125 %9:_(p4) = G_PTR_ADD %7, %8(s64)126 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4)127 %11:_(s32) = G_CONSTANT i32 0128 %12:_(s1) = G_ICMP intpred(sge), %10(s32), %11129 G_BRCOND %12(s1), %bb.3130 G_BR %bb.2131 132 bb.2:133 %24:_(s64) = G_CONSTANT i64 0134 %14:_(s1) = G_CONSTANT i1 false135 G_BR %bb.4136 137 bb.3:138 G_BR %bb.6139 140 bb.4:141 successors: %bb.5, %bb.4142 143 %15:_(s64) = G_PHI %24(s64), %bb.2, %16(s64), %bb.4144 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %15(s64)145 ; CHECK: DIVERGENT: SI_LOOP146 SI_LOOP %16(s64), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec147 G_BR %bb.5148 149 bb.5:150 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI151 %18:_(s64) = G_PHI %16(s64), %bb.4152 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64)153 G_BR %bb.3154 155 bb.6:156 S_ENDPGM 0157 158...159---160# CHECK-LABEL: MachineUniformityInfo for function: @temporal_diverge_inloop161name: temporal_diverge_inloop162alignment: 1163legalized: true164tracksRegLiveness: true165registers:166 - { id: 3, class: _ }167 - { id: 4, class: vgpr_32 }168 - { id: 5, class: sgpr_32 }169 - { id: 6, class: sgpr_32 }170liveins:171 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }172 - { reg: '$vgpr0', virtual-reg: '%4' }173 - { reg: '$sgpr2', virtual-reg: '%5' }174 - { reg: '$sgpr3', virtual-reg: '%6' }175body: |176 bb.1:177 liveins: $sgpr0_sgpr1178 179 %3:_(p4) = COPY $sgpr0_sgpr1180 %7:_(p4) = COPY %3(p4)181 %8:_(s64) = G_CONSTANT i64 40182 %9:_(p4) = G_PTR_ADD %7, %8(s64)183 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4)184 %12:_(s32) = G_CONSTANT i32 0185 %13:_(s1) = G_ICMP intpred(slt), %10(s32), %12186 187 bb.2:188 %25:_(s64) = G_CONSTANT i64 0189 190 bb.3:191 successors: %bb.4, %bb.3192 193 %15:_(s64) = G_PHI %25(s64), %bb.2, %16(s64), %bb.3194 %24:_(s1) = G_CONSTANT i1 false195 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %15(s64)196 ; CHECK: DIVERGENT: SI_LOOP197 SI_LOOP %16(s64), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec198 G_BR %bb.4199 200 bb.4:201 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI202 successors: %bb.5, %bb.2203 204 %18:_(s64) = G_PHI %16(s64), %bb.3205 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64)206 G_BRCOND %13(s1), %bb.2207 G_BR %bb.5208 209 bb.5:210 S_ENDPGM 0211 212...213---214# CHECK-LABEL: MachineUniformityInfo for function: @temporal_uniform_indivloop215name: temporal_uniform_indivloop216alignment: 1217legalized: true218tracksRegLiveness: true219registers:220 - { id: 3, class: _ }221 - { id: 4, class: vgpr_32 }222 - { id: 5, class: sgpr_32 }223 - { id: 6, class: sgpr_32 }224liveins:225 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }226 - { reg: '$vgpr0', virtual-reg: '%4' }227 - { reg: '$sgpr2', virtual-reg: '%5' }228 - { reg: '$sgpr3', virtual-reg: '%6' }229body: |230 bb.1:231 liveins: $sgpr0_sgpr1232 233 %3:_(p4) = COPY $sgpr0_sgpr1234 %19:_(s64) = G_CONSTANT i64 0235 %7:_(p4) = COPY %3(p4)236 %8:_(s64) = G_CONSTANT i64 40237 %9:_(p4) = G_PTR_ADD %7, %8(s64)238 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4)239 %12:_(s32) = G_CONSTANT i32 0240 %13:_(s1) = G_ICMP intpred(sge), %10(s32), %12241 242 bb.2:243 %15:_(s64) = G_PHI %16(s64), %bb.4, %19(s64), %bb.1244 %24:_(s1) = G_CONSTANT i1 true245 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %15(s64)246 247 bb.3:248 successors: %bb.4, %bb.3249 250 G_BRCOND %13(s1), %bb.3251 G_BR %bb.4252 253 bb.4:254 successors: %bb.5, %bb.2255 256 ; CHECK: DIVERGENT: SI_LOOP257 SI_LOOP %16(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec258 G_BR %bb.5259 260 bb.5:261 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI262 %18:_(s64) = G_PHI %16(s64), %bb.4263 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64)264 S_ENDPGM 0265 266...267---268# CHECK-LABEL: MachineUniformityInfo for function: @temporal_diverge_loopuser269name: temporal_diverge_loopuser270alignment: 1271legalized: true272tracksRegLiveness: true273registers:274 - { id: 3, class: _ }275 - { id: 4, class: vgpr_32 }276 - { id: 5, class: sgpr_32 }277 - { id: 6, class: sgpr_32 }278liveins:279 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }280 - { reg: '$vgpr0', virtual-reg: '%4' }281 - { reg: '$sgpr2', virtual-reg: '%5' }282 - { reg: '$sgpr3', virtual-reg: '%6' }283body: |284 bb.1:285 liveins: $sgpr0_sgpr1286 287 %3:_(p4) = COPY $sgpr0_sgpr1288 %19:_(s64) = G_CONSTANT i64 0289 290 bb.2:291 successors: %bb.3, %bb.2292 293 %10:_(s64) = G_PHI %11(s64), %bb.2, %19(s64), %bb.1294 %24:_(s1) = G_CONSTANT i1 false295 %11:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %10(s64)296 ; CHECK: DIVERGENT: SI_LOOP297 SI_LOOP %11(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec298 G_BR %bb.3299 300 bb.3:301 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI302 ; CHECK-NOT: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI303 %13:_(s64) = G_PHI %11(s64), %bb.2304 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %13(s64)305 %14:_(p4) = COPY %3(p4)306 %15:_(s64) = G_CONSTANT i64 40307 %16:_(p4) = G_PTR_ADD %14, %15(s64)308 %17:_(s32) = G_LOAD %16(p4) :: (dereferenceable invariant load (s32), addrspace 4)309 %25:_(s32) = G_CONSTANT i32 0310 %18:_(s1) = G_ICMP intpred(slt), %17(s32), %25311 312 bb.4:313 successors: %bb.5, %bb.4314 315 G_BRCOND %18(s1), %bb.4316 G_BR %bb.5317 318 bb.5:319 S_ENDPGM 0320 321...322---323# CHECK-LABEL: MachineUniformityInfo for function: @temporal_diverge_loopuser_nested324name: temporal_diverge_loopuser_nested325alignment: 1326legalized: true327tracksRegLiveness: true328registers:329 - { id: 3, class: _ }330 - { id: 4, class: vgpr_32 }331 - { id: 5, class: sgpr_32 }332 - { id: 6, class: sgpr_32 }333liveins:334 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }335 - { reg: '$vgpr0', virtual-reg: '%4' }336 - { reg: '$sgpr2', virtual-reg: '%5' }337 - { reg: '$sgpr3', virtual-reg: '%6' }338body: |339 bb.1:340 liveins: $sgpr0_sgpr1341 342 %3:_(p4) = COPY $sgpr0_sgpr1343 %7:_(p4) = COPY %3(p4)344 %8:_(s64) = G_CONSTANT i64 40345 %9:_(p4) = G_PTR_ADD %7, %8(s64)346 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4)347 %12:_(s32) = G_CONSTANT i32 0348 %13:_(s1) = G_ICMP intpred(sge), %10(s32), %12349 350 bb.2:351 %23:_(s64) = G_CONSTANT i64 0352 353 bb.3:354 successors: %bb.4, %bb.3355 356 %15:_(s64) = G_PHI %23(s64), %bb.2, %16(s64), %bb.3357 %25:_(s1) = G_CONSTANT i1 false358 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %25(s1), %15(s64)359 ; CHECK: DIVERGENT: SI_LOOP360 SI_LOOP %16(s64), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec361 G_BR %bb.4362 363 bb.4:364 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI365 %18:_(s64) = G_PHI %16(s64), %bb.3366 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64)367 368 bb.5:369 370 bb.6:371 successors: %bb.8, %bb.5372 373 G_BRCOND %13(s1), %bb.8374 G_BR %bb.5375 376 bb.7:377 S_ENDPGM 0378 379 bb.8:380 successors: %bb.7, %bb.2381 382 %24:_(s1) = G_CONSTANT i1 false383 G_BRCOND %24(s1), %bb.7384 G_BR %bb.2385 386...387