112 lines · plain
1; RUN: opt -mtriple amdgcn-unknown-amdhsa -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s2 3declare i32 @gf2(i32)4declare i32 @gf1(i32)5 6define void @tw1(ptr addrspace(4) noalias nocapture readonly %A, ptr addrspace(4) noalias nocapture %B) local_unnamed_addr #2 {7; CHECK: for function 'tw1':8; CHECK-DAG: DIVERGENT: ptr addrspace(4) %A9; CHECK-DAG: DIVERGENT: ptr addrspace(4) %B10entry:11; CHECK: DIVERGENT: %call = tail call i32 @gf2(i32 0) #012; CHECK: DIVERGENT: %cmp = icmp ult i32 %call, 1613; CHECK: DIVERGENT: br i1 %cmp, label %if.then, label %new_exit14 %call = tail call i32 @gf2(i32 0) #315 %cmp = icmp ult i32 %call, 1616 br i1 %cmp, label %if.then, label %new_exit17 18if.then:19; CHECK: DIVERGENT: %call1 = tail call i32 @gf1(i32 0) #020; CHECK: DIVERGENT: %arrayidx = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %call121; CHECK: DIVERGENT: %0 = load i32, ptr addrspace(4) %arrayidx, align 422; CHECK: DIVERGENT: %cmp225 = icmp sgt i32 %0, 023; CHECK: DIVERGENT: %arrayidx10 = getelementptr inbounds i32, ptr addrspace(4) %B, i32 %call124; CHECK: DIVERGENT: br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge25 %call1 = tail call i32 @gf1(i32 0) #426 %arrayidx = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %call127 %0 = load i32, ptr addrspace(4) %arrayidx, align 428 %cmp225 = icmp sgt i32 %0, 029 %arrayidx10 = getelementptr inbounds i32, ptr addrspace(4) %B, i32 %call130 br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge31 32while.body.preheader:33 br label %while.body34 35if.then.while.end_crit_edge:36; CHECK: DIVERGENT: %.pre = load i32, ptr addrspace(4) %arrayidx10, align 437 %.pre = load i32, ptr addrspace(4) %arrayidx10, align 438 br label %while.end39 40while.body:41; CHECK-NOT: DIVERGENT: %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ]42; CHECK: DIVERGENT: %call3 = tail call i32 @gf1(i32 0) #043; CHECK: DIVERGENT: %cmp4 = icmp ult i32 %call3, 1044; CHECK: DIVERGENT: %arrayidx6 = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %i.02645; CHECK: DIVERGENT: %1 = load i32, ptr addrspace(4) %arrayidx6, align 446; CHECK: DIVERGENT: br i1 %cmp4, label %if.then5, label %if.else47 %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ]48 %call3 = tail call i32 @gf1(i32 0) #449 %cmp4 = icmp ult i32 %call3, 1050 %arrayidx6 = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %i.02651 %1 = load i32, ptr addrspace(4) %arrayidx6, align 452 br i1 %cmp4, label %if.then5, label %if.else53 54if.then5:55; CHECK: DIVERGENT: %mul = shl i32 %1, 156; CHECK: DIVERGENT: %2 = load i32, ptr addrspace(4) %arrayidx10, align 457; CHECK: DIVERGENT: %add = add nsw i32 %2, %mul58 %mul = shl i32 %1, 159 %2 = load i32, ptr addrspace(4) %arrayidx10, align 460 %add = add nsw i32 %2, %mul61 br label %if.end62 63if.else:64; CHECK: DIVERGENT: %mul9 = shl i32 %1, 265; CHECK: DIVERGENT: %3 = load i32, ptr addrspace(4) %arrayidx10, align 466; CHECK: DIVERGENT: %add11 = add nsw i32 %3, %mul967 %mul9 = shl i32 %1, 268 %3 = load i32, ptr addrspace(4) %arrayidx10, align 469 %add11 = add nsw i32 %3, %mul970 br label %if.end71 72if.end:73; CHECK: DIVERGENT: %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ]74; CHECK: DIVERGENT: store i32 %storemerge, ptr addrspace(4) %arrayidx10, align 475; CHECK-NOT: DIVERGENT: %inc = add nuw nsw i32 %i.026, 176; CHECK: DIVERGENT: %exitcond = icmp ne i32 %inc, %077; CHECK: DIVERGENT: br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit78 %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ]79 store i32 %storemerge, ptr addrspace(4) %arrayidx10, align 480 %inc = add nuw nsw i32 %i.026, 181 %exitcond = icmp ne i32 %inc, %082 br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit83 84if.end.while.body_crit_edge:85 br label %while.body86 87while.end.loopexit:88; CHECK: DIVERGENT: %storemerge.lcssa = phi i32 [ %storemerge, %if.end ]89 %storemerge.lcssa = phi i32 [ %storemerge, %if.end ]90 br label %while.end91 92while.end:93; CHECK: DIVERGENT: %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ]94; CHECK: DIVERGENT: %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ]95; CHECK: DIVERGENT: %sub = sub nsw i32 %4, %i.0.lcssa96; CHECK: DIVERGENT: store i32 %sub, ptr addrspace(4) %arrayidx10, align 497 %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ]98 %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ]99 %sub = sub nsw i32 %4, %i.0.lcssa100 store i32 %sub, ptr addrspace(4) %arrayidx10, align 4101 br label %new_exit102 103new_exit:104 ret void105}106 107attributes #0 = { nounwind readnone }108attributes #1 = { nounwind readnone }109attributes #2 = { nounwind readnone }110attributes #3 = { nounwind readnone }111attributes #4 = { nounwind readnone }112