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1; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=tahiti -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s2; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=gfx908 -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s3; Make sure nothing crashes on targets with or without AGPRs4 5; CHECK-LABEL: for function 'inline_asm_1_sgpr_virtreg_output':6; CHECK-NOT: DIVERGENT7define i32 @inline_asm_1_sgpr_virtreg_output() {8 %sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()9 ret i32 %sgpr10}11 12; CHECK-LABEL: for function 'inline_asm_1_sgpr_physreg_output':13; CHECK-NOT: DIVERGENT14define i32 @inline_asm_1_sgpr_physreg_output() {15 %sgpr = call i32 asm "s_mov_b32 s0, 0", "={s0}"()16 ret i32 %sgpr17}18 19; CHECK-LABEL: for function 'inline_asm_1_vgpr_virtreg_output':20; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()21define i32 @inline_asm_1_vgpr_virtreg_output() {22 %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()23 ret i32 %vgpr24}25 26; CHECK-LABEL: for function 'inline_asm_1_vgpr_physreg_output':27; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()28define i32 @inline_asm_1_vgpr_physreg_output() {29 %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()30 ret i32 %vgpr31}32 33; CHECK-LABEL: for function 'inline_asm_1_agpr_virtreg_output':34; CHECK: DIVERGENT: %vgpr = call i32 asm "; def $0", "=a"()35define i32 @inline_asm_1_agpr_virtreg_output() {36 %vgpr = call i32 asm "; def $0", "=a"()37 ret i32 %vgpr38}39 40; CHECK-LABEL: for function 'inline_asm_1_agpr_physreg_output':41; CHECK: DIVERGENT: %vgpr = call i32 asm "; def a0", "={a0}"()42define i32 @inline_asm_1_agpr_physreg_output() {43 %vgpr = call i32 asm "; def a0", "={a0}"()44 ret i32 %vgpr45}46 47; CHECK-LABEL: for function 'inline_asm_2_sgpr_virtreg_output':48; CHECK-NOT: DIVERGENT49define void @inline_asm_2_sgpr_virtreg_output() {50 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s"()51 %sgpr0 = extractvalue { i32, i32 } %asm, 052 %sgpr1 = extractvalue { i32, i32 } %asm, 153 store i32 %sgpr0, ptr addrspace(1) undef54 store i32 %sgpr1, ptr addrspace(1) undef55 ret void56}57 58; One output is SGPR, one is VGPR. Infer divergent for the aggregate, but uniform on the SGPR extract59; CHECK-LABEL: for function 'inline_asm_sgpr_vgpr_virtreg_output':60; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()61; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 062; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 163define void @inline_asm_sgpr_vgpr_virtreg_output() {64 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()65 %sgpr = extractvalue { i32, i32 } %asm, 066 %vgpr = extractvalue { i32, i32 } %asm, 167 store i32 %sgpr, ptr addrspace(1) undef68 store i32 %vgpr, ptr addrspace(1) undef69 ret void70}71 72; CHECK-LABEL: for function 'inline_asm_vgpr_sgpr_virtreg_output':73; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()74; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 075; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 176define void @inline_asm_vgpr_sgpr_virtreg_output() {77 %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()78 %vgpr = extractvalue { i32, i32 } %asm, 079 %sgpr = extractvalue { i32, i32 } %asm, 180 store i32 %vgpr, ptr addrspace(1) undef81 store i32 %sgpr, ptr addrspace(1) undef82 ret void83}84 85; Have an extra output constraint86; CHECK-LABEL: for function 'multi_sgpr_inline_asm_output_input_constraint':87; CHECK-NOT: DIVERGENT88define void @multi_sgpr_inline_asm_output_input_constraint() {89 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s,s"(i32 1234)90 %sgpr0 = extractvalue { i32, i32 } %asm, 091 %sgpr1 = extractvalue { i32, i32 } %asm, 192 store i32 %sgpr0, ptr addrspace(1) undef93 store i32 %sgpr1, ptr addrspace(1) undef94 ret void95}96 97; CHECK-LABEL: for function 'inline_asm_vgpr_sgpr_virtreg_output_input_constraint':98; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)99; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0100; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1101define void @inline_asm_vgpr_sgpr_virtreg_output_input_constraint() {102 %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)103 %vgpr = extractvalue { i32, i32 } %asm, 0104 %sgpr = extractvalue { i32, i32 } %asm, 1105 store i32 %vgpr, ptr addrspace(1) undef106 store i32 %sgpr, ptr addrspace(1) undef107 ret void108}109