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1; RUN: opt -mtriple amdgcn-- -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s2 3; CHECK: for function 'interp_p1_f16'4; CHECK: DIVERGENT: %p1 = call float @llvm.amdgcn.interp.p1.f165define amdgpu_ps float @interp_p1_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {6main_body:7 %p1 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)8 ret float %p19}10 11; CHECK: for function 'interp_p2_f16'12; CHECK: DIVERGENT: %p2 = call half @llvm.amdgcn.interp.p2.f1613define amdgpu_ps half @interp_p2_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {14main_body:15 %p2 = call half @llvm.amdgcn.interp.p2.f16(float %i, float %j, i32 1, i32 2, i1 0, i32 %m0)16 ret half %p217}18 19; float @llvm.amdgcn.interp.p1.f16(i, attrchan, attr, high, m0)20declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) #021; half @llvm.amdgcn.interp.p1.f16(p1, j, attrchan, attr, high, m0)22declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32) #023declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #024 25attributes #0 = { nounwind readnone }26