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1; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s2 3; CHECK=LABEL: UniformityInfo for function 'basic':4; CHECK: CYCLES ASSUMED DIVERGENT:5; CHECK: depth=1: entries(P T) Q6define amdgpu_kernel void @basic(i32 %a, i32 %b, i32 %c) {7entry:8 %cond.uni = icmp slt i32 %a, 09 %tid = call i32 @llvm.amdgcn.workitem.id.x()10 %cond.div = icmp slt i32 %tid, 011 br i1 %cond.div, label %T, label %P12 13P:14; CHECK: DIVERGENT: %pp.phi =15; CHECK: DIVERGENT: %pp =16 %pp.phi = phi i32 [ %a, %entry], [ %b, %T ]17 %pp = add i32 %b, 118 br label %Q19 20Q:21; CHECK: DIVERGENT: %qq =22; CHECK: DIVERGENT: %qq.div =23 %qq = add i32 %b, 124 %qq.div = add i32 %pp.phi, 125 br i1 %cond.uni, label %T, label %exit26 27T:28; CHECK: DIVERGENT: %t.phi =29; CHECK: DIVERGENT: %tt =30 %t.phi = phi i32 [ %qq, %Q ], [ %a, %entry ]31 %tt = add i32 %b, 132 br label %P33 34exit:35; CHECK-NOT: DIVERGENT: %ee =36 %ee = add i32 %b, 137 ret void38}39 40; CHECK=LABEL: UniformityInfo for function 'nested':41; CHECK: CYCLES ASSUMED DIVERGENT:42; CHECK: depth=1: entries(P T) Q A C B43define amdgpu_kernel void @nested(i32 %a, i32 %b, i32 %c) {44entry:45 %cond.uni = icmp slt i32 %a, 046 %tid = call i32 @llvm.amdgcn.workitem.id.x()47 %cond.div = icmp slt i32 %tid, 048 br i1 %cond.div, label %T, label %P49 50P:51 %pp.phi = phi i32 [ %a, %entry], [ %b, %T ]52 %pp = add i32 %b, 153 br i1 %cond.uni, label %B, label %Q54 55Q:56 %qq = add i32 %b, 157 br i1 %cond.uni, label %T, label %exit58 59A:60 %aa = add i32 %b, 161 br label %B62 63B:64 %bb = add i32 %b, 165 br label %C66 67C:68 %cc = add i32 %b, 169 br i1 %cond.uni, label %Q, label %A70 71T:72 %t.phi = phi i32 [ %qq, %Q ], [ %a, %entry ]73 %tt = add i32 %b, 174 br i1 %cond.uni, label %A, label %P75 76exit:77 %ee = add i32 %b, 178 ret void79}80 81; Just make sure that this does not asert. It is important that Q is recognized82; as the header of the outermost cycle. The incorrect assert was exercised by83; this hierarchy:84;85; CycleInfo for function: irreducible_outer_cycle86; depth=1: entries(Q R) C B D87; depth=2: entries(R) C B D88; depth=3: entries(B) D89;90; CHECK-LABEL: UniformityInfo for function 'irreducible_outer_cycle':91; CHECK: CYCLES ASSUMED DIVERGENT:92; CHECK: depth=1: entries(Q R) C B D93define void @irreducible_outer_cycle(i1 %c1, i1 %c2, i1 %c3) {94entry:95 br i1 %c1, label %P, label %Q96 97P:98 br i1 false, label %Q, label %R99 100Q:101 br label %R102 103R:104 br i1 false, label %Q, label %B105 106B:107 br i1 false, label %C, label %D108 109D:110 br label %B111 112C:113 br i1 false, label %R, label %exit114 115exit:116 ret void117}118 119declare i32 @llvm.amdgcn.workitem.id.x() #0120