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1; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s2 3define amdgpu_kernel void @divergent_cycle_1(i32 %a, i32 %b, i32 %c) {4; CHECK-LABEL: UniformityInfo for function 'divergent_cycle_1':5; CHECK: CYCLES ASSUMED DIVERGENT:6; CHECK: depth=1: entries(R P) S Q7; CHECK: CYCLES WITH DIVERGENT EXIT:8; CHECK: depth=2: entries(S P) Q9; CHECK: depth=1: entries(R P) S Q10entry:11 %cond.uni = icmp slt i32 %a, 012 %tid = call i32 @llvm.amdgcn.workitem.id.x()13 %cond.div = icmp slt i32 %tid, 014 br i1 %cond.uni, label %P, label %R15 16P:17; CHECK: DIVERGENT: %pp.phi =18 %pp.phi = phi i32 [ %a, %entry], [ %b, %S ]19 %pp = add i32 %b, 120 br label %Q21 22Q:23 %qq = add i32 %b, 124 br i1 %cond.div, label %S, label %R25 26R:27 %rr = add i32 %b, 128 br label %S29 30S:31; CHECK: DIVERGENT: %s.phi =32 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]33 %ss = add i32 %b, 134 br i1 %cond.uni, label %exit, label %P35 36exit:37 %ee = add i32 %b, 138 ret void39}40 41define amdgpu_kernel void @uniform_cycle_1(i32 %a, i32 %b, i32 %c) {42; CHECK-LABEL: UniformityInfo for function 'uniform_cycle_1':43; CHECK-NOT: CYCLES ASSUMED DIVERGENT:44; CHECK-NOT: CYCLES WITH DIVERGENT EXIT:45entry:46 %cond.uni = icmp slt i32 %a, 047 %tid = call i32 @llvm.amdgcn.workitem.id.x()48 %cond.div = icmp slt i32 %tid, 049 br i1 %cond.uni, label %P, label %T50 51P:52; CHECK-NOT: DIVERGENT: %pp.phi = phi i3253 %pp.phi = phi i32 [ %a, %entry], [ %b, %T ]54 %pp = add i32 %b, 155 br label %Q56 57Q:58 %qq = add i32 %b, 159 br i1 %cond.div, label %S, label %R60 61R:62 %rr = add i32 %b, 163 br label %S64 65S:66; CHECK: DIVERGENT: %s.phi =67 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]68 %ss = add i32 %b, 169 br i1 %cond.uni, label %exit, label %T70 71T:72 %tt = add i32 %b, 173 br label %P74 75exit:76 %ee = add i32 %b, 177 ret void78}79 80declare i32 @llvm.amdgcn.workitem.id.x() #081