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1; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s2 3; These tests have identical control flow graphs with slight changes4; that affect cycle-info. There is a minor functional difference in5; the branch conditions; but that is not relevant to the tests.6 7;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;8;;9;; The inner cycle has a header (P) that dominates the join, hence10;; both cycles are reported as converged.11;;12;; CHECK-LABEL: UniformityInfo for function 'headers_b_p':13;; CHECK-NOT: CYCLES ASSUMED DIVERGENT:14;; CHECK-NOT: CYCLES WITH DIVERGENT EXIT:15 16define amdgpu_kernel void @headers_b_p(i32 %a, i32 %b, i32 %c) {17entry:18 %cond.uni = icmp slt i32 %a, 019 %tid = call i32 @llvm.amdgcn.workitem.id.x()20 %cond.div = icmp slt i32 %tid, 021 %a.div = add i32 %tid, %a22 br i1 %cond.uni, label %B, label %A23 24A:25 br label %B26 27B:28 br i1 %cond.uni, label %C, label %D29 30C:31 br i1 %cond.uni, label %T, label %P32 33P:34 %pp.phi = phi i32 [ %a, %C], [ %b, %T ]35 %pp = add i32 %b, 136 br i1 %cond.uni, label %R, label %Q37 38Q:39 %qq = add i32 %b, 140 br i1 %cond.div, label %S, label %R41 42R:43 %rr = add i32 %b, 144 br label %S45 46S:47 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]48 %ss = add i32 %pp.phi, 149 br i1 %cond.uni, label %D, label %T50 51D:52 br i1 %cond.uni, label %exit, label %A53 54T:55 %tt.phi = phi i32 [ %ss, %S ], [ %a, %C ]56 %tt = add i32 %b, 157 br label %P58 59exit:60 %ee = add i32 %b, 161 ret void62}63 64;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;65;;66;; Same as previous, but the outer cycle has a different header (A).67;; The inner cycle has a header (P) that dominates the join, hence68;; both cycles are reported as converged.69;;70;; CHECK-LABEL: UniformityInfo for function 'headers_a_p':71;; CHECK-NOT: CYCLES ASSUMED DIVERGENT:72;; CHECK-NOT: CYCLES WITH DIVERGENT EXIT:73 74define amdgpu_kernel void @headers_a_p(i32 %a, i32 %b, i32 %c) {75entry:76 %cond.uni = icmp slt i32 %a, 077 %tid = call i32 @llvm.amdgcn.workitem.id.x()78 %cond.div = icmp slt i32 %tid, 079 %a.div = add i32 %tid, %a80 br i1 %cond.uni, label %B, label %A81 82A:83 br label %B84 85B:86 br i1 %cond.uni, label %C, label %D87 88C:89 br i1 %cond.uni, label %T, label %P90 91P:92 %pp.phi = phi i32 [ %a, %C], [ %b, %T ]93 %pp = add i32 %b, 194 br i1 %cond.uni, label %R, label %Q95 96Q:97 %qq = add i32 %b, 198 br i1 %cond.div, label %S, label %R99 100R:101 %rr = add i32 %b, 1102 br label %S103 104S:105 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]106 %ss = add i32 %pp.phi, 1107 br i1 %cond.uni, label %D, label %T108 109D:110 br i1 %cond.uni, label %exit, label %A111 112T:113 %tt.phi = phi i32 [ %ss, %S ], [ %a, %C ]114 %tt = add i32 %b, 1115 br label %P116 117exit:118 %ee = add i32 %b, 1119 ret void120}121 122;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;123;;124;; The inner cycle has a header (T) that does not dominate the join.125;; The outer cycle has a header (B) that dominates the join. Hence126;; only the inner cycle is reported as diverged.127;;128;; CHECK-LABEL: UniformityInfo for function 'headers_b_t':129;; CHECK: CYCLES ASSUMED DIVERGENT:130;; CHECK: depth=2: entries(T P) S Q R131;; CHECK-NOT: CYCLES WITH DIVERGENT EXIT:132 133define amdgpu_kernel void @headers_b_t(i32 %a, i32 %b, i32 %c) {134entry:135 %cond.uni = icmp slt i32 %a, 0136 %tid = call i32 @llvm.amdgcn.workitem.id.x()137 %cond.div = icmp slt i32 %tid, 0138 %a.div = add i32 %tid, %a139 br i1 %cond.uni, label %A, label %B140 141A:142 br label %B143 144B:145 br i1 %cond.uni, label %C, label %D146 147C:148 br i1 %cond.uni, label %P, label %T149 150P:151 %pp.phi = phi i32 [ %a, %C], [ %b, %T ]152 %pp = add i32 %b, 1153 br i1 %cond.uni, label %R, label %Q154 155Q:156 %qq = add i32 %b, 1157 br i1 %cond.div, label %S, label %R158 159R:160 %rr = add i32 %b, 1161 br label %S162 163S:164 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]165 %ss = add i32 %pp.phi, 1166 br i1 %cond.uni, label %D, label %T167 168D:169 br i1 %cond.uni, label %exit, label %A170 171T:172 %tt.phi = phi i32 [ %ss, %S ], [ %a, %C ]173 %tt = add i32 %b, 1174 br label %P175 176exit:177 %ee = add i32 %b, 1178 ret void179}180 181;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;182;;183;; The cycles have headers (A and T) that do not dominate the join.184;; Hence the outermost cycle is reported as diverged.185;;186;; CHECK-LABEL: UniformityInfo for function 'headers_a_t':187;; CHECK: CYCLES ASSUMED DIVERGENT:188;; CHECK: depth=1: entries(A B) D T S Q P R C189;; CHECK-NOT: CYCLES WITH DIVERGENT EXIT:190 191define amdgpu_kernel void @headers_a_t(i32 %a, i32 %b, i32 %c) {192entry:193 %cond.uni = icmp slt i32 %a, 0194 %tid = call i32 @llvm.amdgcn.workitem.id.x()195 %cond.div = icmp slt i32 %tid, 0196 %a.div = add i32 %tid, %a197 br i1 %cond.uni, label %B, label %A198 199A:200 br label %B201 202B:203 br i1 %cond.uni, label %C, label %D204 205C:206 br i1 %cond.uni, label %P, label %T207 208P:209 %pp.phi = phi i32 [ %a, %C], [ %b, %T ]210 %pp = add i32 %b, 1211 br i1 %cond.uni, label %R, label %Q212 213Q:214 %qq = add i32 %b, 1215 br i1 %cond.div, label %S, label %R216 217R:218 %rr = add i32 %b, 1219 br label %S220 221S:222 %s.phi = phi i32 [ %qq, %Q ], [ %rr, %R ]223 %ss = add i32 %pp.phi, 1224 br i1 %cond.uni, label %D, label %T225 226D:227 br i1 %cond.uni, label %exit, label %A228 229T:230 %tt.phi = phi i32 [ %ss, %S ], [ %a, %C ]231 %tt = add i32 %b, 1232 br label %P233 234exit:235 %ee = add i32 %b, 1236 ret void237}238 239declare i32 @llvm.amdgcn.workitem.id.x() #0240