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1; RUN: opt %s -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s2 3target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"4target triple = "nvptx64-nvidia-cuda"5 6define ptx_kernel i32 @daorder(i32 %n) {7; CHECK-LABEL: for function 'daorder'8entry:9 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()10 %cond = icmp slt i32 %tid, 011 br i1 %cond, label %A, label %B ; divergent12; CHECK: DIVERGENT: %cond =13; CHECK: DIVERGENT: br i1 %cond,14A:15 %defAtA = add i32 %n, 1 ; uniform16; CHECK-NOT: DIVERGENT: %defAtA =17 br label %C18B:19 %defAtB = add i32 %n, 2 ; uniform20; CHECK-NOT: DIVERGENT: %defAtB =21 br label %C22C:23 %defAtC = phi i32 [ %defAtA, %A ], [ %defAtB, %B ] ; divergent24; CHECK: DIVERGENT: %defAtC =25 br label %D26 27D:28 %i = phi i32 [0, %C], [ %i.inc, %E ] ; uniform29; CHECK-NOT: DIVERGENT: %i = phi30 br label %E31 32E:33 %i.inc = add i32 %i, 134 %loopCnt = icmp slt i32 %i.inc, %n35; CHECK-NOT: DIVERGENT: %loopCnt =36 br i1 %loopCnt, label %D, label %exit37 38exit:39 ret i32 %n40}41 42declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()43declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()44declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()45declare i32 @llvm.nvvm.read.ptx.sreg.laneid()46