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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instsimplify < %s -S | FileCheck %s3 4define <4 x i1> @vec_reverse_known_bits(<4 x i8> %xx) {5; CHECK-LABEL: @vec_reverse_known_bits(6; CHECK-NEXT: ret <4 x i1> splat (i1 true)7;8 %x = or <4 x i8> %xx, <i8 128, i8 128, i8 128, i8 128>9 %rev = call <4 x i8> @llvm.vector.reverse(<4 x i8> %x)10 %r = icmp slt <4 x i8> %rev, zeroinitializer11 ret <4 x i1> %r12}13 14define <4 x i1> @vec_reverse_known_bits_fail(<4 x i8> %xx) {15; CHECK-LABEL: @vec_reverse_known_bits_fail(16; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 -128, i8 -128, i8 -128, i8 127>17; CHECK-NEXT: [[REV:%.*]] = call <4 x i8> @llvm.vector.reverse.v4i8(<4 x i8> [[X]])18; CHECK-NEXT: [[R:%.*]] = icmp slt <4 x i8> [[REV]], zeroinitializer19; CHECK-NEXT: ret <4 x i1> [[R]]20;21 %x = or <4 x i8> %xx, <i8 128, i8 128, i8 128, i8 127>22 %rev = call <4 x i8> @llvm.vector.reverse(<4 x i8> %x)23 %r = icmp slt <4 x i8> %rev, zeroinitializer24 ret <4 x i1> %r25}26 27define i1 @vec_reverse_known_bits_demanded(<4 x i8> %xx) {28; CHECK-LABEL: @vec_reverse_known_bits_demanded(29; CHECK-NEXT: ret i1 true30;31 %x = or <4 x i8> %xx, <i8 127, i8 55, i8 128, i8 123>32 %rev = call <4 x i8> @llvm.vector.reverse(<4 x i8> %x)33 %ele = extractelement <4 x i8> %rev, i64 134 %r = icmp slt i8 %ele, 035 ret i1 %r36}37 38define i1 @vec_reverse_known_bits_demanded_fail(<4 x i8> %xx) {39; CHECK-LABEL: @vec_reverse_known_bits_demanded_fail(40; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], <i8 127, i8 55, i8 -128, i8 123>41; CHECK-NEXT: [[REV:%.*]] = call <4 x i8> @llvm.vector.reverse.v4i8(<4 x i8> [[X]])42; CHECK-NEXT: [[ELE:%.*]] = extractelement <4 x i8> [[REV]], i64 243; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[ELE]], 044; CHECK-NEXT: ret i1 [[R]]45;46 %x = or <4 x i8> %xx, <i8 127, i8 55, i8 128, i8 123>47 %rev = call <4 x i8> @llvm.vector.reverse(<4 x i8> %x)48 %ele = extractelement <4 x i8> %rev, i64 249 %r = icmp slt i8 %ele, 050 ret i1 %r51}52