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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4declare void @llvm.assume(i1)5 6define i1 @blsmsk_eq_is_false(i32 %x) {7; CHECK-LABEL: @blsmsk_eq_is_false(8; CHECK-NEXT: ret i1 false9;10 %x1 = or i32 %x, 1011 %x2 = sub i32 %x1, 112 %x3 = xor i32 %x1, %x213 %z = icmp eq i32 %x3, 814 ret i1 %z15}16 17define <2 x i1> @blsmsk_ne_is_true_vec(<2 x i32> %x) {18; CHECK-LABEL: @blsmsk_ne_is_true_vec(19; CHECK-NEXT: ret <2 x i1> splat (i1 true)20;21 %x1 = or <2 x i32> %x, <i32 10, i32 10>22 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>23 %x3 = xor <2 x i32> %x2, %x124 %z = icmp ne <2 x i32> %x3, <i32 8, i32 8>25 ret <2 x i1> %z26}27 28define <2 x i1> @blsmsk_ne_is_true_diff_vec(<2 x i32> %x) {29; CHECK-LABEL: @blsmsk_ne_is_true_diff_vec(30; CHECK-NEXT: ret <2 x i1> splat (i1 true)31;32 %x1 = or <2 x i32> %x, <i32 10, i32 130>33 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>34 %x3 = xor <2 x i32> %x2, %x135 %z = icmp ne <2 x i32> %x3, <i32 8, i32 8>36 ret <2 x i1> %z37}38 39define i1 @blsmsk_ge_is_false(i32 %x) {40; CHECK-LABEL: @blsmsk_ge_is_false(41; CHECK-NEXT: ret i1 false42;43 %x1 = or i32 %x, 1044 %x2 = sub i32 %x1, 145 %x3 = xor i32 %x1, %x246 %z = icmp uge i32 %x3, 847 ret i1 %z48}49 50define <2 x i1> @blsmsk_gt_is_false_vec(<2 x i32> %x) {51; CHECK-LABEL: @blsmsk_gt_is_false_vec(52; CHECK-NEXT: ret <2 x i1> zeroinitializer53;54 %x1 = or <2 x i32> %x, <i32 10, i32 10>55 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>56 %x3 = xor <2 x i32> %x2, %x157 %z = icmp ugt <2 x i32> %x3, <i32 8, i32 8>58 ret <2 x i1> %z59}60 61define i1 @blsmsk_signed_is_false(i32 %x) {62; CHECK-LABEL: @blsmsk_signed_is_false(63; CHECK-NEXT: ret i1 false64;65 %x1 = or i32 %x, 1066 %x2 = sub i32 %x1, 167 %x3 = xor i32 %x1, %x268 %z = icmp slt i32 %x3, 069 ret i1 %z70}71 72define i32 @blsmsk_add_eval(i32 %x) {73; CHECK-LABEL: @blsmsk_add_eval(74; CHECK-NEXT: ret i32 3375;76 %x1 = or i32 %x, 977 %x2 = sub i32 %x1, 178 %x3 = xor i32 %x2, %x179 %z = add i32 %x3, 3280 ret i32 %z81}82 83define <2 x i32> @blsmsk_add_eval_vec(<2 x i32> %x) {84; CHECK-LABEL: @blsmsk_add_eval_vec(85; CHECK-NEXT: ret <2 x i32> splat (i32 33)86;87 %x1 = or <2 x i32> %x, <i32 9, i32 9>88 %x2 = add <2 x i32> %x1, <i32 -1, i32 -1>89 %x3 = xor <2 x i32> %x2, %x190 %z = add <2 x i32> %x3, <i32 32, i32 32>91 ret <2 x i32> %z92}93 94define i32 @blsmsk_sub_eval(i32 %x) {95; CHECK-LABEL: @blsmsk_sub_eval(96; CHECK-NEXT: ret i32 -3197;98 %x1 = or i32 %x, 999 %x2 = sub i32 %x1, 1100 %x3 = xor i32 %x1, %x2101 %z = sub i32 %x3, 32102 ret i32 %z103}104 105define i32 @blsmsk_or_eval(i32 %x) {106; CHECK-LABEL: @blsmsk_or_eval(107; CHECK-NEXT: ret i32 33108;109 %x1 = or i32 %x, 129110 %x2 = sub i32 %x1, 1111 %x3 = xor i32 %x2, %x1112 %z = or i32 %x3, 32113 ret i32 %z114}115 116define <2 x i32> @blsmsk_or_eval_vec(<2 x i32> %x) {117; CHECK-LABEL: @blsmsk_or_eval_vec(118; CHECK-NEXT: ret <2 x i32> splat (i32 33)119;120 %x1 = or <2 x i32> %x, <i32 9, i32 9>121 %x2 = add <2 x i32> %x1, <i32 -1, i32 -1>122 %x3 = xor <2 x i32> %x2, %x1123 %z = or <2 x i32> %x3, <i32 32, i32 32>124 ret <2 x i32> %z125}126 127define i32 @blsmsk_xor_eval(i32 %x) {128; CHECK-LABEL: @blsmsk_xor_eval(129; CHECK-NEXT: ret i32 33130;131 %x1 = or i32 %x, 255132 %x2 = sub i32 %x1, 1133 %x3 = xor i32 %x1, %x2134 %z = xor i32 %x3, 32135 ret i32 %z136}137 138define i32 @blsmsk_and_eval(i32 %x) {139; CHECK-LABEL: @blsmsk_and_eval(140; CHECK-NEXT: ret i32 0141;142 %x1 = or i32 %x, 34143 %x2 = sub i32 %x1, 1144 %x3 = xor i32 %x2, %x1145 %z = and i32 %x3, 32146 ret i32 %z147}148 149define <2 x i32> @blsmsk_and_eval_vec(<2 x i32> %x) {150; CHECK-LABEL: @blsmsk_and_eval_vec(151; CHECK-NEXT: ret <2 x i32> zeroinitializer152;153 %x1 = or <2 x i32> %x, <i32 34, i32 34>154 %x2 = add <2 x i32> %x1, <i32 -1, i32 -1>155 %x3 = xor <2 x i32> %x2, %x1156 %z = and <2 x i32> %x3, <i32 32, i32 32>157 ret <2 x i32> %z158}159 160define i32 @blsmsk_and_eval2(i32 %x) {161; CHECK-LABEL: @blsmsk_and_eval2(162; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 10163; CHECK-NEXT: [[X2:%.*]] = add i32 [[X1]], 63164; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X]], [[X2]]165; CHECK-NEXT: [[Z:%.*]] = and i32 [[X3]], 32166; CHECK-NEXT: ret i32 [[Z]]167;168 %x1 = or i32 %x, 10169 %x2 = sub i32 %x1, 1170 %x3 = xor i32 %x1, %x2171 %z = and i32 %x3, 32172 ret i32 %z173}174 175define <2 x i32> @blsmsk_and_eval3_vec(<2 x i32> %x) {176; CHECK-LABEL: @blsmsk_and_eval3_vec(177; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 34)178; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[X1]], splat (i32 63)179; CHECK-NEXT: [[X3:%.*]] = xor <2 x i32> [[X2]], [[X1]]180; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[X3]], <i32 16, i32 32>181; CHECK-NEXT: ret <2 x i32> [[Z]]182;183 %x1 = or <2 x i32> %x, <i32 34, i32 34>184 %x2 = add <2 x i32> %x1, <i32 -1, i32 -1>185 %x3 = xor <2 x i32> %x2, %x1186 %z = and <2 x i32> %x3, <i32 16, i32 32>187 ret <2 x i32> %z188}189 190define i1 @blsmsk_eq_is_false_assume(i32 %x) {191; CHECK-LABEL: @blsmsk_eq_is_false_assume(192; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 4193; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0194; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])195; CHECK-NEXT: ret i1 false196;197 %lb = and i32 %x, 4198 %cmp = icmp ne i32 %lb, 0199 call void @llvm.assume(i1 %cmp)200 %x2 = add i32 %x, -1201 %x3 = xor i32 %x2, %x202 %z = icmp eq i32 %x3, 8203 ret i1 %z204}205 206define i1 @blsmsk_gt_is_false_assume(i32 %x) {207; CHECK-LABEL: @blsmsk_gt_is_false_assume(208; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 2209; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0210; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])211; CHECK-NEXT: ret i1 false212;213 %lb = and i32 %x, 2214 %cmp = icmp ne i32 %lb, 0215 call void @llvm.assume(i1 %cmp)216 %x2 = sub i32 %x, 1217 %x3 = xor i32 %x2, %x218 %z = icmp ugt i32 %x3, 8219 ret i1 %z220}221 222define i32 @blsmsk_add_eval_assume(i32 %x) {223; CHECK-LABEL: @blsmsk_add_eval_assume(224; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1225; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0226; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])227; CHECK-NEXT: ret i32 33228;229 %lb = and i32 %x, 1230 %cmp = icmp ne i32 %lb, 0231 call void @llvm.assume(i1 %cmp)232 %x2 = sub i32 %x, 1233 %x3 = xor i32 %x2, %x234 %z = add i32 %x3, 32235 ret i32 %z236}237 238define <2 x i32> @blsmsk_add_eval_assume_vec(<2 x i32> %x) {239; CHECK-LABEL: @blsmsk_add_eval_assume_vec(240; CHECK-NEXT: [[CMP:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i1>241; CHECK-NEXT: [[CMP0:%.*]] = extractelement <2 x i1> [[CMP]], i64 0242; CHECK-NEXT: call void @llvm.assume(i1 [[CMP0]])243; CHECK-NEXT: [[CMP1:%.*]] = extractelement <2 x i1> [[CMP]], i64 1244; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])245; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[X]], splat (i32 -1)246; CHECK-NEXT: [[X3:%.*]] = xor <2 x i32> [[X2]], [[X]]247; CHECK-NEXT: [[Z:%.*]] = add <2 x i32> [[X3]], splat (i32 32)248; CHECK-NEXT: ret <2 x i32> [[Z]]249;250 %lb = and <2 x i32> %x, <i32 1, i32 1>251 %cmp = icmp ne <2 x i32> %lb, <i32 0, i32 0>252 %cmp0 = extractelement <2 x i1> %cmp, i32 0253 call void @llvm.assume(i1 %cmp0)254 %cmp1 = extractelement <2 x i1> %cmp, i32 1255 call void @llvm.assume(i1 %cmp1)256 %x2 = sub <2 x i32> %x, <i32 1, i32 1>257 %x3 = xor <2 x i32> %x2, %x258 %z = add <2 x i32> %x3, <i32 32, i32 32>259 ret <2 x i32> %z260}261 262define i32 @blsmsk_sub_eval_assume(i32 %x) {263; CHECK-LABEL: @blsmsk_sub_eval_assume(264; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1265; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0266; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])267; CHECK-NEXT: ret i32 -31268;269 %lb = and i32 %x, 1270 %cmp = icmp ne i32 %lb, 0271 call void @llvm.assume(i1 %cmp)272 %x2 = sub i32 %x, 1273 %x3 = xor i32 %x, %x2274 %z = sub i32 %x3, 32275 ret i32 %z276}277 278define i32 @blsmsk_or_eval_assume(i32 %x) {279; CHECK-LABEL: @blsmsk_or_eval_assume(280; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1281; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0282; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])283; CHECK-NEXT: ret i32 33284;285 %lb = and i32 %x, 1286 %cmp = icmp ne i32 %lb, 0287 call void @llvm.assume(i1 %cmp)288 %x2 = sub i32 %x, 1289 %x3 = xor i32 %x2, %x290 %z = or i32 %x3, 32291 ret i32 %z292}293 294define i32 @blsmsk_and_eval_assume(i32 %x) {295; CHECK-LABEL: @blsmsk_and_eval_assume(296; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 4297; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0298; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])299; CHECK-NEXT: [[X2:%.*]] = add i32 [[X]], 63300; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X2]], [[X]]301; CHECK-NEXT: [[Z:%.*]] = and i32 [[X3]], 32302; CHECK-NEXT: ret i32 [[Z]]303;304 %lb = and i32 %x, 4305 %cmp = icmp ne i32 %lb, 0306 call void @llvm.assume(i1 %cmp)307 %x2 = sub i32 %x, 1308 %x3 = xor i32 %x2, %x309 %z = and i32 %x3, 32310 ret i32 %z311}312 313 314define <2 x i1> @blsi_eq_is_false_vec(<2 x i32> %x) {315; CHECK-LABEL: @blsi_eq_is_false_vec(316; CHECK-NEXT: ret <2 x i1> zeroinitializer317;318 %x1 = or <2 x i32> %x, <i32 10, i32 10>319 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1320 %x3 = and <2 x i32> %x1, %x2321 %z = icmp eq <2 x i32> %x3, <i32 8, i32 8>322 ret <2 x i1> %z323}324 325define i1 @blsi_ne_is_true(i32 %x) {326; CHECK-LABEL: @blsi_ne_is_true(327; CHECK-NEXT: ret i1 true328;329 %x1 = or i32 %x, 10330 %x2 = sub i32 0, %x1331 %x3 = and i32 %x1, %x2332 %z = icmp ne i32 %x3, 8333 ret i1 %z334}335 336define <2 x i1> @blsi_ge_is_false_vec(<2 x i32> %x) {337; CHECK-LABEL: @blsi_ge_is_false_vec(338; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 10)339; CHECK-NEXT: [[X2:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X1]]340; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X]], [[X2]]341; CHECK-NEXT: [[Z:%.*]] = icmp ugt <2 x i32> [[X3]], splat (i32 7)342; CHECK-NEXT: ret <2 x i1> [[Z]]343;344 %x1 = or <2 x i32> %x, <i32 10, i32 10>345 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1346 %x3 = and <2 x i32> %x1, %x2347 %z = icmp uge <2 x i32> %x3, <i32 8, i32 8>348 ret <2 x i1> %z349}350 351define <2 x i1> @blsi_ge_is_false_diff_vec(<2 x i32> %x) {352; CHECK-LABEL: @blsi_ge_is_false_diff_vec(353; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], <i32 10, i32 11>354; CHECK-NEXT: [[X2:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X1]]355; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X]], [[X2]]356; CHECK-NEXT: [[Z:%.*]] = icmp ugt <2 x i32> [[X3]], splat (i32 7)357; CHECK-NEXT: ret <2 x i1> [[Z]]358;359 %x1 = or <2 x i32> %x, <i32 10, i32 11>360 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1361 %x3 = and <2 x i32> %x1, %x2362 %z = icmp uge <2 x i32> %x3, <i32 8, i32 8>363 ret <2 x i1> %z364}365 366define i1 @blsi_gt_is_false(i32 %x) {367; CHECK-LABEL: @blsi_gt_is_false(368; CHECK-NEXT: ret i1 false369;370 %x1 = or i32 %x, 10371 %x2 = sub i32 0, %x1372 %x3 = and i32 %x2, %x1373 %z = icmp ugt i32 %x3, 8374 ret i1 %z375}376 377 378define i32 @blsi_add_eval(i32 %x) {379; CHECK-LABEL: @blsi_add_eval(380; CHECK-NEXT: ret i32 33381;382 %x1 = or i32 %x, 9383 %x2 = sub i32 0, %x1384 %x3 = and i32 %x2, %x1385 %z = add i32 %x3, 32386 ret i32 %z387}388 389define i32 @blsi_sub_eval(i32 %x) {390; CHECK-LABEL: @blsi_sub_eval(391; CHECK-NEXT: ret i32 -31392;393 %x1 = or i32 %x, 33394 %x2 = sub i32 0, %x1395 %x3 = and i32 %x2, %x1396 %z = sub i32 %x3, 32397 ret i32 %z398}399 400define <2 x i32> @blsi_sub_eval_vec(<2 x i32> %x) {401; CHECK-LABEL: @blsi_sub_eval_vec(402; CHECK-NEXT: ret <2 x i32> splat (i32 -31)403;404 %x1 = or <2 x i32> %x, <i32 33, i32 33>405 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1406 %x3 = and <2 x i32> %x1, %x2407 %z = sub <2 x i32> %x3, <i32 32, i32 32>408 ret <2 x i32> %z409}410 411define i32 @blsi_or_eval(i32 %x) {412; CHECK-LABEL: @blsi_or_eval(413; CHECK-NEXT: ret i32 33414;415 %x1 = or i32 %x, 129416 %x2 = sub i32 0, %x1417 %x3 = and i32 %x2, %x1418 %z = or i32 %x3, 32419 ret i32 %z420}421 422define <2 x i32> @blsi_xor_eval_vec(<2 x i32> %x) {423; CHECK-LABEL: @blsi_xor_eval_vec(424; CHECK-NEXT: ret <2 x i32> splat (i32 33)425;426 %x1 = or <2 x i32> %x, <i32 33, i32 33>427 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1428 %x3 = and <2 x i32> %x2, %x1429 %z = xor <2 x i32> %x3, <i32 32, i32 32>430 ret <2 x i32> %z431}432 433define i32 @blsi_and_eval(i32 %x) {434; CHECK-LABEL: @blsi_and_eval(435; CHECK-NEXT: ret i32 0436;437 %x1 = or i32 %x, 34438 %x2 = sub i32 0, %x1439 %x3 = and i32 %x2, %x1440 %z = and i32 %x3, 32441 ret i32 %z442}443 444define <2 x i32> @blsi_and_eval2_vec(<2 x i32> %x) {445; CHECK-LABEL: @blsi_and_eval2_vec(446; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 30)447; CHECK-NEXT: [[X2:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X1]]448; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X]], [[X2]]449; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[X3]], splat (i32 32)450; CHECK-NEXT: ret <2 x i32> [[Z]]451;452 %x1 = or <2 x i32> %x, <i32 30, i32 30>453 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1454 %x3 = and <2 x i32> %x1, %x2455 %z = and <2 x i32> %x3, <i32 32, i32 32>456 ret <2 x i32> %z457}458 459define i32 @blsi_and_eval3(i32 %x) {460; CHECK-LABEL: @blsi_and_eval3(461; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 34462; CHECK-NEXT: [[X2:%.*]] = sub nsw i32 0, [[X1]]463; CHECK-NEXT: [[X3:%.*]] = and i32 [[X]], [[X2]]464; CHECK-NEXT: [[Z:%.*]] = and i32 [[X3]], 208465; CHECK-NEXT: ret i32 [[Z]]466;467 %x1 = or i32 %x, 34468 %x2 = sub i32 0, %x1469 %x3 = and i32 %x2, %x1470 %z = and i32 %x3, 240471 ret i32 %z472}473 474define <2 x i1> @blsi_eq_is_false_assume_vec(<2 x i32> %x) {475; CHECK-LABEL: @blsi_eq_is_false_assume_vec(476; CHECK-NEXT: [[LB:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 2)477; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[LB]], zeroinitializer478; CHECK-NEXT: [[CMP0:%.*]] = extractelement <2 x i1> [[CMP]], i64 0479; CHECK-NEXT: call void @llvm.assume(i1 [[CMP0]])480; CHECK-NEXT: [[CMP1:%.*]] = extractelement <2 x i1> [[CMP]], i64 1481; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])482; CHECK-NEXT: [[X2:%.*]] = sub <2 x i32> zeroinitializer, [[X]]483; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X]], [[X2]]484; CHECK-NEXT: [[Z:%.*]] = icmp eq <2 x i32> [[X3]], splat (i32 8)485; CHECK-NEXT: ret <2 x i1> [[Z]]486;487 %lb = and <2 x i32> %x, <i32 2, i32 2>488 %cmp = icmp ne <2 x i32> %lb, <i32 0, i32 0>489 %cmp0 = extractelement <2 x i1> %cmp, i32 0490 call void @llvm.assume(i1 %cmp0)491 %cmp1 = extractelement <2 x i1> %cmp, i32 1492 call void @llvm.assume(i1 %cmp1)493 %x2 = sub <2 x i32> <i32 0, i32 0>, %x494 %x3 = and <2 x i32> %x2, %x495 %z = icmp eq <2 x i32> %x3, <i32 8, i32 8>496 ret <2 x i1> %z497}498 499define i1 @blsi_ne_is_true_assume(i32 %x) {500; CHECK-LABEL: @blsi_ne_is_true_assume(501; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 4502; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0503; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])504; CHECK-NEXT: ret i1 true505;506 %lb = and i32 %x, 4507 %cmp = icmp ne i32 %lb, 0508 call void @llvm.assume(i1 %cmp)509 %x2 = sub i32 0, %x510 %x3 = and i32 %x2, %x511 %z = icmp ne i32 %x3, 8512 ret i1 %z513}514 515define i1 @blsi_ge_is_false_assume(i32 %x) {516; CHECK-LABEL: @blsi_ge_is_false_assume(517; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 4518; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0519; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])520; CHECK-NEXT: ret i1 false521;522 %lb = and i32 %x, 4523 %cmp = icmp ne i32 %lb, 0524 call void @llvm.assume(i1 %cmp)525 %x2 = sub i32 0, %x526 %x3 = and i32 %x2, %x527 %z = icmp uge i32 %x3, 8528 ret i1 %z529}530 531define <2 x i1> @blsi_cmp_eq_diff_bits_vec(<2 x i32> %x) {532; CHECK-LABEL: @blsi_cmp_eq_diff_bits_vec(533; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], <i32 1, i32 2>534; CHECK-NEXT: [[X2:%.*]] = sub <2 x i32> zeroinitializer, [[X1]]535; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X1]], [[X2]]536; CHECK-NEXT: [[Z:%.*]] = icmp eq <2 x i32> [[X3]], splat (i32 32)537; CHECK-NEXT: ret <2 x i1> [[Z]]538;539 %x1 = or <2 x i32> %x, <i32 1, i32 2>540 %x2 = sub <2 x i32> <i32 0, i32 0>, %x1541 %x3 = and <2 x i32> %x1, %x2542 %z = icmp eq <2 x i32> %x3, <i32 32, i32 32>543 ret <2 x i1> %z544}545 546define i32 @blsi_xor_eval_assume(i32 %x) {547; CHECK-LABEL: @blsi_xor_eval_assume(548; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1549; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0550; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])551; CHECK-NEXT: ret i32 33552;553 %lb = and i32 %x, 1554 %cmp = icmp ne i32 %lb, 0555 call void @llvm.assume(i1 %cmp)556 %x2 = sub i32 0, %x557 %x3 = and i32 %x2, %x558 %z = xor i32 %x3, 32559 ret i32 %z560}561 562define i32 @blsi_and_eval_assume(i32 %x) {563; CHECK-LABEL: @blsi_and_eval_assume(564; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 8565; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0566; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])567; CHECK-NEXT: ret i32 0568;569 %lb = and i32 %x, 8570 %cmp = icmp ne i32 %lb, 0571 call void @llvm.assume(i1 %cmp)572 %x2 = sub i32 0, %x573 %x3 = and i32 %x2, %x574 %z = and i32 %x3, 32575 ret i32 %z576}577 578define <2 x i1> @blsmsk_ne_no_proof_vec(<2 x i32> %x) {579; CHECK-LABEL: @blsmsk_ne_no_proof_vec(580; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 10)581; CHECK-NEXT: [[X2:%.*]] = add nsw <2 x i32> [[X1]], <i32 -2, i32 -3>582; CHECK-NEXT: [[X3:%.*]] = xor <2 x i32> [[X2]], [[X1]]583; CHECK-NEXT: [[Z:%.*]] = icmp ne <2 x i32> [[X3]], splat (i32 8)584; CHECK-NEXT: ret <2 x i1> [[Z]]585;586 %x1 = or <2 x i32> %x, <i32 10, i32 10>587 %x2 = sub <2 x i32> %x1, <i32 2, i32 3>588 %x3 = xor <2 x i32> %x2, %x1589 %z = icmp ne <2 x i32> %x3, <i32 8, i32 8>590 ret <2 x i1> %z591}592 593define <2 x i32> @blsmsk_add_noeval_vec(<2 x i32> %x) {594; CHECK-LABEL: @blsmsk_add_noeval_vec(595; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 9)596; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[X1]], <i32 1, i32 -2>597; CHECK-NEXT: [[X3:%.*]] = xor <2 x i32> [[X2]], [[X1]]598; CHECK-NEXT: [[Z:%.*]] = add <2 x i32> [[X3]], splat (i32 32)599; CHECK-NEXT: ret <2 x i32> [[Z]]600;601 %x1 = or <2 x i32> %x, <i32 9, i32 9>602 %x2 = add <2 x i32> %x1, <i32 1, i32 -2>603 %x3 = xor <2 x i32> %x2, %x1604 %z = add <2 x i32> %x3, <i32 32, i32 32>605 ret <2 x i32> %z606}607 608define i1 @blsmsk_eq_no_proof(i32 %x) {609; CHECK-LABEL: @blsmsk_eq_no_proof(610; CHECK-NEXT: ret i1 false611;612 %x1 = or i32 %x, 10613 %x2 = add i32 %x1, -2614 %x3 = xor i32 %x2, %x1615 %z = icmp eq i32 %x3, 8616 ret i1 %z617}618 619 620define i32 @blsmsk_add_no_eval(i32 %x) {621; CHECK-LABEL: @blsmsk_add_no_eval(622; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 9623; CHECK-NEXT: [[X2:%.*]] = add nsw i32 [[X1]], -3624; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X1]], [[X2]]625; CHECK-NEXT: [[Z:%.*]] = add i32 [[X3]], 32626; CHECK-NEXT: ret i32 [[Z]]627;628 %x1 = or i32 %x, 9629 %x2 = sub i32 %x1, 3630 %x3 = xor i32 %x1, %x2631 %z = add i32 %x3, 32632 ret i32 %z633}634 635define i32 @blsmsk_add_no_eval2(i32 %x) {636; CHECK-LABEL: @blsmsk_add_no_eval2(637; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 256638; CHECK-NEXT: [[X2:%.*]] = add nsw i32 [[X1]], -1639; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X1]], [[X2]]640; CHECK-NEXT: [[Z:%.*]] = add nuw nsw i32 [[X3]], 32641; CHECK-NEXT: ret i32 [[Z]]642;643 %x1 = or i32 %x, 256644 %x2 = sub i32 %x1, 1645 %x3 = xor i32 %x1, %x2646 %z = add i32 %x3, 32647 ret i32 %z648}649 650define <2 x i32> @blsmsk_xor_no_eval_vec(<2 x i32> %x) {651; CHECK-LABEL: @blsmsk_xor_no_eval_vec(652; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 34)653; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[X1]], <i32 -9, i32 1>654; CHECK-NEXT: [[X3:%.*]] = xor <2 x i32> [[X2]], [[X1]]655; CHECK-NEXT: [[Z:%.*]] = xor <2 x i32> [[X3]], splat (i32 32)656; CHECK-NEXT: ret <2 x i32> [[Z]]657;658 %x1 = or <2 x i32> %x, <i32 34, i32 34>659 %x2 = add <2 x i32> %x1, <i32 -9, i32 1>660 %x3 = xor <2 x i32> %x2, %x1661 %z = xor <2 x i32> %x3, <i32 32, i32 32>662 ret <2 x i32> %z663}664 665define i32 @blsmsk_xor_no_eval_assume(i32 %x) {666; CHECK-LABEL: @blsmsk_xor_no_eval_assume(667; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1668; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[LB]], 0669; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])670; CHECK-NEXT: [[X2:%.*]] = add i32 [[X]], -1671; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X]], [[X2]]672; CHECK-NEXT: [[Z:%.*]] = xor i32 [[X3]], 32673; CHECK-NEXT: ret i32 [[Z]]674;675 %lb = and i32 %x, 1676 %cmp = icmp ne i32 %lb, 1677 call void @llvm.assume(i1 %cmp)678 %x2 = sub i32 %x, 1679 %x3 = xor i32 %x, %x2680 %z = xor i32 %x3, 32681 ret i32 %z682}683 684define i32 @blsmsk_xor_no_eval_assume2(i32 %x) {685; CHECK-LABEL: @blsmsk_xor_no_eval_assume2(686; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 128687; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0688; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])689; CHECK-NEXT: [[X2:%.*]] = add nsw i32 [[X]], -1690; CHECK-NEXT: [[X3:%.*]] = xor i32 [[X]], [[X2]]691; CHECK-NEXT: [[Z:%.*]] = xor i32 [[X3]], 32692; CHECK-NEXT: ret i32 [[Z]]693;694 %lb = and i32 %x, 128695 %cmp = icmp ne i32 %lb, 0696 call void @llvm.assume(i1 %cmp)697 %x2 = sub i32 %x, 1698 %x3 = xor i32 %x, %x2699 %z = xor i32 %x3, 32700 ret i32 %z701}702 703define i1 @blsi_ne_no_proof2(i32 %x) {704; CHECK-LABEL: @blsi_ne_no_proof2(705; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 512706; CHECK-NEXT: [[X2:%.*]] = sub nsw i32 0, [[X1]]707; CHECK-NEXT: [[X3:%.*]] = and i32 [[X1]], [[X2]]708; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[X3]], 8709; CHECK-NEXT: ret i1 [[Z]]710;711 %x1 = or i32 %x, 512712 %x2 = sub i32 0, %x1713 %x3 = and i32 %x2, %x1714 %z = icmp ne i32 %x3, 8715 ret i1 %z716}717 718 719define i32 @blsi_or_no_eval(i32 %x) {720; CHECK-LABEL: @blsi_or_no_eval(721; CHECK-NEXT: [[X1:%.*]] = or i32 [[X:%.*]], 129722; CHECK-NEXT: [[X2:%.*]] = sub nsw i32 2, [[X1]]723; CHECK-NEXT: [[X3:%.*]] = and i32 [[X2]], [[X1]]724; CHECK-NEXT: [[Z:%.*]] = or i32 [[X3]], 32725; CHECK-NEXT: ret i32 [[Z]]726;727 %x1 = or i32 %x, 129728 %x2 = sub i32 2, %x1729 %x3 = and i32 %x2, %x1730 %z = or i32 %x3, 32731 ret i32 %z732}733 734define <2 x i32> @blsi_or_no_partial_eval_vec(<2 x i32> %x) {735; CHECK-LABEL: @blsi_or_no_partial_eval_vec(736; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], splat (i32 30)737; CHECK-NEXT: [[X2:%.*]] = sub nsw <2 x i32> <i32 0, i32 1>, [[X1]]738; CHECK-NEXT: [[X3:%.*]] = and <2 x i32> [[X1]], [[X2]]739; CHECK-NEXT: [[Z:%.*]] = or <2 x i32> [[X3]], splat (i32 32)740; CHECK-NEXT: ret <2 x i32> [[Z]]741;742 %x1 = or <2 x i32> %x, <i32 30, i32 30>743 %x2 = sub <2 x i32> <i32 0, i32 1>, %x1744 %x3 = and <2 x i32> %x1, %x2745 %z = or <2 x i32> %x3, <i32 32, i32 32>746 ret <2 x i32> %z747}748 749 750;; Test that if we have different knowledge about lowbit of X/-X that we select the minimum.751define i1 @blsi_differing_lowbits(i8 %x) {752; CHECK-LABEL: @blsi_differing_lowbits(753; CHECK-NEXT: [[Z:%.*]] = sub i8 0, [[X:%.*]]754; CHECK-NEXT: [[LB:%.*]] = and i8 [[Z]], 2755; CHECK-NEXT: [[NE:%.*]] = icmp ne i8 [[LB]], 0756; CHECK-NEXT: call void @llvm.assume(i1 [[NE]])757; CHECK-NEXT: ret i1 false758;759 %y = or i8 %x, 8760 %z = sub i8 0, %y761 %lb = and i8 %z, 2762 %ne = icmp ne i8 %lb, 0763 call void @llvm.assume(i1 %ne)764 %o = and i8 %z, %y765 %r = icmp eq i8 %o, 4766 ret i1 %r767}768 769define i1 @blsi_differing_lowbits2(i8 %x) {770; CHECK-LABEL: @blsi_differing_lowbits2(771; CHECK-NEXT: [[Z:%.*]] = sub nsw i8 0, [[X:%.*]]772; CHECK-NEXT: [[LB:%.*]] = and i8 [[Z]], 8773; CHECK-NEXT: [[NE:%.*]] = icmp ne i8 [[LB]], 0774; CHECK-NEXT: call void @llvm.assume(i1 [[NE]])775; CHECK-NEXT: [[LB2:%.*]] = and i8 [[X]], 2776; CHECK-NEXT: [[NE2:%.*]] = icmp ne i8 [[LB2]], 0777; CHECK-NEXT: call void @llvm.assume(i1 [[NE2]])778; CHECK-NEXT: ret i1 false779;780 %z = sub i8 0, %x781 %lb = and i8 %z, 8782 %ne = icmp ne i8 %lb, 0783 call void @llvm.assume(i1 %ne)784 %lb2 = and i8 %x, 2785 %ne2 = icmp ne i8 %lb2, 0786 call void @llvm.assume(i1 %ne2)787 %o = and i8 %z, %x788 %r = icmp eq i8 %o, 4789 ret i1 %r790}791