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1; RUN: llvm-dis < %s.bc | FileCheck %s2 3; Bitcode was generated from file below4 5define <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {6; CHECK-LABEL: @test_vbfdot_f327entry:8 %0 = bitcast <4 x bfloat> %a to <8 x i8>9 %1 = bitcast <4 x bfloat> %b to <8 x i8>10 ; CHECK: %2 = bitcast <8 x i8> %0 to <4 x bfloat>11 ; CHECK-NEXT: %3 = bitcast <8 x i8> %1 to <4 x bfloat>12 ; CHECK-NEXT: %vbfdot1.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %2, <4 x bfloat> %3)13 %vbfdot1.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %0, <8 x i8> %1)14 ret <2 x float> %vbfdot1.i15}16 17define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {18; CHECK-LABEL: @test_vbfdotq_f3219entry:20 %0 = bitcast <8 x bfloat> %a to <16 x i8>21 %1 = bitcast <8 x bfloat> %b to <16 x i8>22 ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>23 ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>24 ; CHECK-NEXT: %vbfdot1.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)25 %vbfdot1.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)26 ret <4 x float> %vbfdot1.i27}28 29define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {30; CHECK-LABEL: @test_vbfmmlaq_f3231entry:32 %0 = bitcast <8 x bfloat> %a to <16 x i8>33 %1 = bitcast <8 x bfloat> %b to <16 x i8>34 %vbfmmla1.i = call <4 x float> @llvm.aarch64.neon.bfmmla.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)35 ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>36 ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>37 ; CHECK-NEXT: %vbfmmla1.i = call <4 x float> @llvm.aarch64.neon.bfmmla(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)38 ret <4 x float> %vbfmmla1.i39}40 41define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {42; CHECK-LABEL: @test_vbfmlalbq_laneq_f3243entry:44 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>45 %0 = bitcast <8 x bfloat> %a to <16 x i8>46 %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>47 %vbfmlalb1.i = call <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)48 ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>49 ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>50 ; CHECK-NEXT: %vbfmlalb1.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)51 ret <4 x float> %vbfmlalb1.i52}53 54define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {55; CHECK-LABEL: @test_vbfmlaltq_laneq_f3256entry:57 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>58 %0 = bitcast <8 x bfloat> %a to <16 x i8>59 %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>60 %vbfmlalt1.i = call <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)61 ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>62 ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>63 ; CHECK-NEXT: %vbfmlalt1.i = call <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)64 ret <4 x float> %vbfmlalt1.i65}66 67declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float>, <8 x i8>, <8 x i8>)68; CHECK: declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)69declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)70; CHECK: declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)71declare <4 x float> @llvm.aarch64.neon.bfmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)72; CHECK: declare <4 x float> @llvm.aarch64.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>)73declare <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)74; CHECK: declare <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)75declare <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)76; CHECK: declare <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>)